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Glitches & Hazards

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Page 1: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Glitches & Hazards

Page 2: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Glitches / Hazards

Gates have an inherent delay We have been ignoring this but delays do exist

A glitch is an unwanted pulse at the output of a combinational circuit Glitches can result from gate delays Glitches depend on the input patterns glitches may not

occur if the input pattern that would cause the glitch never occurs

A circuit with the potential for a glitch has a hazard A circuit with a hazard may or may not glitch

Page 3: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Glitch Example

F = AB + A'C: assume all gate delays = 10ns

An input change from ABC = 111 to 011 results in a glitch output changes from 1 0 1 again A static hazard: result should have stayed statically at 1

Page 4: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Static & Dynamic Hazards

Static hazards:

Dynamic hazards:

1 1 0 0

1 0 0 1

1

0

1

0

Page 5: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Removing Static Hazards

Glitch occurs in moving from one implicant to another within a cover When two adjacent 1's are not covered by a single

implicant Solution: add an extra implicant to provide that coverage

F = AB + A'C + BC No longer minimum form but no hazard now

B C A

00 01 11 10

0 0 1 1 0

1 0 0 1 1

Page 6: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Hazard Removal: Example

F(A,B,C,D) = m(6,7,8,9,12,13,14,15)

The red prime implicant removes the static-1 hazard

C D A B

00 01 11 10

00 0 0 0 0

01 0 0 1 1

11 1 1 1 1

10 1 1 0 0

Page 7: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Dynamic Hazards

Dynamic hazards do not occur in two-level combinational circuits only in multi-level circuits

x 2

x 1

x 3

x 4

b

a

c d

f

x 2 x 3 x 4

x 1

b

a

c

d

f

One gate delay

Page 8: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Causes of Dynamic Hazards

For an output to change 0101 (i.e. 3 times) in response to a single input change, there must be at least 3 paths of different length in the circuit 2 gate delays: x1 b f

3 gate delays: x1 a b f

4 gate delays: x1 a c d f

x 2

x 1

x 3

x 4

b

a

c d

f

Page 9: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Removing Dynamic Hazards

Removing dynamic hazards is very difficult

Even detecting dynamic hazards is very difficult

Stick to two level designs to ensure combinational circuits do not have dynamic hazards Sequential circuits do not have this problem

Page 10: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Quine-McClusky Method

Page 11: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Quine-McClusky Method

An algorithm that CAD tools can and do use

Uses tables to: Compute all prime implicants Identify essential prime implicants Select the minimum number of prime implicants for a cover

Is based on the combining property again x y + x y' = x (y + y') = x

Page 12: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Grouping the Minterms

f(A,B,C,D) = m(0,4,8,10,11,12,13,15)

Arrange all minterms according to the number of 1’s in the binary representation

Sort and group them

These are called 0-cubes Like vertices of a 4D cube

0 0000

4 0100

8 1000

10 1010

12 1100

11 1011

13 1101

15 1111

Page 13: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Forming 1-cubes

Compare each 0-cube in one group with each 0-cube in an adjacent group Use combining property to form 1-cubes

0 cubes

0 0000 X

4 0100 X

8 1000 X

10 1010 X

12 1100 X

11 1011 X

13 1101 X

15 1111 X

1 cubes

0,4 0x00

0,8 x000

8,10 10x0

4,12 x100

8,12 1x00

10,11 101x

12,13 110x

11,15 1x11

13,15 11x1

Page 14: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Forming 2-cubes

Compare each 1-cube in one group with each 1-cube in an adjacent group Use combining property to form 2-cubes

2 cubes

0,8,4,12 xx00

1 cubes

0,4 0x00 X

0,8 x000 X

8,10 10x0

4,12 x100 X

8,12 1x00 X

10,11 101x

12,13 110x

11,15 1x11

13,15 11x1

mark each 1-cube that contributes to a 2-cube

Page 15: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

The Prime Implicants

All “unchecked” cubes are prime implicants They did not get combined into a larger cube

2 cubes

0,8,4,12 xx00

1 cubes

0,4 0x00 X

0,8 x000 X

8,10 10x0

4,12 x100 X

8,12 1x00 X

10,11 101x

12,13 110x

11,15 1x11

13,15 11x1

0 cubes

0 0000 X

4 0100 X

8 1000 X

10 1010 X

12 1100 X

11 1011 X

13 1101 X

15 1111 X

All prime implicants are:

P = { 10x0, 101x, 110x, 1x11, 11x1, xx00 }

Page 16: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Prime Implicant Cover Table

For each prime implicant, mark all minterms covered by that implicant

prime minterms

implicants 0 4 8 10 11 12 13 15

p1 10x0 X X

p2 101x X X

p3 110x X X

p4 1x11 X X

p5 11x1 X X

p6 xx00 X X X X

Page 17: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Find Essential Prime Implicants

p6 is an essential prime implicant minterms 0 and 4 must be covered by p6 Minimum cover C = { p6 } at the moment

prime minterms

implicants 0 4 8 10 11 12 13 15

p1 10x0 X X

p2 101x X X

p3 110x X X

p4 1x11 X X

p5 11x1 X X

p6 xx00 X X X X

Page 18: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Row Dominance

p2 row dominates p1 since p2 covers everything that p1 covers p1 can be eliminated

Note: we remove the dominated row

prime minterms

implicants 10 11 13 15

p1 10x0 X

p2 101x X X

p3 110x X

p4 1x11 X X

p5 11x1 X X

p5 row dominates p3

Page 19: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Column Dominance

Column 11 column dominates column 10 since everything that covers column 10 also covers column 11 Column 11 can be eliminated

Note: we remove the dominating column

We could also have considered p2 and p5 as essential at this point

prime minterms

implicants 10 11 13 15

p2 101x X X

p4 1x11 X X

p5 11x1 X X

column 15 dominates column 13

Page 20: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Final Cover

The final cover is C = { p6, p2, p5 }

f = xx00 + 101x + 11x1 = C'D' + AB'C + ABD

prime minterms

implicants 10 13

p2 101x X

p4 1x11

p5 11x1 X

Page 21: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Another Example

f(A,B,C,D) = m(0,2,4,5,6,7,8,10,11,12,15)

0 cubes

0 0000

2 0010

4 0100

8 1000

5 0101

6 0110

10 1010

12 1100

7 0111

11 1011

15 1111

Page 22: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Cubes

2 cubes

0,2,4,6 0xx0

0,2,8,10 x0x0

0,4,8,12 xx00

4,5,6,7 01xx

1 cubes

0,2 00x0 X

0,4 0x00 X

0,8 x000 X

2,6 0x10 X

2,10 x010 X

4,5 010x X

4,6 01x0 X

4,12 x100 X

8,10 10x0 X

8,12 1x00 X

5,7 01x1 X

6,7 011x X

10,11 101x

7,15 x111

11,15 1x11

0 cubes

0 0000 X

2 0010 X

4 0100 X

8 1000 X

5 0101 X

6 0110 X

10 1010 X

12 1100 X

7 0111 X

11 1011 X

15 1111 X

All prime implicants are:

P = { 101x, x111, 1x11, 0xx0, x0x0, xx00, 01xx }

Page 23: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Cover Table

C = { p6, p7 } since p6 and p7 are essential

prime minterms

implicants 0 2 4 5 6 7 8 10 11 12 15

p1 101x X X

p2 x111 X X

p3 1x11 X X

p4 0xx0 X X X X

p5 x0x0 X X X X

p6 xx00 X X X X

p7 01xx X X X X

Page 24: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Row Dominance

Row p5 dominates row p4 Row p3 dominates row p2

prime minterms

implicants 2 10 11 15

p1 101x X X

p2 x111 X

p3 1x11 X X

p4 0xx0 X

p5 x0x0 X X

Page 25: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Column Domination

Column 10 dominates column 2 Column 11 dominates column 15

Final min cover is C = { p6, p7, p3, p5 } f = xx00 + 01xx + 1x11 + x0x0

= C'D' + A'B + ACD + B'D'

prime minterms

implicants 2 10 11 15

p1 101x X X

p3 1x11 X X

p5 x0x0 X X

Page 26: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Handling Don't Cares

f(A,B,C,D) = m(0,3,10,15) + d(1,2,7,8,11,14)

Don't care conditions areused for creating the prime implicants

Don't care conditions arenot used for computing theminimum cover

0 cubes

0 0000

1 0001

2 0010

8 1000

3 0011

10 1010

7 0111

11 1011

14 1110

15 1111

Page 27: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Cubes

0 cubes

0 0000 X

1 0001 X

2 0010 X

8 1000 X

3 0011 X

10 1010 X

7 0111 X

11 1011 X

14 1110 X

15 1111 X

1 cubes

0,1 000x X

0,2 00x0 X

0,8 x000 X

1,3 00x1 X

2,3 001x X

2,10 x010 X

8,10 10x0 X

3,7 0x11 X

3,11 x011 X

10,11 101x X

10,14 1x10 X

7,15 x111 X

11,15 1x11 X

14,15 111x X

2 cubes

0,1,2,3 00xx

0,2,8,10 x0x0

2,3,10,11 x01x

3,7,11,15 xx11

10,11,14,15 1x1x

All prime implicants are:

P = { 00xx, x0x0, x01x, xx11, 1x1x }

Page 28: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Cover Table

Include only required minterms in the initial cover table

There are no essential prime implicants

prime minterms

implicants 0 3 10 15

p1 00xx X X

p2 x0x0 X X

p3 x01x X X

p4 xx11 X X

p5 1x1x X X

Page 29: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Branching

There are no dominant rows and no dominant columns

Require a branching strategy Backtracking type algorithm

Select C = { p1 } prime minterms

implicants 0 3 10 15

p1 00xx X X

p2 x0x0 X X

p3 x01x X X

p4 xx11 X X

p5 1x1x X X

Page 30: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Min Cover That Includes p1

Row p5 dominates rows p2, p3, and p4 Min cover C = { p1, p5 }

f = 00xx + 1x1x = A'B' + AC Cost = 3 + 6 = 9

prime minterms

implicants 10 15

p2 x0x0 X

p3 x01x X

p4 xx11 X

p5 1x1x X X

Page 31: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Backtrack

Now backtrack and eliminate p1 to find covers

prime minterms

implicants 0 3 10 15

p1 00xx X X

p2 x0x0 X X

p3 x01x X X

p4 xx11 X X

p5 1x1x X X

prime minterms

implicants 0 3 10 15

p2 x0x0 X X

p3 x01x X X

p4 xx11 X X

p5 1x1x X X

Column 10 dominates column 0

Page 32: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Min Cover That Excludes p1

Row p4 dominates rows p3 and p5 Min cover C = { p2, p4 } f = x0x0 + xx11 = B'D' + CD

Cost = 3 + 6 = 9 Same cost as other solution!

prime minterms

implicants 0 3 15

p2 x0x0 X

p3 x01x X

p4 xx11 X X

p5 1x1x X

Page 33: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Factoring and Decomposition

Page 34: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Factoring

Two level logic is good for problems with only a few variables and/or limited fan-in to all gates Factoring can be used to reduce fan-in, but results in > 2

level logic

Ex: f(A,B,C,D,E,F) = AB'CD'EF + ABC'D'E'F

Requires two 6 input ANDs, one 2 input OR If only 4 input AND gates are available then we can factor f

into f(A,B,C,D,E,F) = AD'F(B'CE + BC'E') Requires one 4 input AND, two 3 input ANDs, one 2 input OR

Requires 3 level logic multi-level synthesis

Page 35: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Multi-level Synthesis

If fan-in is limited to at most 4, then the original two level circuit could be done as ….

The factored circuit could be done as …

cost = 5 + 16 = 21

cost = 4 + 12 = 16

cascading ANDs

Page 36: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Functional Decomposition

Multi-level circuits may sometimes be preferred over two-level circuits due to reduced cost Done at the expense of longer delays

Decompose circuits into subcircuits with shared functionality Shared subcircuits provide reduced total cost

Page 37: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Example Functional Decomposition

SOP form: f = A'BC + AB'C + ABD + A'B'D cost = 5 + 16 = 21 + 2 inverters + 2 fan-in = 25

factoring …

f = (A'B + AB') C + (AB + A'B') D

= g C + g' D where g = A'B + AB'

since g' = (A'B + AB')' = (A'B)'(AB')' = (A+B')(A'+B)

= AA' + B'A' + AB + B'B = AB + A'B'

Page 38: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Implemented Decomposition

cost = 6 + 12 + 3 inverters + 3 fan-in = 24

Page 39: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Another Example

The shaded region is g(X,W) = XW' + X'W f(V,W,X,Y,Z) = g (V+Y+Z) + g' (V+Y+Z)' = g h + g' h'

Y Z W X

00 01 11 10

00 0 0 0 0

01 1 1 1 1

11 0 0 0 0

10 1 1 1 1

Y Z W X

00 01 11 10

00 1 0 0 0

01 0 1 1 1

11 1 0 0 0

10 0 1 1 1

V = 0 V = 1

Page 40: Glitches & Hazards. Glitches / Hazards  Gates have an inherent delay We have been ignoring this  but delays do exist  A glitch is an unwanted pulse

Implementation

cost = 11 + 19 = 30

minimal SOP cost = 55 (includes inverters)