g list of examples - springer978-0-306-47658-7/1.pdfg list of examples a gate-level ......

G LIST OF EXAMPLES

A gate-level description of edge-sensitive d flip-flop 23334

5679

13

A 4-bit counter built using instances of d flip-flop defined in Figure 1 -1Example 1-1.Example 1-2.Example 1-3. Schematics for dff in 1-1Example 1-4. Schematic for counter in 1-2Example 1-5. Behavioral description of the same counter as in 1-2Example 1-6. A test module for testing the two descriptions of counter and their

equivalenceExample 1-7. Waveforms for the counter exampleExample 1-8. Factorial generation of a numberExample 1-9. A system model with microprocessor, ram, and cache controllerExample 1-10. Behavioral description of a cache controller with write-through scheme

Example 2-1. Data declarationsExample 2-2. Reg declarationsExample 2-3. Wire declarations

232425

Example 2-4. Wand (wired-AND) declarations and usageExample 2-5. wor (wired-OR) declarations and usage

2526

Example 2-6. Tri (Three-State) declarations and usage 27Example 2-7. Nets of tri types declared and used for multiple drivers with tri-state

resolution 27Example 2-8. supply0 and supply1 constructs 27Example 2-9. Trireg net and the switch-level modeling example 28Example 2-10. Net type declarations 29Example 2-11. Port type declarations 30Example 2-12. Aggregate declarations 31Example 2-13.Example 2-14.Example 2-15.Example 2-16.Example 2-17.

Vectored and scalared bit-vector net declarations 31Memory declarations 31Net declarations with delay specifications 32Integer and time declarationsReal declarations

3333

452 Appendix F

Example 2-18Example 2-19.

Parameter declaration examples 34Hierarchical names 35

Example 3-1. Levels of abstractions 3839414142

Example 3-2. Behavioral level of abstraction – adderExample 3-3. Two equivalent continuous assignmentsExample 3-4. RTL abstractions – adderExample 3-5. RTL abstractions – adder with boolean optimizationsExample 3-6. Continuous assignments – RTL modeling 43Example 3-7.Example 3-8.Example 3-9.Example 3-10.Example 3-11.Example 3-12.Example 3-13.

Addition operation 46Relational operators 46Equality operator 47Logical operators 47Bit-wise operators 48Reduction operators 48Shift operator 49

Example 3-14. Conditional operator 49Example 3-15. Nested conditional operator 50Example 3-16. Concatenation operator 50Example 3-17.Example 3-18.Example 3-19.Example 3-20.Example 3-21.Example 3-22.Example 3-23.

Concatenation equivalent 50Different representations of constant 10 in Verilog 52Wire operands 52Bit-select operands 52Part-select operands 53Function call used as an operand 53Concatenation of operands 53

Example 3-24. Constant valued expressions 55Example 3-25. Examples of operator usage 56Example 3-26. Different ways to perform sized operations 57Example 3-27.Example 3-28.Example 3-29.Example 3-30.Example 3-31.Example 3-32.Example 3-33.Example 3-34.

Example 3-35.

Example 4-1.Example 4-2.Example 4-3.Example 4-4.

Example 4-5.

Example 5-1.Example 5-2.

Datapath design using continuous assignments RTL abstractions 62Structural design – A CPU with details of adder at the gate-level 63Example of parametrized module definitions 65Example of a macromodule construct 65Named ports in modules 66Module instantiations 68Module definitions and instantiation – hierarchical design example 68A structural model of R4200 processor with declarations andinstances at top-level 71A structural model of UltraSPARC-IIi 81

A sample design with structure and behavior 86Log of a typical simulator with tracingIdeal simulation log for a sample circuit with tracing 90Multiple events on a reg – but no cancellation(algorithm 4-7 applied) 96Multiple events on a reg resulting cancellation(algorithm 4-7 applied) 97

Behavioral clock generation 100Blocking assignments – inter-assignment delays 101

FORMAL SYNTAX DEFINITION OF SDF 453


Example 5-7.

Blocking Assignment – intra-assignment delays 102Blocking assignments – interassignment delays 103Blocking assignments – intra-assignment delays 104Blocking and non-blocking comparison – exchange ofvalues for blocking 105Blocking and non-blocking comparison – no exchange ofvalues for blocking 105

Example 5-8. Blocking assignments – multiple schedules 106Example 5-9.Example 5-10.Example 5-11.Example 5-12.Example 5-13.

Blocking assignments – no multiple schedules 106

Example 5-14.Example 5-15.Example 5-16.Example 5-17.Example 5-18.Example 5-19.Example 5-20.Example 5-21.Example 5-22.Example 5-23.Example 5-24.Example 5-25.Example 5-26.Example 5-27.

Example 5-28.Example 5-29.Example 5-30.Example 5-31.Example 5-32.Example 5-33.Example 5-34.Example 5-35.

Example 5-36.

If statement exampleNested if statementIf-else-if mutually exclusive multiple conditions

107107108108109110111111112112112113113114114115115

118118119119120120121123

124125132

136139

142143

145146Example 6-6.


Example 6-3.Example 6-2.Example 6-1.

Example 5-37.

User-defined primitives – instances

Mixed edge and level sensitive sequential UDP – SR flip-flopwith clear

Level sensitive sequential UDP – a latch

A combinational user–defined primitive: An adder part –carry computation

A user-defined primitive definitionBuilt-in gates modeling

A behavioral processor modelForce-release statements – debugging the flip-flop model

Aassign – deassign – a flip-flop model with quasi-continuousassignments

Task disabling – reset modeling for a microprocessorTask declaration and usage – a shift registerFunction call – creating a multiplexor module with function muxFunction definition – a muxModeling instructions with pipeline – fork-join usageModeling instructions with parallelismModeling instructions with no parallelism

Fork-join statements – modeling asynchronous reset andinstruction loop concurrency in microprocessors

Event triggering and event based synchronizationMulti-event eventEvent declarationsEvent declarations and usageWait statement – synchronizing two processesSequential blocks – begin-end usageLoops – forever statement usageLoops – repeat statement usageLoops – while statement usageLoops – for statement usageCase statement with unknowns and tri-statesCasex statement with unknowns and tri-statesCase statement with unknowns and tri-statesCase statement – a multiplexor model

454 Appendix F


Example 7-3.



Comparisons of different levels of abstraction by mixed level designSystem modeling with behavioral, rtl, gates and switches mixedin one board design

152

153A behavioral flag-bit generation mixed with adder of rtl orstructural style 153

$display usage with different methods of capturing design data 156Capturing simulation results of a design selectively with$monitor and $monitoron/off 159File management in capturing results of simulating a design 161Reading input from files – $readmem usage 162Simulation control tasks – $stop and $finish 163Creating a waveform data file using $dumpvars and relatedsystem tasks 164

Example 9-1. `include compiler directiveExample 9-2.

Example 9-3.

Example 11-1.

Example 11-2.


Example 11-5.

Example 11-6.

168Compiling code conditionally based on prior macro definitionsusing `ifdef 170default_nettype compiler directive 170

8085 microprocessor, ram, and 8251 serial IO controller system –behavioral model 183R4200 microprocessor with instructions, bus-cycles, and registers –behavioral model 215A cache system with a write-through policy; behavioral abstraction 222Cache system with a write-back policy: behavioral model –refinement of Example 11-3 229A register transfer level model of the cache system with write-throughpolicy: with blocks 236Detailed model of a cache controller with write-through policy 242


Example 13-1.Example 13-2.Example 13-3.Example 13-4.Example 13-5.Example 13-6.

Synthesizable combinational adder 249Synthesizable combinational multiplexor 249Synthesizable sequential design – traffic light controller 250Synthesizable parts of the cache system – cache control (sequential),mux, compare 253

Parametrized design 259Instantiating a parameterized design in your Verilog code 259Gate-level instantiations 260Three-state gate instantiation 261Synthesis and comparisons to X 262Synthesizable combinational 4-bit adder using functions andcontinuous assignments 262

Example 13-7.Example 13-8.Example 13-9.Example 13-10.Example 13-11.Example 13-12.

Synthesizable combinational multiplexor 263A behavioral description with feedback that is not real 264Memory declarations – synthesized as bank of registers 264Accessing bits within a memory block 265Parameter declaration in a function 265if statement that synthesizes multiplexor logic 267

FORMAL SYNTAX DEFINITION OF SDF 455

Example 13-13.Example 13-14.Example 13-15.Example 13-16.Example 13-17.Example 13-18.Example 13-19.Example 13-20.Example 13-21.Example 13-22.

if...else if...else structure with several mutually exclusive conditions 267Nested if and else statements 268Synthesizing a latch for a conditionally-driven variable 268A case statement that is both full and parallel 269A non-full but parallel case statement – synthesized with latches 269A case statement that is neither parallel, nor fullExample of synthesizable simple for loop

270270

Example of nested for loops that can be synthesized 271For loop used for duplicating statements 271Equivalent expansion of for loop in Example 13-20 271

Example 13-23.Example 13-24.Example 13-25.Example 13-26.Example 13-27.Example 13-28.Example 13-29.Example 13-30.Example 13-31.

Unsupported while loop 271Supported while loops 272Supported forever loopLoop exiting using disable – a comparator model

272273

Synchronous reset of state register using disable in a forever loop 273Using tasks to describe synthesizable combinational logic 274A simple always block describing synthesizable combinational logic 274Event expression indicating sensitivity or input to a block 275Event expression indicating rising edge of clock 275

Example 13-32. Falling clock edge modeled in event-expression 275Example 13-33. Event expression modeling clock-edge combined with

resetting condition 275Example 13-34.Example 13-35.Example 13-36.

Incomplete event list – simulation and synthesis may mismatch 276Complete event list 276Incomplete event list for edge-triggered flip-flop withasynchronous reset 276

Example 14-1.Example 14-2.Example 14-3.Example 14-4.Example 14-5.Example 14-6.Example 14-7.Example 14-8.Example 14-9.

Creating a latch 280Creating a latch with a case statement 280Variable declared within a function-no latches inferred 281Creating an edge-triggered D flip-flop 281Flip-flop with asynchronous reset 282Flip-flop with synchronous resetAsynchronous set/reset on a design

283284

Synchronous set/reset on a design 284Using one_hot for set and reset 285

Example 14-10.Example 14-11.Example 14-12.Example 14-13.Example 14-14.Example 14-15.Example 14-16.Example 14-17.Example 14-18.Example 14-19.Example 14-20.Example 14-21.

Using one_cold for set and reset 286Creation of a bus-latch 286An 8-1 multiplexer modeled behaviorally and synthesized to a mux 287A 3-state gate created behaviorally 288A 3-state gate with 2 drivers 288Creation of two 3-state gates with independent controls 288Three-state with registered enable 289Three-state without registered enable 289Sharing of adder resources 291Shared resources have independent paths 292Case statement sharing 292Sharing may result in feedback loop 293

456 Appendix F

Example 15-1.Example 15-2.Example 15-3.Example 15-4.Example 15-5.Example 15-6.Example 15-7.Example 15-8.Example 15-9.Example 15-10.Example 15-11.Example 15-12.

Timing checks and path delay specifications in specify blocks 296Specify block example – timing checks on module pins 300Specify blocks – simple paths from input to output 300Edge-sensitive paths with sensitivity to positive clock edges 301State dependent path delay specifications: example statements 302State dependent path delay specifications – a full module 302Edge sensitive state dependent path delays 303Multiple edge and state delay specifications for the same simple path 303Illegal state dependent delay specificationifnone statements in a state dependent specification 303ifnone statement – opcode dependent delays for execution unit 304Delay specifications – one delay for all cases and a min-typ-maxspecification 304

Example 15-13. Two, three, six, and twelve different delays for the same path 305


Unidirectional transistors: a dynamic mos serial shift register 317Bidirectional transistors and modeling with strengths –a static ram cell 319


Analog resistor described in Verilog’s analog extensions 366Electrical type declarations in analog or mixed signal modules 366Example of analog block 367Mixed signal design with Verilog MS 369

303

H REFERENCES

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.12.

13.

14.

15.

16.

The IEEE 1364-1995 Verilog Language Reference Manual, IEEE Standards Press, 1995.

Digital Design with the Verilog HDL -by Vivek Sagdeo, Class Notes – UC Berkeley Ext,1996

Designing with Verilog – Class Notes by Vivek Sagdeo, PerformanCAE CorporationTraining

SDF 3.0 Reference Manual, Open Verilog International, May 1995

Semantic Model for Verilog HDL by Vivek Sagdeo PerformanCAE Corporation - InternalPapers

Analog Design with Verilog-A –I Miller et al, IVC 97 Proceedings, 1997.

Verilog-A Language Reference Manual, OVI1996

Verilog Support for Cycle-Based Simulation – Speedsim Inc., 1996

Open Model Interface Draft Standard V1.0, CFI – http://www.cfi.org/OMF/, 1997

DCL Proposal, CFI 1997

R4200 Microprocessor Reference Guide, MIPS Technologies Inc, 1995

comp.lang.verilog newsgroup archives – 1997

http://www.veri-log.com PerformanCAE Corporation Web Site

Synthesis Subsets-Descriptions from Synopsys, Synplicity, Exemplar Logic, and SiliconAutomation Systems

OVI Directory for Verilog, 1996

DAC Proceedings –1986-1996

INDEX

-,44,51

!,44!=,44,51

$display, 156$dumpfile, 163$dumpoff, 163$dumpon, 163$dumpvars, 163$fclose, 160, 161$fdisplay, 161$finish, 162$fmonitor, 161$fopen, 160$fstrobe, 160, 161$fwrite, 161$gr_waves, 174$hold, 297$keys, 174$log, 174$monitor, 158$period, 298$readmemb, 161$readmemh, 162$recovery, 298$setup, 297$setuphold, 299$showvars, 174$skew, 298$stop, 162$time, 162$width, 297

%, 44,51%b, 157%d, 157%e, 157%g, 157%m, 157%o, 157

%s, 157%t, 157%v, 157

&, 44, 51&&, 44, 51

*, 44

/, 44, 51

?, 51?:, 45?:, 51

^, 44, 45, 51^~, 44, 51

`default_nettype, 170`define, 168èlse, 169èndif, 170ìfdef, 170ìnclude, 168`resetall, 171t̀imescale, 171ùndef, 169

{ }, 44{},51

|, 44, 45, 51||, 51

~ 44~&, 45~^, 45-|, 45

+, 44, 51

460 INDEX

<, 44, 51<<, 45, 51<=, 44, 51

=, 44, 51==, 44, 51

>, 44, 51>=, 44, 51>>, 45, 51

128-state types, 21

4-state values, 21

8085 Based System : Sio85.V, 1778251 serial io controller, 183

A

A Register transfer level model of thecache, 236

Abstraction Levels, 37, 38acc routines, 309Aggregates, 31Algorithm, 94algorithmic style, 99always, 100and, 136architectural, 15, 243Arithmetic Operators, 44ASIC library, 255Assign, 123Assignments, 101

B

Begin-End, 112Behavioral Abstractions, 39behavioral descriptions, 100Behavioral Synthesis, 243bits, 21Bit-Selects, 52bit-vectors, 21block diagram of r4200, 69blocking assignments, 101Boolean Operators, 44Boolean/conditional values, 22Bottom up methodology, 14Browser, 174buf, 136

bufif0, 136bufifl, 136built-in gates, 136

C

Cache Design, 217called continuous assignments, 40Case, 108Casex, 109casez, 109character strings, 22Class A, 248clock generation, 100cmos, 138Combinational UDPs, 141Commands, 174Compiler Directives, 167Concatenation, 44concurrent processes, 95Conditional Paths, 302Conditional Statement, 107constant-valued expression, 55constraints, 243continuous assignment, 41Control flow modeling, 39Counter, 2

D

Data Declarations, 22Data Types, 21Datapath design, 62debugging, 125default, 108define, 168defparam, 34Delay Specifications, 304delay values, 22delays, 32Design Cycle, 154Design Flow, 15, 243designer driven resource sharing, 293disable, 122Display System Tasks, 156double specification, 305

E

Edge Sensitive Sequential UDPs, 143else, 170

INDEX 461

end, 112endcase, 108endfunction, 119endmodule, 64endprimitive, 138endspecify, 296endtable, 138endtask, 119equal to, 44Evaluate Events, 90Evaluation Event, 92Event, 92, 114Event Declaration, 34Event declarations, 114Event Driven Simulation, 90Event Generalization, 116Event OR, 115event triggering, 115Expressions, 43

F

factorial generation, 7fdisplay, 161fdisplayb, 161fdisplayh, 161fdisplayo, 161File Input, 161File Management, 160Flip-Flop Inference, 281floating point types, 21for, 111for Task Enabling, 122Force, 124forever, 111Fork-Join, 117formal syntax definition conventions, 18fstrobeh, 161fstrobeh, 160, 161Full Analysis, 87Full Case, 268Functions, 119fwriteb, 160, 161

G

Gates, 135ground, 27

H

H, 135Hierarchical Names, 35highz0, 138highzl, 138Hold, 297

I

if, 107ifnone, 303inertial delay model, 95initial, 100inout, 30input, 29instantiations, 67Integer And Time, 33integers, 21Intel, 177Interactive Simulation, 173inter-assignment delays, 102Internal Data Structure, 90intra-assignment delays, 102IVC, 1

K

keywords, 17

L

L, 135large, 28latch inference, 279Level-Sensitive Sequential UDPs, 142lexical conventions, 18Log Of A Typical Simulator, 87Log Of An Ideal Simulator, 88Logic Synthesis, 243logic values, 21Logical Operators, 44Loops, 111

M

Macromodules, 65mapping, 243Mealy machine, 248medium, 28memories, 31Microprocessor, 125

462 INDEX

Mips, 67Mixed Level and Edge Sensitive

Sequential UDPs, 144Mixed Modeling, 151Model Execution, 93Modeling Pipelines, 118Modern view, 248Module Definitions, 64Module Instantiation, 67Monitor System Tasks, 158Multi-driver Nets, 305Multi-Event Event, 115

N

named ports, 66nand, 136negedge, 117net, 24Network Representation, 92nmos, 138non-blocking assignments, 103non-determinism, 91non-synthesizable code, 256nor, 136not, 136not equal to, 44notif0, 136notifl, 136Numbers, 51

O

Open Verilog International, 1operands in expressions, 51Operator Precedence, 56Operators, 46Operators on Reals, 55optimize design, 243or, 136output, 29

P

Parallel Case, 268parallelism, 118parameter, 22, 34Part-Selects, 52Path, 300Period, 298Pin Timing, 295

pipelines, 118PLI, 307pmos, 138Port Types, 29posedge, 117power supply, 27precedence of operators, 56Primitive, 138Process or Evaluation Block, 92processing an event, 94Programming Language Interface, 307Project Planning, 154pull0, 138pull1, 138pulldown, 136, 138pullup, 136, 138Pulse Specification, 305

Q

quasi-continuous assignment, 123

R

R4200, 183ram, 183range, 31rcmos, 137Real, 33Real Declaration, 33Recovery, 298Reg Declaration, 23register inference, 279Register Transfer Level Abstractions, 40Relational Operators, 44Release, 124repeat, 111resistive transistors, 138Resource sharing, 290retargetting, 243rnmos, 138rpmos, 138rtran, 138rtranif0, 138rtranifl, 138Rules for the Delay Models in SDF, 361

S

Sagdeo machine, 248scalared, 32

INDEX 463

sdf TIMINGCHECK, 341sdf TIMINGENV, 350sdf VENDOR, 326sdf VERSION, 326sdf VOLTAGE, 327sdf WAVEFORM, 357SDFVERSION, 325Semantic Model, 85sequential statements, 99Setup, 297Shift Operators, 44Signal, 92simple paths, 300Simulation Control Tasks, 162Simulation Time Functions, 162small, 28Specify Blocks, 295specparam, 302Standard Delay Format, 321State-dependent paths, 301stepwise refinement, 16, 244stime, 162strong0, 138strong1,138Structural, 135structural model of R4200, 71SUN, 67supply0, 24,138supplyl, 24, 138Switch Declarations, 137Switches, 138synchronization primitives, 99syntax conventions, 18Synthesis, 243Synthesis Components, 246synthesis subset, 255synthesizable bus latch, 286synthesizable disable, 272synthesizable event specification, 276synthesizable forever loop, 272synthesizable Task statements, 273synthesizable adder, 249synthesizable behavioral statements, 265synthesizable Behavioral Constructs, 262synthesizable case statement, 268synthesizable continuous assignments,

258synthesizable declarations, 257synthesizable gates, 259synthesizable if, 267

Schedule, 92scheduling an event, 95Schematic for counter, 3Schematics for dff, 3sdf ABSOLUTE, 331sdf ARRIVAL, 354sdf CELL, 329sdf CELLTYPE, 329, 341sdf COND, 337sdf CONDELSE, 337sdf DATE, 326sdf DELAY, 330sdf delay model, 361sdf DELAYFILE, 324sdf delval, 335sdf DEPARTURE, 354sdf DESIGN, 326sdf DEVICE, 340sdf DIFF, 352sdf DIVIDER, 327sdf File Examples, 359sdf header, 325sdf HOLD, 344sdf INCREMENT, 331sdf INSTANCE, 330, 332sdf INTERCONNECT, 339sdf IOPATH, 335sdf NOCHANGE, 349sdf PATHCONSTRAINT, 350sdf PATHPULSE, 332sdf PATHPULSEPERCENT, 333sdf PERIOD, 348sdf PERIODCONSTRAINT, 351sdf PORT, 339sdf PROCESS, 328sdf PROGRAM, 326sdf RECOVERY, 345sdf RECREM, 347sdf REMOVAL, 346sdf RETAIN, 338sdf SETUP, 344sdf SETUPHOLD, 345sdf SKEW, 347sdf SKEWCONSTRAINT, 353sdf SLACK, 355sdf SUM, 352sdf temperature, 328sdf timescale, 328sdf Timing Checks, 323sdf Timing Models, 323

464 INDEX

synthesizable multiplexer, 249Synthesizable Operand Types, 261synthesizable parameterized designs, 258Synthesizable parts of the cache system,

253synthesizable structure, 256synthesizable three-state gates, 260synthesizable while loop, 271Synthesizable wire types, 257synthesizer driven resource sharing, 294Synthesizer ignores delay, 258System Examples, 177system model, 9System Modeling, 152System Tasks, 155

T

table, 139Tasks, 121technology dependent., 247technology independent, 247tf routines, 309The Programming Language Interface,

307three-state gate-inference, 287time, 33Timing Checks, 296Top-Down Methodology, 14Traditional View, 248Traffic Light Controller, 250tran, 138tranif0, 138tranifl, 138Transistors, 315transition values, 22transport delay model, 97tri, 24tri0, 24tril, 24triand, 24

trior, 24trireg, 24

U

UDP Instances, 145UltraSPARC-IIi, 81, 82Unary Operators, 44units, 22Update Event, 90, 92User Defined Primitives, 138

V

Value Systems, 21vdd, 27vectored, 32Verilog objects, 92vpi routines, 309vss, 27

W

Wait, 113Wait Statements, 113wand, 24Waveform Interface, 163Waveforms for the counter, 6weak0, 138weakl, 138while, 111Width, 297wire, 24wor, 24write-back policy, 223Write-Through Policy, 217, 222

X

xnor, 136xor, 136

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