FX to FX2: A Comparison

Agenda

• Block diagram

• Evolution

• Hardware

• Firmware

• Wrap-up

Address (16)8051 Core24/48 MHz,

4 clocks/cycle

CYSmartUSB

Engine

12 MHzXTAL

I/O Ports (40)

4 KB /8KBRAM

Add

ress

(16

) / D

ata

Bus

(8)

X4PLL

I2CCompatibl

e

Four64 bytes

FIFO

8/16bits

Data(8)

DMA Engine

EZ-USB FX

USB1.1

XCVR

D+

D-

Uses Low-Cost CrystalHigh Performance Micro

Using Standard Tools

Memory Expansion or

Data Buffer Ports

Peripheral I/O Flexibility

1K Double-Buffer Isochronous Support

"Soft Configuration” Easy Firmware Changes

Enhanced USB Core Simplifies 8051 Code

Master or Slave Operation

Abundant I/OIncluding 2 UARTS

Up to 48 MBytes/sBurst Rates

GPIF

General Programmable I/F to any ASIC/DSP or bus

standards such as ATAPI, EPP, etc.

2 KBFIFO

EZ-USB FX Block Diagram

EZ-USB FX2Block Diagram

24 MHz XTAL

Uses Low-Cost Crystal

High Performance Micro Using standard tools with

low power options

Memory Expansion or Data Buffer

Ports

Peripheral I/O Flexibility

"Soft Configuration” Easy Firmware Changes

Enhanced USB Core Simplifies 8051 Code

FIFO and Endpoint Memory (Master or Slave Operation)

Abundant I/O Including 2 UARTS

General Programmable Interface to any

ASIC/DSP or bus standards such as ATAPI, EPP, etc.

8051 Core 12/24/48 MHz4 clocks/cycle

CY Smart USB

Engine

8.5kB RAM

Add

ress

(1

6)

/ D

ata

Bu

s (8

)X20 PLL

4kBFIFO

EZ-USB FX2

USB 2.0

XCVR

D+

D-GPIF

ADDR (9)

connectfor fullspeed

1.5k

Vcc

I2C - Compatible

Master/0.5 /1.0 /2.0

Additional I/Os (24)

Data (8)

Address (16)

RDY (6)CTL (6)

8/16

EZ-USB FX2Architectural Evolution

EndpointFIFOS

MicroprocessorOutsideWorld

(a) USB 1.1 Full Speed

USB

EZ-USB

EndpointFIFOS

Microprocessor

(c) USB 2.0--no time wasted transferring databetween FIFOS

OutsideWorld

USB

RAM/FIFO access

(36 kilobits)

EZ-USB FX2

EndpointFIFOS

USB

Microprocessor

DMAInterface

FIFO

(b) USB 1.1 Full Speed

OutsideWorld

RAM/FIFO access

(24 kilobits) (2 kilobits)

EZ-USB FXcontrol

FX to FX2Hardware - General

• Not pin compatible

• Internal resistor for DISCON pin

• Programmable WAKEUP with multiple sources

• Firmware SUSPEND

• Finally 115k and 230k baud internally with dedicated pins

FX vs. FX2Hardware - General

Parameter FX FX2Mechanical Pkg(s) 52, 80, 128 56, 100, 128

PIN Assignments PINS do NOT match w/ FX2 Pins do NOT match w/ FX

External Crystal 12MHz +/- 2000ppm series resonantnetwork, 1M ohm resistor, 27-33pf(5%) load capacitors operating in

fundamental mode.

24MHz +/- 100ppm parallel resonant network,27-33pf (5%) load capacitors operating in

fundamental mode.

RESET – RC Network ~ 100msec (needs to be ~ 10msec), troublemeeting USB spec. I think this is to

overcome an issue w/ voltage regulator andhope not chip.

USB DISCON 1.5k D+ pull-up External, typically controlledvia DISCON pin

Internal, no DISCON pin

USB CONNECT / DISCONNECTDefault State

has the ability to come up eitherconnected or disconnected

does NOT have the ability to immediatelycome up DISCONNECTED (to be added in Rev B.

silicon, w/ EA=1), the default isCONNECTED... set in SEE

Ext. WAKEUP pin(s)Programmable Polarity

fixed WAKEUP# signal assertpolarity

programmable WAKEUP source polarity,ability to enable/disable D+, WAKEUP, WU2

Ext. WAKEUP source(s) one external WAKEUP source and D+ two external WAKEUP source pins and D+,shared PA3/WU2 port pin... supports

periodic wakeup feature

Entering SUSPEND mode, whennot connected to USB

Needs 'J' state on D+/D- to enterSUSPEND, when not connected to

USB

does NOT need 'J' state on D+/D- to enterSUSPEND, when not connected to USB... new

register SUSPEND

FX vs. FX2Hardware - General

Parameter FX FX2UART230 can NOT achieve near 0% error

at 115k/230k baud (UART230Errata)

can achieve near 0% error at 115k (set 8051bit) and 230k baud via register setting

UART0/1 Availability 52 pin part does have UART0 56 pin part does not have serial ports

I/O pin(s) sink/source I/O pins can sink/source 4mA (50mA max partconsumption)

I/Os 5v Tolerant 5v tolerant I/O's 5v tolerant I/O's

I/Os Hysteresis all pins (as inputs) have hysteresis

8051 RD# / WR# Pull-ups pull-ups on RD# / WR# pull-ups on RD# / WR#

I2C Pull-ups pull-ups on SCL/SDA Needs pull-ups on SCL/SDA (verify drivermin resistor value (1k ohm) - add to

datasheet)

AUTODATA Register(s)Location Program MemoryHole(s)

One AUTODATA Register (can’tdisable)

Two AUTODATA Register(s) (can disable whenexternal access is turned off via

AUTOPTRSETUP)

FAST TRANSFER has PORTC strobe feature for reads andwrites

Suspend Current ~ 275uA ~250uA

FX to FX2Hardware - Slave FIFOs

• Dedicated PKTEND pin

• More flags with more programmable flexibility

• Two address pins to select 1 of 4 FIFOs

• Same flexible programmable polarity for control pins

FX vs. FX2Hardware - Slave FIFOs

Parameter FX FX2Slave FIFO PKTEND Use I/O pin, and 8051 code Ext. PKTEND pin for IN transfers on slave

FIFO interface, saves 8051 intervention

Slave FIFO ProgrammableFlags

Two programmable slave FIFOstatus flags, fixed INFULL and

OUTEMPTY status flags

Four programmable slave FIFO status flags(FLAGA, FLAGB, FLAGC, FLAGD) with

programmable polarity

Slave FIFO Ext. AddressPins

Two FIFO (ASEL, BSEL) externallogic address pins, used to

select any one of two slave FIFOs(A, B)

Two FIFO (FIFOADR[1:0]) external logicaddress pins, used to select any one offour slave FIFOs (2, 4, 6, 8)

Slave FIFO I/F pin(s)programmable polarity

Programmable polarity for AOE,BOE, SLRD, SLWR, ASEL, BSEL

Programmable polarity for SLOE, SLRD, SLWR,PKTEND pins for slave FIFO interface

FX to FX2Hardware - GPIF

• GPIF sampling or sync clock either 30 or 48 MHz

• More address lines (9 vs. 6)

• GPIF signals are not muxed with GPIO signals

FX vs. FX2Hardware - GPIF

Parameter FX FX2GPIF 16-bit mode FIFOTransaction(s) data busorientation

GPIF 16-bit FIFO transactions mustuse slave FIFO double-byte mode inwhich the first byte in the fifogoes out PORTD (when using eitherA or B) and the second byte goes

out PORTB

GPIF 16-bit FIFO transactions first bytegoes out PORTB, second bytes goes out

PORTD, no double-stuff mode

GPIF Async signal(s)sampling rate

GPIF async (SAS) mode (RDY's)sampled at 48MHz

GPIF async (SAS) mode (RDYs) sampled ateither 30MHz or 48MHz (IFCLK setting), set

in IFCONFIG

GPIF Address Assert GPIF address assert/de-assert oncewaveform is launched

GPIF address assert/de-assert whenregisters are written, regardless of

waveform launched

GPIF Available AddressSignals

GPIF has 6 incremental (during atransaction) address lines

GPIF has 9 incremental (during atransaction) address lines

GPIF Signals GPIF pins are muxed w/8051function pins

GPIF CTL/RDY pins are NOT muxed w/8051functions

GPIF Sync Clock GPIF executes either internally(48MHz) or externally fed XCLK (5

- 48MHz) in sync. mode

GPIF executes either internally (30MHz or48MHz) or externally fed IFCLK (5 - 48MHz)

in sync. mode

GPIF / Keil Monitor UsagePins

SIO-1 pins interfere with GPIFoperation (default monitor) on

PORTB

Keil monitor pins are separate from 8051functions

Parameter FX FX2CLKOUT signaling rate CLKOUT either driven at 48MHz or

24MHz (represents CPU clock), andis not in the same clock domain as

XCLK

CLKOUT can be either 48, 24, or 12MHz(represents CPU clock), and is not in the

same clock domain as IFCLK

XCLK / IFCLK SignalingDirection

XCLK is an input only signal (5 –48MHz)

IFCLK can be either an input (5 – 48MHz)or an output (30/48MHz), set via IFCONFIG,

can also be inverted or tri-stated

FX vs. FX2Hardware - I/F Clocking

• CLKOUT either 12, 24, or 48 MHz

• IFCLK can either be an input or an output

Parameter FX FX2DK Glue Logic Industry Standard 22v10 for

flexible memory expansionCypress CY37xxx CPLD for flexible memory

expansion, etc.

DK General Purpose debug LEDs BKPT / monitor LED (Green) BKPT / monitor LED (Green) , and fouradditional debug LEDs (Red) via MOVX reads

(non-destructive) at specific memorylocations

DK Serial EEPROM (SEE) Small or large SEE Small and large switch selectable SEEs

DK voltage regulator Requires smaller capacityvoltage regulator on DK

Requires larger capacity voltage regulatoron DK

FX vs. FX2Hardware - DK

• CPLD instead of 22V10

• Same BRKPT LED plus four additional LED’s

• Switch selectable EEPROM size

FX to FX2Firmware - USB

• Endpoint size and buffering is programmable

• Auto In/Out to take 8051 out of data path

• No separate ISO buffers

• Can turn off SOF generation

• Better setup data pointer

• No more busy bits

• From 16 endpoints to 7

FX vs. FX2Firmware - USB

Parameter FX FX2Autovector Organization INT2 and INT4 vectors are re-defined, no

gaps

USB OUT PKT Commit/Skip can skip or commit OUT packets, stillhave dummy byte count writes, but now

have new bit for skip or commit

USB Endpoint IN/OUT implements separateendpoint/slave FIFO buffers for

in/out direction

Large endpoint buffers have programmablein/out directions

USB Endpoint Size fixed buffer size, endpointparing

programmable buffer size, type, buffers2x 3x 4x

AUTOIN / AUTOOUT does not have AUTOIN / AUTOOUTcapabilities

AUTOIN / AUTOOUT feature for largeendpoints (2,4,6,8), 8051 sets bit and

then not in data path

USB ZERO LENGTH PKT ability to send zero length packets (ornot) for IN's

Autovector(s) Autoclear no longer need to enable autoclear inISRs for INT2 & INT4

ISO Buffers 2kbytes ISO buffer that can bereclaimed as XDATA

does not have separate ISO buffers

ISO High Bandwidth Report ISO, high bandwidth report, ISOINPACKETS

FX vs. FX2Firmware - USB

Parameter FX FX2USB EP0 ACK Status New Endpoint zero ACK ISV/R. status stage

completed

USB Error Count Error count register, can disconnect beforebeing kicked off bus when renumerating

USB SOF Synthesis Can turn off SOF synthesis

USB High Speed MicroframeCount

microframe register, count generatedinternally...

(may not be in other vendors parts)

USB SETUP DATA POINTER endpoint zero has byte count high (forexplicit setup data pointer) and low(number of bytes to send, HID usage

reports)

USB Endpoint BUSY bit no more endpoint busy bits, now have packetstatus bits.

USB PING-NAK PING-NAK interrupts, similar to IBN... butfor OUTs

USB IBN IN-bulk NAK (IBN)

USB HSGRANT high speed grant is automatic

USB Endpoint Architecture 16 endpoints Four big endpoint/slave fifo buffers andthree smaller EPO, EP1in, EP1out (64 bytes

each)

Parameter FX FX2Slave FIFO Data Path separate 8/16 bit individually selectable

slave FIFO's (WORDWIDE)

Slave FIFO IN full minus 1/ OUT empty plus 1

full minus one (IN) and empty plus one(OUT), status flags on pins

AUTOIN PKT Length Limit packet length registers to limit bufferbytes, commit IN pkts

Slave FIFO Flag(s) status can check GPIF/FIFO status from SFR space

FX vs. FX2Firmware - Slave FIFOs

• FIFOs individually selectable 8/16 wide

• FIFO empty + 1 and full -1 flags

• FIFO status registers in SFR space

Parameter FX FX2GPIF Long Transfer Mode GPIF does not have auto-throttle

for long transfers via idlecheck, a.k.a. - variable rate

mode

long transfer mode of up to 2 to the 16thor 64kbytes/words

GPIF Underflow / OverflowAutoThrottle

GPIF now automatically considers underflowand overflow and TC in the idle state,

variable rate mode

GPIF Decision Point FIFOFLAG SELECT

GPIF can only branch/test theprogrammable flag during a DP

interval

GPIF has a mode with the ability to examineeither PF, FF, EF in decision point

GPIF FIFO TransactionTrigger

can trigger GPIF FIFO read/writetransactions from SFR space (GPIFTRIG)

FX vs. FX2Firmware - GPIF

• New GPIF long transfer mode

• Can now check all flags in decision point

• GPIF trigger now in SFR space

FX to FX2Firmware - 8051

• Full 8k of internal memory for code & xdata

• More registers in SFR space

• I/O ports in SFR space only

• 8051 clock rate either 12, 24, or 48 MHz

• No more DMA

• Two autopointers

FX vs. FX2Firmware - 8051

Parameter FX FX28051 Scratch-Pad RAM 512 bytes scratch ram

8051 Write Recovery write recovery issue, registers indifferent clock domain from the 8051

8051 CODE/DATA Space internal code/data limited to0x1B40

does not use any of the internal 8kbytesRAM for EZ-USB Registers, internal

code/data can be up to 8kbytes

SFRs some registers implemented in SFRspace

more registers are implemented in SFRspace

I/O Port Pin Manipulation can access PORTA-E via mov(PORTSETUP=1) or movx

instructions

I/O port pin access is only via SFR,doesn't need to be enabled

8051 Code Execution Rate executes code at either 48MHz or24MHz clock

executes code either at 48MHz, 24MHz, or12MHz clock reference

EZ-USB Register Location(s) EZ-USB Registers uses some ofinternal memory

EZ-USB Registers are not aliased, theydo NOT appear in two places in XDATA

space

FX vs. FX2Firmware - 8051

Parameter FX FX2DK Keil Monitor DownloadLocation

external monitor downloads at0xE000 and above on DK

external monitor downloads at 0x2000 andabove on DK

DMA-like Available DMA-like mechanism does not have or require DMA-like feature(AUTOIN / AUTOOUT and Dual Autopointers)

AUTOPOINTER(s) Available one AUTOPOINTER two AUTOPOINTERs

AUTOPOINTER(s) Freeze Mode AUTOPOINTER freeze mode, which can be used topoint to any EZ-USB Register thus making one

XDATA location at a time SFR accessible

AUTODATA Register LocationProgram Memory Hole

has AUTODATA register locationas program memory hole

selectable AUTOPOINTER to either MOV or MOVXspace (if external is not used then no longer

have program holes in code space)