functional testing

124 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 1, JANUARY 2013

Built-In Generation of Functional Broadside TestsUsing a Fixed Hardware Structure

Irith Pomeranz, Fellow, IEEE

Abstract—Functional broadside tests are two-pattern scan-based tests that avoid overtesting by ensuring that a circuit tra-verses only reachable states during the functional clock cycles of atest. In addition, the power dissipation during the fast functionalclock cycles of functional broadside tests does not exceed thatpossible during functional operation. On-chip test generationhas the added advantage that it reduces test data volume andfacilitates at-speed test application. This paper shows that on-chipgeneration of functional broadside tests can be done using a simpleand fixed hardware structure, with a small number of parametersthat need to be tailored to a given circuit, and can achieve hightransition fault coverage for testable circuits. With the proposedon-chip test generation method, the circuit is used for generatingreachable states during test application. This alleviates the needto compute reachable states offline.

Index Terms—Built-in test generation, functional broadsidetests, reachable states, transition faults.

I. INTRODUCTION

O VERTESTING due to the application of two-patternscan-based tests was described in [1]–[3]. Overtesting

is related to the detection of delay faults under non-functionaloperation conditions. One of the reasons for these non-func-tional operation conditions is the following. When an arbitrarystate is used as a scan-in state, a two-pattern test can takethe circuit through state-transitions that cannot occur duringfunctional operation. As a result, slow paths that cannot besensitized during functional operation may cause the circuitto fail [1]. In addition, current demands that are higher thanthose possible during functional operation may cause voltagedrops that will slow the circuit and cause it to fail [2], [3]. Inboth cases, the circuit will operate correctly during functionaloperation.Functional broadside tests [4] ensure that the scan-in state is

a state that the circuit can enter during functional operation, ora reachable state. As broadside tests [5], they operate the circuitin functional mode for two clock cycles after an initial state isscanned in. This results in the application of a two-pattern test.Since the scan-in state is a reachable state, the two-pattern test

Manuscript received April 11, 2011; revised November 14, 2011; acceptedDecember 07, 2011. Date of publication January 02, 2012; date of current ver-sion December 19, 2012. This work was supported in part by SemiconductorResearch Corporation under Grant 2011-TJ-2135. This paper was presented inpart at the Proceedings of the Design Automation and Test in Europe Confer-ence, Grenoble, France, March 2011.The author is with the School of Electrical and Computer Engineering, Purdue

University, West Lafayette, IN 47907 USA (e-mail: [email protected]).Digital Object Identifier 10.1109/TVLSI.2011.2179682

takes the circuit through state-transitions that are guaranteed tobe possible during functional operation. Delay faults that aredetected by the test can also affect functional operation, and thecurrent demands do not exceed those possible during functionaloperation. This alleviates the type of overtesting described in[1]–[3]. In addition, the power dissipation during fast functionalclock cycles of functional broadside tests does not exceed thatpossible during functional operation.Test generation procedures for functional and pseudo-func-

tional scan-based tests were described in [4] and [6]–[13]. Theprocedures generate test sets offline for application from anexternal tester. Functional scan-based tests use only reachablestates as scan-in states. Pseudo-functional scan-based testsuse functional constraints to avoid unreachable states that arecaptured by the constraints.This work considers the on-chip (or built-in) generation of

functional broadside tests. On-chip test generation reducesthe test data volume and facilitates at-speed test application.On-chip test generation methods for delay faults, such as theones described in [14] and [15], do not impose any constraintson the states used as scan-in states. Experimental results indi-cate that an arbitrary state used as a scan-in state is unlikely tobe a reachable state [4]. The on-chip test generation methodfrom [16] applies pseudo-functional scan-based tests. Suchtests are not sufficient for avoiding unreachable states as scan-instates. The on-chip test generation process described in thiswork guarantees that only reachable states will be used.It should be noted that the delay fault coverage achievable

using functional broadside tests is, in general, lower than thatachievable using arbitrary broadside tests as in [14], [15] orpseudo-functional broadside tests as in [16]. This is due to thefact that functional broadside tests avoid unreachable scan-instates, which are allowed by themethods described in [14]–[16].However, the tests that are needed for achieving this higher faultcoverage are also ones that can cause overtesting. They can alsodissipate more power than possible during functional operation.Only functional broadside tests are considered in this work.Under the proposed on-chip test generation method, the cir-

cuit is used for generating reachable states during test appli-cation. This alleviates the need to compute reachable states orfunctional constraints by an offline process as in [4], [6]–[13]and [16]. The underlying observation is related to one of themethods used in [4] for offline test generation, and is the fol-lowing.If a primary input sequence is applied in functional mode

starting from a reachable state, all the states traversed underare reachable states. Any one of these states can be used as theinitial state for the application of a functional broadside test.

1063-8210/$31.00 © 2012 IEEE

POMERANZ: BUILT-IN GENERATION OF FUNCTIONAL BROADSIDE TESTS 125

By generating on-chip and ensuring that it takes the circuitthrough a varied set of reachable states, the on-chip test gener-ation process is able to achieve high transition fault coverageusing functional broadside tests based on . It should be notedthat, for the detection of a set of faults , at most differentreachable states are required. This number is typically only asmall fraction of the number of all the reachable states of thecircuit. Thus, the primary input sequence does not need totake the circuit through all its reachable states, but only througha sufficiently large number relative to , in order to be effec-tive for the detection of target faults.The hardware used in this paper for generating the primary

input sequence consists of a linear-feedback shift-register(LFSR) as a random source [17], and of a small number of gates(at most six gates are needed for every one of the benchmark cir-cuits considered). The gates are used for modifying the randomsequence in order to avoid cases where the sequence takes thecircuit into the same or similar reachable states repeatedly. Thisis referred to as repeated synchronization [18]. In addition, theon-chip test generation hardware consists of a single gate that isused for determining which tests based on will be applied tothe circuit. The result is a simple and fixed hardware structure,which is tailored to a given circuit only through the followingparameters.1) The number of LFSR bits.2) The length of the primary input sequence .3) The specific gates used for modifying the LFSR sequenceinto the sequence .

4) The specific gate used for selecting the functional broad-side tests that will be applied to the circuit based on .

5) Seeds for the LFSR in order to generate several primaryinput sequences and several subsets of tests.

The on-chip test generation hardware is based on the one de-scribed in [19]. It differs from it in the following ways.1) The logic that produces the primary input sequence isdesigned in this paper to reduce the dependencies betweenthe values assigned to the primary inputs, considering thefollowing sources of dependency. In [19], for a circuitwith primary inputs and a parameter mod, the LFSRused for producing has bits. The left-mostbits are used for driving the primary inputs of the circuit,and the mod right-most bits are used for modifying therandom sequence in order to avoid repeated synchroniza-tion. With this structure, all the primary input values aremodified using the same function of the mod right-mostbits of the LFSR. Thus, they are always modified togetherand to the same values. In addition, some primary inputsreceive shifted values of the primary inputs immediatelypreceding them.The structure used in this paper reduces these dependen-cies between primary input values by using a -bitLFSR for a circuit with primary inputs, where is a pa-rameter such that . Every consecutive bits of theLFSR are used for producing the value of a different pri-mary input. At most mod of the bits dedicated to a primaryinput are actually used for producing values for the input,including the modification of the input values in order toavoid repeated synchronization. Since the modification is

done using different bits for every primary input, the de-pendencies between primary input values are reduced. Inaddition, the unused bits serve to reduce the dependen-cies between the values of different primary inputs furtherby avoiding cases where a primary input receives shiftedvalues of the primary input immediately preceding it. Withreduced dependencies, the primary input sequence ismore likely to take the circuit into a varied set of reach-able states. As a result, a higher fault coverage is achievedfor several of the circuits considered in [19]. In addition,other parts of the test generation hardware can be simpli-fied compared with the design in [19], as discussed next.

2) Both [19] and this paper apply multiple primary input se-quences in order to achieve the highest possible fault cov-erage. To select which tests will be applied to the circuitbased on every sequence, the approach of [19] uses a dif-ferent gate for every sequence. Since the number of se-quences in [19] is significant, a large multiplexer and a sig-nificant number of gates are needed for this purpose. Theapproach in this paper fixes the gate used for test selec-tion in advance, and ensures that all the primary input se-quences used for the circuit fit with the preselected gate. Inthis way, a single gate is needed for test selection regardlessof the number of sequences used, and there is no need fora multiplexer to distinguish between different sequences.

3) The lengths of the primary input sequences is varied in [19]in order to control the number of tests applied to the circuit.In this paper, all the sequences have the same length. Thismakes the test application process uniform across differentsequences.

The result is that the test generation hardware used in thispaper has a simple and fixed structure, and it is independent ofthe number of sequences used. The sequences differ only in theseed used for the LFSR. The seeds can be stored on-chip, or aseed can be scanned in together with the initial state of the circuitbefore the application of every primary input sequence.The paper focuses on the generation of input test data, which

is unique to functional broadside tests. For the output test datathe paper assumes that an output compactor such as a multiple-input shift-register (MISR) [17] will be used.When the circuit-under-test is embedded in a larger design,

its primary inputs may be driven by other logic blocks thatare part of the same design. In addition, the primary inputs ofthe circuit-under-test include any external inputs of the designthat drive the circuit-under-test. The primary outputs of the cir-cuit-under-test may drive other logic blocks, or they may be pri-mary outputs of the complete design. For simplicity this paperassumes that primary inputs can be assigned any combination ofvalues. Functional constraints on primary input sequences canbe accommodated in one of the following ways.1) The logic used for producing the primary input sequencecan be extended to incorporate some functional constraints.

2) A separate logic block can be used for modifying so asto satisfy functional constraints.

3) Placing the on-chip test generation hardware for a logicblock on the inputs of the logic blocks driving it can createsome of the functional constraints for the block withoutrequiring additional logic.


This paper is organized as follows. Section II gives anoverview of the on-chip generation and application of functionalbroadside tests. Section III describes the details. Section IVpresents experimental results demonstrating the achievablefault coverage.

II. OVERVIEW

This section gives an overview of the proposed method foron-chip generation of functional broadside tests.The discussion in this paper assumes that the circuit is ini-

tialized into a known state before functional operation starts.Initialization may be achieved by applying a synchronizing se-quence as in [4], [6]–[8] and [10]–[12], by asserting a reset inputas in [9] and [13], or by a combination of both. The initial stateof the circuit is denoted by . The discussion also assumes thatfunctional operation consists of the application of primary inputsequences starting from state .With as the initial state for functional operation, is a

reachable state. In addition, the set of reachable states consistsof every state such that there exists a primary input sequencethat takes the circuit from to . Since can be entered duringfunctional operation starting from is a reachable state.It is possible to obtain reachable states on-chip by placing

the circuit in state and applying a primary input sequenceof length in functional mode. The

circuit can be brought into state by using a scan-in operation,or by using its initializing sequence. Let be the state thatthe circuit reaches at time unit under , for . Wehave that . In addition, is a reachable state for

. Therefore, every state can be used as the initialstate for a functional broadside test , whereplays the role of a scan-in state. As in a broadside test, andare primary input vectors that are applied in two consecutive

functional clock cycles starting from using a slow and afast clock, respectively.In addition to producing reachable states, the primary input

sequence can also be used as a source for the primary inputvectors of functional broadside tests. In particular, every sub-sequence of length two of defines a functional broadside test

. By using and from, it is possible to avoid the need for a different source for theseprimary input vectors during on-chip test generation.For illustration we consider ISCAS-89 benchmark

with initial state . The circuit is shown in Fig. 1.A primary input sequence for the circuit is shown in Table I.For every time unit , Table I shows the state andthe primary input vector . Table I yields the func-tional broadside tests

.The proposed on-chip generationmethod of functional broad-

side tests is based on placing the circuit in the initial state ,applying a primary input sequence , and using several of thefunctional broadside tests that can be extracted from in orderto detect target faults.Next, we discuss how the application of is affected

by the need to observe fault effects created by a test.

Fig. 1. .

TABLE IPRIMARY INPUT SEQUENCE FOR

At time unit the circuit is in state . Applying andin functional mode will result in the application of .

A fault can be detected in one of the following two ways.1) Based on the primary output vector obtained inresponse to , if this vector is different from theexpected fault free primary output vector.

2) Based on the final state of the test, if this state isdifferent from the expected fault free state.

In the context of built-in self-test, and needto be captured by an output response compactor such as aMISR[17]. In the case of , the state needs to be shifted into theoutput response compactor over a number of clock cycles equalto the length of the longest scan chain. The circuit then needs tobe brought back to state in order to continue the testapplication process under .Bringing the circuit back to state can be done by

using circular shift of [17]. As is scanned out,it can also be scanned in. If is faulty, the output responsecompactor will capture the fault effect, and observation of thefinal signature will indicate that a fault is present. Ifis fault free, the remaining tests based on will be applied asrequired.It should be noted that the tests starting in two consecutive

time units, and , are overlapping in the followingsense. Application of takes the circuit through states

and . Application of takesthe circuit through states , and .The application of both and requires specialhardware to bring the circuit back to state after is


TABLE IIPARAMETERS

applied. To avoid the need for this hardware, the proposed testgeneration hardware applies subsets of non-overlapping testsof the form , wherefor .

III. ON-CHIP GENERATION OF FUNCTIONAL BROADSIDE TESTS

This section describes the on-chip generation method forfunctional broadside tests based on the concepts discussed inSection II. Section III-A describes the generation of the se-quence . Section III-B describes the selection of tests that willbe applied based on . Section III-C describes the selectionof seeds for the generation of several different primary inputsequences and the application of several different subsets oftests. Section III-D describes the selection of parameter valuesin order to match the on-chip test generation hardware to agiven circuit. The parameters of the on-chip test generationhardware are summarized in Table II for ease of reference.

A. Primary Input Sequence

The simplest way to generate a primary input sequenceon-chip is to use a random source such as an LFSR. However, arandom sequence may bring the circuit from the initial stateinto a limited set of reachable states. This can be explained by

the effect observed in [18] and referred to as repeated synchro-nization. According to [18], a primary input cube synchronizesa subset of state variables if the following conditions aresatisfied. Let be applied to the primary inputs when the circuitis in the all-unspecified present-state. Suppose that this resultsin a next-state . The state variables whose values are specifiedin are included in .In the example of shown in Fig. 1, the primary input cube

applied in present-state resultsin the next-state , synchronizing state variable. In addition, the primary input cube ap-

plied in present-state results in the next-state, synchronizing state variable .

A primary input cube with a small number of specifiedvalues is likely to appear repeatedly in a random primary inputsequence . When this happens, the state variables in as-sume the same values repeatedly under . This may preventthe circuit from entering certain reachable states, and limit theability of the functional broadside tests extracted from to de-tect target faults. Repeated synchronization can also be causedby a sequence of primary input cubes. However, the longer thesequence the less likely it is to appear in a random primary inputsequence. Therefore, only single cubes are considered in [18].

Considering single cubes, repeated synchronization wasavoided in [18] by using a software procedure. With a highprobability, the procedure avoids primary input cubes thatwould cause repeated synchronization. It allows them to ap-pear with a small probability in order not to preclude certainvalues from ever appearing on the state variables. Here, weneed a similar process that will be implemented using on-chiphardware. To design such hardware, a software procedure isfirst used for computing primary input cubes that synchronizeone or more state variables. The procedure focuses on primaryinput cubes with single specified values since such cubes arethe most likely to appear repeatedly in a random primary inputsequence. For a circuit with primary inputs, ,the procedure considers every primary input cube whereprimary input assumes the value and the other primary in-puts are unspecified. For , where and ,the procedure computes the set of synchronized state variables

. It then combines all the primary input cubes into asingle cube that is useful for avoidingrepeated synchronization as follows.1) If , setting causes fewer next-state variables to be specified than setting . Theprocedure sets .

2) If , setting causes fewer next-state variables to be specified than setting . Theprocedure sets .

3) If , the procedure sets .In the example of the procedure yields

, and in all the other cases.Therefore, it yields . When this cube is applied tothe circuit in the all-unspecified state it leaves all the next-statevariables unspecified. Thus, it ensures that the circuit cantraverse all its reachable states.It is possible to specify additional bits of in order to avoid

cubes with more than one specified value, or based on sequencesof cubes. A single specified bit of is sufficient in both of thesecases. For example, to avoid the sequence 0xxx x0xx xx0x it issufficient to set or or .The on-chip test generation hardware uses for the gener-

ation of as follows. For a circuitwith primary inputs and for parameters and mod such that

, the hardware includes a -bit LFSR. The LFSRis clocked for cycles to produce a sequence of length .At every time unit of the LFSR sequence, every consec-

utive bits of the LFSR are used for producing the value of oneprimary input. Let the LFSR state at time unit be . Letthe value of bit of the LFSR at time unit be . Thevalue of primary input at time unit is producedbased on . The value

of primary input at time unit is produced basedon . In general,the value of primary input at time unit is producedbased onusing the following rules.1) If . In this case, the valueof is the random value produced by theLFSR. Bits are


Fig. 2. On-chip generation of .

unused, and they serve to reduce the dependencies betweenthe values of and those of .

2) If. By using the AND

function of mod LFSR bits, with probability. Thus, repeated synchronization of state vari-

ables due to is avoided with this probability.Bitsare unused, and they serve to reduce the dependenciesbetween the values of and those of .

3) If. By using the OR function of

mod LFSR bits, with probability .Thus, repeated synchronization of state variables due to

is avoided with this probability. Bitsare unused, and they

serve to reduce the dependencies between the values ofand those of .

With this implementation, the values of each primary inputare modified independently using a different set of mod LFSRbits. This reduces the dependencies between the values of dif-ferent primary inputs further.For illustration, Fig. 2 shows the hardware used for with

parameters and . For this circuit, and. The 12-bit LFSR is shown at the top of Fig. 2. Bits

0, 1 and 2 of the LFSR are used for producing the values of .Since , an OR gate is used for increasing the probabilitythat will be assigned the value 1. The OR gate is driven by bits0 and 1 of the LFSR. Bit 2 of the LFSR reduces the dependenciesbetween the values of and the values of .Bits 3, 4, and 5 of the LFSR are used for producing the values

of . For . Therefore, is driven directly by bit 3of the LFSR. Bits 4 and 5 reduce the dependencies between thevalues of and the values of .Bits 6, 7, and 8 are used for producing the values of . Since

, an AND gate is used for increasing the probability thatwill be assigned the value 0. The AND gate is driven by bits 6

and 7. Bit 8 of the LFSR reduces the dependencies between thevalues of and those of .Finally, bits 9, 10, and 11 are used for producing the values

of . For . Therefore, is driven directly by bit 9of the LFSR.In general, if there are primary inputs with , the

implementation illustrated by Fig. 2 requires a -bit LFSR,and AND or OR gates with mod inputs.

TABLE IIILFSR SEQUENCE FOR

The primary input sequence shown in Table I was producedby the structure shown in Fig. 2 using the 12-bit primitive LFSR

from [20] with seed 101 011 100 100.The states of the LFSR are shown in Table III.

B. Test Selection

This subsection describes the selection of the functionalbroadside tests that will be applied based on a primary inputsequence . Let be the set of target faults. In general, thegoal is to select a subset of time unitsand apply a test set , where

, such that the followingconditions are satisfied.1) To ensure that the tests are non-overlapping,for .

2) It should be possible to produce the subset on-chip effi-ciently.

3) The test set based on should detect as many of thefaults in as possible.

4) should be as small as possible.For simplicity, the proposed on-chip test generation hardware

satisfies the first two conditions as follows. A counter denotedby , where ,counts from 0 to to indicate the current time unit of .For a parameter , a test is applied when the last bitsof CNT are 0, that is, when

. With , the condition impliesthat only tests that start at even time units are applied. Thus,

. With , the conditionimplies that only tests that start at time units

divisible by four are applied. Thus, . In gen-eral, the conditionimplies that only tests that start at time units divisible by areapplied. We denote .For a given value of , a single NOR gate is needed for pro-

ducing the function .An example using and is shown inFig. 3. The counter CNT is shown at the top of the figure. When

is applied as a two-pattern test to the circuit.Application of includes output response compaction of theprimary output vector under the second pattern, and


Fig. 3. On-chip test selection.

output response compaction of the final state of thetest. The counter CNT is stopped during the scan-out operationof the final state until state is restored through circularshift as discussed in Section II.

C. Selecting Seeds

The on-chip test generation hardware described so far hasparameters and sel. These parameters determine theprimary input sequence , and the tests that will be appliedbased on it. Keeping and sel constant in order to keepthe hardware fixed, there is flexibility only in determining theseed of the LFSR. Different seeds yield different primary inputsequences and different tests. Therefore, it is possible to increasethe fault coverage by using several different seeds.To select seeds for a circuit it is possible to use an approach

similar to the one used for test data compression [21]. Usinga symbolic seed, it is possible to compute a primary input se-quence and the subset of tests based on it, and then solve equa-tions based on functional broadside tests that are known to de-tect target faults. The approach used in this paper avoids deter-ministic test generation to identify effective functional broad-side tests by considering random seeds. A set of seeds is selectedusing the following process.Let be the set of target faults. For , the process

selects a random seed denoted by . It computes the pri-mary input sequence obtained with this seed. It also finds thesubset of tests that will be applied based on . Bothand are determined by the parameters and sel.In particular, is fixed by sel for all the values of . The processperforms fault simulation of under and removes the de-tected faults from . If any faults are detected, it stores ina set denoted by SEED. It continues to consider additional seedsuntil the last seeds do not improve the fault coverage, for aconstant .Computation of seeds requires fault simulation with fault

dropping of under tests for every seed. As additionalseeds are selected, the number of faults in is reduced, and thefault simulation effort decreases.Let the set of selected seeds be

, with corresponding se-quences and subsets of applied tests

. It is possible that allthe faults detected by will also be detected by

. In this case, does not need to be

used as part of the on-chip test generation process. The processof seed selection identifies and removes such sequences asfollows.During the selection of the seeds, if a fault is detected

by a test from , the process sets . It also setsfor . After all the seeds are selected, for

, the process checks whether all the faultsdetected by are also detected by subsets such that

and . This requires fault simulation of everyfault such that under subsets such thatand . If all the faults with are detected byother subsets, the process updates the variable for everysuch fault to reflect another subset based on which is detected.It also sets . At the end, the process removes fromSEED every seed for which .

D. Selecting Parameters

The parameters of the on-chip test generation hardware,and sel, are selected as follows.

The value of mod determines the probability of avoiding re-peated synchronization by modifying a primary input vector

of based on the cube . Experimental results for bench-mark circuits indicate that or 4 is suitable for all thecircuits considered, and that decreasing or increasing mod be-yond these values does not produce a higher fault coverage. Weuse when it is sufficient for matching or exceeding thefault coverage reported in [19], and when isnot sufficient for this purpose. It was necessary to useonly for one circuit.Increasing and can potentially increase the fault coverage.

Increasing increases the number of available tests, and in-creasing reduces the dependencies between the values of theprimary inputs. Increasing sel can potentially decrease the faultcoverage since it decreases the number of tests that will be ap-plied to the circuit.Considering the values suitable for different circuits and the

effects of increasing and decreasing these values, the valuesfound to be effective are , or 8192,

or , andor 512. The value of determines the number of LFSR bits tobe . This number is limited to be at most 300. The followingprocess is applied in order to select the values of these parame-ters for a given circuit.Setting and , the process considers

and 16. For every value of such that it selects seedsas described in the previous subsection using . It findsa fault coverage denoted by . Of all the values of, it selects the lowest one that yields the highest fault coverage.This is the value of selected for the circuit.Next, the process considers and 8192.

For every value of it considers . For everyvalue of and sel it selects seeds as described in the previoussubsection using . It finds a fault coverage denotedby . The process continues to increase sel for eachvalue of only as long as the fault coverage does not go down,or until sel reaches its upper bound of 512.Of the solutions obtained with , the following ones

are reported.


TABLE IVON-CHIP TEST GENERATION

1) If the fault coverage does not exceed that of [19] for anysolution, we report on the following solutions.a) The solution with the highest fault coverage and thelowest number of seeds.

b) The solution with the highest fault coverage and thelowest number of applied tests.

2) If the fault coverage of at least one solution exceeds that of[19], we report on the following solutions.a) The solution with the highest fault coverage.b) The solution with a fault coverage higher than that of[19] and the lowest number of seeds.

c) The solution with a fault coverage higher than that of[19] and the lowest number of applied tests.

One of these solutions is expected to be the most appropriatefor the circuit. In addition to these solutions there are others withintermediate numbers of seeds and applied tests, which are notreported.

IV. EXPERIMENTAL RESULTS

The circuits considered for the on-chip generation of func-tional broadside tests are ISCAS-89 and ITC-99 benchmarks

that are testable using functional tests. This excludes fromconsideration circuits such as , and , forwhich the fault coverage achievable by functional tests is verylow. Practical circuits are expected to be testable by functionaltests of the type considered here.The initial state of the circuit is assumed to be the all-0 state.

Transition faults are used as the target fault model. For the LFSRin the implementation of the on-chip test generation hardware,a primitive LFSR from [20] is used.The highest number of specified values in the cube used

for avoiding repeated synchronization in any circuit was six.Thus, at most six mod-input gates are required for modifyingthe primary input sequence as illustrated by Fig. 2.The results are shown in Table IV as follows. The first row

for every circuit provides the results from [19] for comparison.The next rows provide the results of the on-chip test generationprocess described in this paper, corresponding to the solutionswith the highest fault coverage, the lowest number of seeds, andthe lowest number of applied tests, as discussed earlier. Eachrow is organized as follows.Columns and sel show the values of the corre-

sponding parameters.


Column seq shows the number of primary input sequences(and the number of seeds) selected.Column tests subcolumn app shows the number of tests ap-

plied based on the selected sequences, and subcolumn eff showsthe number of tests that improve the fault coverage when theyare applied. Some applied tests do not increase the fault cov-erage since the function apply does not exclude all the tests thatdo not increase the fault coverage.Column f.c. shows the transition fault coverage achieved by

the tests applied on-chip. For all of the circuits considered, theon-chip generation of functional broadside tests achieves a tran-sition fault coverage that is the same as or higher than that re-ported in [13] using an offline test generation procedure.Column gates shows the following numbers of gates.1) For the approach from [19], the modification of the pri-mary input sequence based on requires a two-input gatefor every specified bit of . In addition, each sequence re-quires a gate for selecting the tests that will be applied tothe circuit. The multiplexer required for selecting the ap-propriate gate for each sequence has one AND gate for everysequence, and an OR gate to produce the output of the mul-tiplexer. Overall, the number of gates is estimated as thenumber of specified bits in plus the number of sequences.

2) For the approach described in this paper, the hardwarestructure is illustrated by Figs. 2 and 3. The modification ofthe primary input sequence based on requires a gate forevery specified bit of . In addition, a single gate is usedfor selecting the tests that will be applied to the circuit. Thesame gate is used for implementing the selection for all thesequences, and no multiplexers are needed to select amongthe different sequences. The number of gates is equal to thenumber of specified bits in plus one.

Column LFSR shows the number of LFSR bits. In spite of thelarger size of the LFSR compared with the approach from [19],the approach described in this paper has the advantage that itreduces the need for random logic, and it already accommodatesthe need to reduce dependencies between primary input valuesin order to increase the fault coverage.From Table IV it can be seen that, the simplified hardware and

the reduced dependencies between the values assigned to theprimary inputs, allows the on-chip test generation approach de-scribed in this paper to achieve a higher fault coverage than thatreported in [19] for several circuits. The fault coverage using theproposed hardware structure is never lower than that reported in[19].The proposed hardware also provides the flexibility needed

to produce solutions with low numbers of different seeds or lownumbers of applied tests. The numbers of applied tests are typ-ically higher than in [19] due to the simpler hardware structure.However, even with higher numbers of applied tests, the num-bers remain manageable.It is also interesting to consider the fault coverage of the pri-

mary input sequences that can be applied under the proposed ap-proach when they are used as functional test sequences, withoutusing scan. We used the on-chip test generation hardware forgenerating functional test sequences targeting single stuck-atfaults, using the parameters or 16, and

. The selection between and 16 was made based on

TABLE VFUNCTIONAL TEST SEQUENCES

the number of primary inputs. For a circuit with up to 10 pri-mary inputs, ensures that the LFSR is large enough toproduce effective test sequences. For a circuit with more than10 primary inputs, is sufficient.The on-chip test generation hardware was simulated with sev-

eral different seeds, until the last sequences did notimprove the single stuck-at fault coverage.The results are shown in Table V, as follows. Columns

and show the values of the corresponding parameters.Column seq shows the number of primary input sequences (andthe number of seeds) selected. Column eff shows the maximumlength required for any applied sequence. If a sequence oflength does not detect any additional faults after the firstprimary input vectors are applied, its effective length is .The number under column eff is the maximum value ofconsidering all the selected primary input sequences. Columnf.c. shows the single stuck-at fault coverage. For comparison,column determ shows the single stuck-at fault coverage thatis known to be achievable using offline deterministic test se-quences. This fault coverage is not available for sincethe circuit is highly untestable using functional test sequencesand it is not considered by test generation procedures fornon-scan circuits.From Table V it can be seen that, for several of the circuits

considered, the proposed approach produces functional test se-quences that match the achievable offline single stuck-at faultcoverage. For other circuits, the fault coverage is significantlylower than that achievable offline. It should be noted that theproposed on-chip hardware achieves the highest known transi-tion fault coverage using functional broadside tests, and that itwas not designed to produce functional test sequences. The dif-ference between functional test sequences and functional broad-side tests can be explained as follows.Fault detection by the application of functional test sequences

requires that the circuit be brought into states where faults canbe activated. It also requires the propagation of fault effects tothe primary outputs. The first requirement exists for functionalbroadside tests as well, and the primary input sequences pro-duced by the on-chip test generation hardware are effective forthis purpose. However, the sequences may not include propa-gation sequences since this is not a requirement for functionalbroadside tests. If propagation sequences are not included, thefault coverage of the sequences, when considered as functionaltest sequences, may be lower.


This points to the existence of a substantial difference be-tween generating functional test sequence and generating func-tional broadside tests. Due to this difference, substantially dif-ferent on-chip hardware may be required for the two applica-tions.

V. CONCLUDING REMARKS

This paper described an on-chip test generation method forfunctional broadside tests. The hardware was based on the appli-cation of primary input sequences starting from a known reach-able state, thus using the circuit to produce additional reachablestates. Random primary input sequences were modified to avoidrepeated synchronization and thus yield varied sets of reachablestates. Two-pattern tests were obtained by using pairs of consec-utive time units of the primary input sequences. The hardwarestructure was simple and fixed, and it was tailored to a givencircuit only through the following parameters: 1) the length ofthe LFSR used for producing a random primary input sequence;2) the length of the primary input sequence; 3) the specific gatesused for modifying the random primary input sequence; 4) thespecific gate used for selecting applied tests; and 5) the seeds forthe LFSR. The on-chip generation of functional broadside testsachieved high transition fault coverage for testable circuits.

REFERENCES

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[3] S. Sde-Paz and E. Salomon, “Frequency and power correlation betweenat-speed scan and functional tests,” in Proc. Int. Test Conf., 2008, pp.1–9, Paper 13.3.

[4] I. Pomeranz and S.M. Reddy, “Generation of functional broadside testsfor transition faults,” IEEE Trans. Comput.-Aided Design Integr. Cir-cuits Syst., vol. 25, no. 10, pp. 2207–2218, Oct. 2006.

[5] J. Savir and S. Patil, “Broad-side delay test,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 8, pp. 1057–1064, Aug.1994.

[6] I. Pomeranz, “On the generation of scan-based test sets with reachablestates for testing under functional operation conditions,” in Proc. De-sign Autom. Conf., 2004, pp. 928–933.

[7] Y.-C. Lin, F. Lu, K. Yang, and K.-T. Cheng, “Constraint extractionfor pseudo-functional scan-based delay testing,” in Proc. Asia SouthPacific Design Autom. Conf., 2005, pp. 166–171.

[8] Z. Zhang, S. M. Reddy, and I. Pomeranz, “On generating pseudo-func-tional delay fault tests for scan designs,” in Proc. Int. Symp. DefectFault Toler. VLSI Syst., 2005, pp. 398–405.

[9] I. Polian and F. Fujiwara, “Functional constraints vs. test compressionin scan-based delay testing,” in Proc. Design, Autom. Test Euro. Conf.,2006, pp. 1–6.

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[19] I. Pomeranz, “Built-in generation of functional broadside tests,” pre-sented at the Design Autom. Test Euro. Conf., Grenoble, France, 2011.

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Irith Pomeranz (M’89–SM’96–F’99) received theB.Sc. degree (summa cum laude) in computer engi-neering and the D.Sc degree from the Department ofElectrical Engineering, Technion—Israel Institute ofTechnology, Haifa, Israel, in 1985 and 1989, respec-tively.From 1989 to 1990, she was a Lecturer with the

Department of Computer Science, Technion. From1990 to 2000, she was a faculty member with theDepartment of Electrical and Computer Engineering,University of Iowa. In 2000, she joined the School of

Electrical and Computer Engineering, Purdue University. Her research interestsinclude testing of VLSI circuits, design for testability, synthesis and design ver-ification.Dr. Pomeranz was a recipient of the NSF Young Investigator Award in 1993,

and of the University of Iowa Faculty Scholar Award in 1997. She is a GoldenCore Member of the IEEE Computer Society.

functional testing

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