functional level implementation of evolvable
TRANSCRIPT
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 1/11
FUNCTIONAL LEVEL IMPLEMENTATION OF EVOLVABLE
HARDWARE USING GENETIC ALGORITHM
ABSTRACT
Filtering data in real time requires dedicated Hardware to meet demanding time
requirements. If the statistics of the signal are not known, then Adaptive filtering
algorithms can be implemented to estimate the signals statistics iteratively. One
important feature of signal processing is coping with noise. To be able to achieve the
required output signal for a wide range of input signals and noise, it is desirable to be
able to adjust both the filter characteristics and the type of filter. In this way the
resulting filter is said to be an Adaptive filter. We propose an on-chip solution for
evolving an adaptive Digital filter using an on-chip evolvable hardware method. We
highlight a challenge within Evolvable hardware for Adaptive designs and that is to
find efficient ways in which sufficient genetic material will be available for the
Evolution process.
This Project is about implementing evolvable hardware using Genetic Algorithms. It
gives a formal introduction to evolvable hardware, which is a new hardware paradigm
in which hardware is built on reconfigurable devices such as PLDs and FPGAs whose
architectures can be reconfigured by using evolutionary computation techniques such
as Genetic Algorithms, to adapt to the new environment. Present EHW researches are
all based on gate level evolution but here we go in for functional level implementation
of EHW which aims at more practical applications.
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 2/11
INTRODUCTION TO EHW
Evolvable Hardware (EHW) is based on the idea of combining a
reconfigurable hardware device with genetic algorithms (GA) to execute
reconfiguration autonomously. The structure of reconfigurable hardware devices can
be changed any number of times by downloading in to the device a software bit string
called the configuration bits. Field Programmable Gate Array (FPGA) and
Programmable Logic Devices (PLD) are typical examples of reconfigurable hardware
devices.
A genetic algorithm starts with a set of random candidate solutions
represented as binary bit strings. This set is referred to as a population, and each
solution within the population is known as a ‘chromosome’. These chromosomes are
evaluated and a fitness score is assigned to each of them, the fitness score is some
predefined criterion. New individuals are created using genetic operators such as
crossover and mutation.
Create an initial pool of solutions to a problem
Evaluate the solutions and assign fitness
Values to each of them
Acceptable yes Exit
solutions obtained
no
Select a number of ‘parent’ solutions from
the pool based on their fitness scores
Use genetic operations i.e. recombination,
crossover and mutation to
generate a set of new solutions
Fig. 1: Standard Genetic Algorithm
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 3/11
The basic concept behind the combination of reconfigurable hardware and
genetic algorithm in EHW is to regard the configuration bits for reconfigurable
hardware devices as chromosomes for genetic algorithms (Fig. 2).
Fig. 2: Basic concept of Evolvable Hardware
THE FPGA MODEL FOR FUNCTION LEVEL EHW:
To produce an adaptive filter with functional level EHW, we use the FPGA
model shown in Fig 3. The FPGA model is comprised of 6 columns, each containing
5 Programmable Function Units (PFUs). Each PFU can implement one of the
following functions: an adder, a subtractor, an if-then, a sine generator, a cosine
generator, a multiplier, or a divider. The selection of the function to be implemented
by the PFU is determined by the chromosome genes given to the PFU. Constant
generators are also included in a PFU. Columns in the architecture are interconnected
by crossbar switches. These crossbars determine the inputs to the PFUs.
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 4/11
Fig. 3: FPGA model
ADAPTIVE FILTER OVERVIEW
Adaptive filters learn the statistics of their operating environment and continually
adjust their parameters accordingly.
One of the aims of evolutionary hardware is to be able to offer adaptive
hardware. In this we focus on the design through evolution of an adaptive digital
filter. The adaptive filter provides a good case study for Adaptive design due to its
requirement for real time fitness evaluation. In addition, we consider an on-chip
solution where the genetic algorithm and the evolving filter design itself are
implemented on the same chip.
In practice, signals of interest often become contaminated by noise or other
signals occupying the same band of frequency. If the statistics of the noise are not
known a priori, or change over time, the co-efficients of the filter cannot be specified
in advance. In these situations, adaptive algorithms are needed in order to
continuously update the filter co-efficients.
In the results presented herein we focus on adjusting the filter coefficients
representing the filter characteristics and the filter type to produce the filter response
required for the specification given, in addition, we test out the effect of noise on the
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 5/11
input signal and the filter’s ability to filter out the noise and still retain the required
response.
An adaptive filter consists of a digital filter along with a generator the
generator. The generator is an adaptive algorithm that adjusts filter coefficients to
meet changing conditions in the input signal – in our case a generic algorithm is used.
The generator uses a reference signal which specifies the desired filter output. i.e the
required pass-band and stop band.
IMPLEMENTATIONThe implementation presented herein maybe termed as complete hardware
evolution (CHE) which is illustrated in Fig 4. The main feature of a CHE
implementation is the Genetic Algorithm pipeline (GA-pipeline) which, as the name
suggests is a pipeline of modules representing the various functions or parts of the
evolution process required to process a given generation, together with a feedback to
handle the creating of further generations. In addition, control hardware allows for
communication with the outside world. The third main feature is the evolving design
itself in this case an adaptive FIR filter.
Fig. 4: Data flow in CHE
As shown in Fig. 5, GA-pipeline and the evolving filter are connected together by a
two way communication. Individuals are transferred to the filter and the filter
response (current output signal) for the current individual are fed back to the GA
GA Pipeline
Control Evolving
Design
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 6/11
pipeline for fitness evaluation. A given individual provides a set of coefficients for the
filter. The reference signal within the generator provides the filter specification i.e. the
required pass-band and stop-band to the GA pipeline. Control logic is not shown in
this figure.
Reference
Signal
Individual
Input signal Output signal
Fig. 5: Adaptive FIR filter structure using CHE
The adaptive FIR Filter design is based on the multiply and Accumulate
structure shown in Fig. 6 This may be compared to Fig. 4 where the GA Pipeline is
the generator and the filter of the evolving design represents the delay line and
accumulator shown in the figure, the coefficients for the evolving design are those
coefficients applied to the delay line in Fig. 6.
GA Pipeline
Filter
Coefficients
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 7/11
Reference
Filter coefficient Generator
So
……
TAP 0 TAP 2 TAP n
z
Yo
Fig. 6: Multiply Accumulate FIR filter
FITNESS EVALUATION
In the case of a static design, the evolution process drives the evolving design towards
an optimal or near optimal solution e.g. a tone discriminator or a multiplex or design.
In the case of the adaptive filter there is one single sought solution i.e. the filter most
responds to the input signal in accordance with the reference signal to appear at the
output. The coefficient solution will vary with varying input signals to the filter and,
as such this type of design may be termed a dynamic design i.e. solutions vary over
time.
1001010 ……………………. 101011
Accumulator
D D D× × ×
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 8/11
The fitness functions uses the response from the current filter i.e. the output of the
design represented by the current individual, to calculate a fitness value (Fit value) for
the proposed solution.
This value is calculated by accumulating the difference between the reference signal
itself (refsig) and the response from the filter (response) i.e. the output signal, for each
sample – i to n. The optimal solution sought is a fitness value of 0 i.e. 100% fitness.
n
Fit value = Σ | ref signal – responsei |
i =1
SIMULATION RESULT
Reference signal Input signal
GA output Adaptive filter simulation
CONCLUSION :
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 9/11
In this paper we have discussed in detail the concept of EHW. In particular,
we proposed and demonstrated that EHW employing evolution at the functional level
is powerful enough to produce hardware that can be of practical use.
Since the EHW concept involves the evolution of desired hardware circuits by
genetic learning, it provides a bottom up approach contrast to the conventional top
down hardware design technology. The principle of functional level EHW is that both
the function of each PFU and the interconnections between them are dynamically
changed according to the chromosome.
RESULTS:
This project was first simulated in C, using the same algorithms on the ones
ultimately implemented in the FPGA. Then this project was written in VHDL capable
of being synthesized. The core was simulated and synthesized using Xilinx. Some
experiments were conducted out using the population size of 32 and the genotype
length in 27 bits. These bits are split into 3 eight-bit ratios representing the 8-bit
concept and the remaining 3 bits to select the input signal to the PFUs.
In the selection mechanism is linear rank selection with elitism. Single point
crossover is taken mutation rate is set to 0.27 per bit. These rates are similar to those
used in ETL [11]. The desired response was achieved after 1131 generations. Only
16.27% of the FPGA is used at the operating frequency of 30MHz. This is still in
progress.
REFERENCES
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 10/11
1) A.E.Eiben, J.E.Smith, “Introduction to Evolutionary computing”, Springer
Verlag, 2003.
2) D.Goldberg, “Genetic Algorithms in Search”, Addison Wesley, 1989.
3) Tetsuya Higuchi, Masahiro Murakawa and Mehrdad Salami, “Evolvable
Hardware at functional level”, IEEE, 1997.
4) Gerald.R.Clark, “A Novel Functional level EHW”, IEEE, 1999.
5) Gunnar Tufte and Pauline C.Haddow, “Evolving an Adaptive Digital filter”
Norwegian university of science and Tech.
6) Arslan T and Horrocks D.D, “Genetic evolution of adaptive filter”, IEEE.
7) Miller J.F and Thompson.P, “Aspects of Digital Evolution”, Conference
paper.
8) L.Sekanina and R.Ruzicka, “Design of the special fast reconfigurable chip
using common FPGA”, In Proc. Of Design and Diagnostics of Electronics
Circuits and systems, IEEE DDECS’2000.
9) J.Torresen, “A divide and conquer approach to evolvable hardware”, Second
Int. Conf. ICES, 98.
10)X.Yao and T.Higuchi, “Promises and challenges of Evolvable hardware”,
IEEE Trans. On Systems, Man and Cybernetics, 1998.
11) M. Murakawa, S. Yoshizawa et al, “Analogue EHW chip for intermediate
frequency filters.” 2nd International Conference on Evolvable systems
(ICES98).
8/8/2019 Functional Level Implementation of Evolvable
http://slidepdf.com/reader/full/functional-level-implementation-of-evolvable 11/11