functional capping of mems and cmos - silex · ges related r r l inte dev with an wa bon exp tak...

2
St Sile an for Sile ba its tha of mi de Thr off co an Ins se thr we de 10 A tec tanda ex Microsys nd volume m r solving pa -Yo ex Microsyst ased Throug foundry c at has now MEMS devi rror applic evices bein rough Silico fers sub 50 onnections nd is a fe sulator proc paration b roughout th ell tuned p ensity integ 0,000 individ -Yo common chnology ard Pac stems, a pu manufacturi ckaging an our Silico tems first of gh Silicon Vi ustomers in w made its w ices, from h cations to g manufac on Via proce 0 μm pitc in up to 60 eature of cess (TSI™) y etching he full thick process als gration of dual vias in our Wafer implement is to f ckagi ure play M ing capabil nd interconn n Via Ex ffered its do a process ( n 2003, a way into a w high end op consumer ctured in m ess develop ch for thro 00 μm thick Silex Throu that create and refillin kness of a so enables vias with a 6” wafer. r Bondin ation of th form the Fu of M ing Pro EMS foundr lity, present nect challen pert oped silicon (Sil-Via™) to technology wide range ptical MEMS electronic millions. The ped by Silex ough wafe k substrates ugh Silicon es dielectric ng trenches wafer. This very high well ove g Expert he Sil-Viaelectrica nctio MEMS ocess ry with state ts in this arti nges related n o y e S c e x r s n c s s h r t l inte dev with an wa bon exp tak nov the Wa pro disc cap In o cus spe pas pro req wa onal and C Techn e-of-the-art cle its innov d to comme erconnect vice. In ord h such req unparallele fer bonding nding herit pertise in via ke a leading vel and gr e area of c afer Level – ocess platfo crete de pabilities of -You order to sup stomers wi ecifications st years wo ocess suita quirements fer via resist l Cap CMOS nology t MEMS pro vative stand ercialization into a der to serv quirements, ed expertis g process c tage in co a processing g position in round-brea capping an Micro Scale orm is use vices, go LTCC and H ur Metal pport requi th low re (RF MEMS) orked on de able to m of sub 50 tance in co ppin S y ocessing tec dardized tec n of MEMS d hermetical ve foundry Silex has d se in solvin challenges. ombination g has enab n the devel king techn nd intercon e Packing ( ed for pac oing bey HTCC techn Via Exp rements fro esistivity int ), Silex has eveloping a meet the mOhm tot mbination w ng™ chnologies chnologies devices. ly sealed customers developed ng difficult This wafer with the led Silex to opment of nologies in nnect. Silex (WL-MSP™) ckaging of ond the nologies. ert om foundry terconnect s over the a metal-via stringent al through with tough

Upload: others

Post on 16-Oct-2020

1 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: Functional Capping of MEMS and CMOS - Silex · ges related r r l inte dev with an wa bon exp tak nov the Wa pro disc cap In o cus spe pas pro req wa nal and C Techn ... MEM via wa

St Sileanfor Silebaits thaof mideThroffcoanInssethrwede10 A tec

tandaex Microsys

nd volume mr solving pa

-Yo

ex Microsystased Throug foundry cat has now MEMS devirror applic

evices beinrough Silicofers sub 50

onnections nd is a fesulator procparation broughout thell tuned pensity integ0,000 individ

-Yo

common chnology

ard Pacstems, a pumanufacturickaging an

our Silico

tems first ofgh Silicon Viustomers in

w made its wices, from h

cations to g manufac

on Via proce0 µm pitcin up to 60

eature of cess (TSI™) y etching he full thickprocess alsgration of dual vias in

our Wafer

implementis to f

ckagiure play Ming capabil

nd interconn

n Via Ex

ffered its doa process (n 2003, a way into a whigh end op

consumer ctured in mess develop

ch for thro00 µm thickSilex Throu

that createand refillin

kness of a so enables

vias with a 6” wafer.

r Bondin

ation of thform the

Fu of M

ing ProEMS foundrlity, presentnect challen

pert

oped silicon(Sil-Via™) totechnologywide range

ptical MEMS electronicmillions. Theped by Silexough wafek substratesugh Silicones dielectricng trenches wafer. This very high well ove

g Expert

he Sil-Via™electrica

nctioMEMS

ocess ry with statets in this artinges related

n o y e S c e x r s n c s s h r

t

™ l

intedevwithan wabonexptaknovtheWaprodisccap In ocusspepasproreqwa

onal and C

Techne-of-the-artcle its innovd to comme

erconnect vice. In ordh such req

unparallelefer bondingnding heritpertise in viake a leadingvel and gr

e area of cafer Level – ocess platfocrete depabilities of

-You

order to supstomers wiecifications st years wo

ocess suitaquirements

fer via resist

l CapCMOS

nologyt MEMS provative standercialization

into a der to serv

quirements, ed expertisg process ctage in coa processingg position inround-brea

capping anMicro Scale

orm is usevices, go LTCC and H

ur Metal

pport requith low re(RF MEMS)

orked on deable to mof sub 50 tance in co

ppinS

y ocessing tecdardized tecn of MEMS d

hermeticalve foundry

Silex has dse in solvinchallenges. ombinationg has enabn the develking techn

nd intercone Packing (

ed for pacoing beyHTCC techn

Via Exp

rements froesistivity int), Silex has

eveloping ameet the mOhm totmbination w

ng™

chnologies chnologies

devices.

ly sealed customers

developed ng difficult This wafer with the led Silex to opment of

nologies in nnect. Silex (WL-MSP™) ckaging of ond the nologies.

ert

om foundry terconnect s over the a metal-via stringent al through with tough

Page 2: Functional Capping of MEMS and CMOS - Silex · ges related r r l inte dev with an wa bon exp tak nov the Wa pro disc cap In o cus spe pas pro req wa nal and C Techn ... MEM via wa

deboinsprosoltheto intwamisavoMeco SilenoSOcreanTheprothiTethewilcrepoIn funMEanfunwacroof of theexcome

Top-view

emands onoasting astallation bocessing exlutions avae developm avoid micterface betafer. Silex htigating theme time e

oid free fillinet-Via™ teonducting m

- Yo

ex has exteovel methodOI wafer aseation of and other fue cap waocessing ockness ofmperature ere is no Cll allow a eated via fossibility to

addition nctionalitiesEMS parts, nd also Sinction that afer walls inoss talk and entire regio the cap wae handle of

xposed baompleted wetallization.

w SEM pictu

hermeticit world

base that xpertise offeilable toda

ment of the cro crack tween the has develope risk of micnabling low

ng of the vechnology material.

our SOI C

ended its IPd of using ts a means

a cap with unctions (Fuafer is cre

of an SOI f typically

budget isMOS preseproper builunctions anincorporateto metal

s may incluIntegrated ilex patenintegrates bto the cap

d allows totaons of the cafer to the f the SOI wackside of with meta

ure of a met

y. Silex newleading combined

ers the besy. A key fo metal via p

developmmetal condped severacro cracks ww total resisvia plug. Sil

using Au

Capping

P portfolio the device s to secure integratedunctional Ceated by device lay

100 to fairly unrent in this wld and refind will also e added fu vias, sucde cavities Passive Deted Zero buried vertiwafer to re

al dielectriccap. Followin

MEMS or Cafer is releas

the devical routing

tal via.

w 8” line isequipment

with Silexst metal viaocus duringprocess was

ment in theductor and

al means ofwhile at thestance andex offers itsor Cu as

g Expert

to cover alayer of ane a robust metal vias

Capping™)front side

yer with a200 µm

estricted aswafer, which

lling of theenable the

unctionalitych added for movingevices (IPD)

Crosstalk™cal throughduce signa

c separationng bondingMOS wafersed and thece layer is

and UBM

s t x a g s e d f

e d s s

a n t s .

e a . s h e e .

d g )

™ h l

n g r, e s

M

Silemaanda tcusconfollocomsucprothefoudevproknomaMEMviawasign Thefabstroprofouequprowasystcap

SileBruPhoinfoww

M(c

- Yo

x Microsyanufacturingd state-of-theam of skilstomers toncepts to owing volumpany was

ccessfully coducts with e globe. F

ndries, Silexveloping

ocesses, leveow-how toanufacturingMS expertis and cappifer level panificantly red

- Yo

e recent exb in its faciong financiaoviding a fu

ndry custouipped w

ocessing eqfer bonderstems, particpping techn

Sche Functio

ex Microttovagen 1,one: +46 8 5o@silexmicro

ww.silexmicro

Zero CrosstaWall Separa

Metal Vias coaxial)

our Exper

ystems offg services he-art 6" anled MEMS

o quickly working p

ume manus founded iompleted more thanollowing thx is also costandardize

eraging inteo compleg offer. Ane is this preing technol

ackaging anduced form

our 8” ME

xpansion wlities in Sweal position uture proofomers. Silewith stat

quipment, ss and Semitocularly adapnologies pre

matic crossonal Cappin

osystems, 17526 Jarfa

580 249 00, osystems.coosystems.co

alk™ tion

Capacitor

rt MEMS

fers MEMSin its fully

nd 8” waferexperts, Sile

take theprototypes

ufacturing. n year 2000well over 75 customhe trend ntinuously wed MEMSellectual proement then examplesented throogy that ennd MEMS d

m factor.

EMS Foun

with anotheeden testifiand comm

volume suex 8” MEMte-of-the-arsuch as EVool Paragonpted to proesented in t

s section of ng™ substra

s alla, Swede

om om

In

Cav

Foundry

S foundry equipped

r fabs. With ex helps its eir design

and the Since the

0, Silex has 100 MEMS ers around of the IC working on foundry operty and e foundry e of such ough wafer nables true esigns with

ndry

r 8” wafer ies of Silex mitment to upply to its MS fab is rt MEMS VG Gemini n plating oviding the his article.

a ate.

en

nductor

vities

y