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SigmaDSPTM 28-/56-Bit Audio Processor Evaluation Board

Preliminary Technical Data EVAL-AD1940AZ

Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

EVALUATION BOARD OVERVIEW

This document explains the design and setup of the AD1940 SigmaDSP evaluation board.

The EVAL-AD1940AZ provides a full range of analog and digital inputs and outputs to and from the AD1940. The SigmaDSP can connect to analog I/O signals through the AD1939 codec and AD1974 ADC. Digital I/O connections are available in both S/PDIF and 3-wire serial data formats. The DSP is controlled by Analog Devices’ SigmaStudioTM software, which interfaces to the evaluation boards with a USB cabke via the EVAL-ADUSB2EBZ add-on board, also known as the USBi. Power is distributed by a single DC supply, which is regulated to the necessary voltages on the board. The PCB is an 7” × 5” 4-layer design with split analog and digital power and ground planes on the two inner layers.

The AD1940 evaluation board should be used for AD1941 evaluation. There is no AD1941 evaluation board.

PACKAGE CONTENTS

The EVAL-AD1940AZ package contains these items:

• AD1940 evaluation board

• EVAL-ADUSB2EBZ (USBi) communications adapter

• 6V DC power supply with standard US plug

• USB cable with mini-B plug

• Evaluation board/software quick-start guide

• SigmaStudio software

OTHER SUPPORTING DOCUMENTATION

AD1940/AD1941 datasheet AD1939 datasheet AD1974 datasheet SigmaStudio Help (included in the software installation) AN-1006: Using the EVAL-ADUSB2EBZ

FUNCTIONAL BLOCK DIAGRAM

AD1940

PERFORMANCE AUDIODSP

POWER SUPPLYREGULATION

AD1939CODEC

AD1974ADC

ANALOG OUTPUTSANALOG INPUTS

XX

XX

X-X

XX

INPUTSIGNAL

ROUTINGJUMPERS

USBi INTERFACE(USB TO SPI)

S/PDIF RECEIVER

EXTERNAL DIGITAL(I2S/TDM INPUTS)

S/PDIF TRANSMITTER

EXTERNAL DIGITAL(I2S/TDM OUTPUTS)

Figure 1. Functional Block Diagram

EVAL-AD1940AZ Preliminary Technical Data

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BOARD LAYOUT BLOCK DIAGRAM

ANALOG INPUTSANALOG OUTPUTS

POWERSUPPLY

REGULATION

MASTERCLOCK

ROUTING

USBiCONTROL

INTERFACE

EXTERNAL DIGITAL AUDIO (I2S/TDM) HEADERS

S/PDIF RECEIVER/TRANSMITTER

AD1939CODEC

AD1974ADC

DATA/CLOCK INPUT ROUTING

AD1940DSP

Figure 2. Board Layout Block Diagram


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TABLE OF CONTENTS Evaluation Board Overview.............................................................1

Package Contents ..............................................................................1

Other Supporting Documentation .................................................1

Functional Block Diagram...............................................................1

Board Layout Block Diagram ......................................................2

Table of Contents...............................................................................3

Revision History................................................................................3

Setting Up the Evaluation Board.....................................................4

SigmaStudio Software Installation..............................................4

Powering the board.......................................................................4

Hardware Setup - USBi.................................................................4

Connecting the audio cables........................................................4

Switch and Jumper settings..........................................................4

Your First SigmaStudio Project – EQ and Volume Control ....5

Using the Evaluation Board .............................................................7

AD1940 SigmaDSP .......................................................................7

Power ..............................................................................................7

Clocking the Evaluation Board ...................................................7

Input Routing ................................................................................8

Analog Audio Inputs ....................................................................8

External Digital Audio (I2S/TDM) Inputs .................................9

S/PDIF Receiver ............................................................................9

Output Routing ...........................................................................10

Analog Audio Outputs ...............................................................10

External Digital Audio (I2S/TDM) Outputs............................10

S/PDIF Transmitter.....................................................................10

Example Configurations ................................................................11

Board Schematics ............................................................................15

Board Silkscreen and Parts Placement .........................................25

Bill of Materials ...............................................................................26

Ordering Guide ...............................................................................29

Ordering Guide ...........................................................................29

ESD Caution ................................................................................29


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SETTING UP THE EVALUATION BOARDSIGMASTUDIO SOFTWARE INSTALLATION 1. Open the provided .zip file and extract the files to your PC. Alternately, insert the SigmaStudio CD into the computer’s optical drive and browse the CD to the SigmaStudio folder.

2. Install Microsoft .NET Framework ver2.0, if you do not already have it installed. (Do this by double-clicking dotnetfx.exe)

3. Install SigmaStudio by double-clicking setup.exe, and following the prompts. A computer restart is not required.

POWERING THE BOARD The board is powered by the included 6V DC power supply, which should be connected to power jack J14. The power indicator LEDs D3 and D2 should be lit.

HARDWARE SETUP - USBI 4. Plug the USBi into the PC’s USB port using the included mini USB cable. Plug in the USBi into the control port J2 on the eval board (marked yellow on Figure 1).

5. Connect the USB cable to your computer, and to the USBi.

6. When prompted for drivers:

• Choose “Install from a list or a specific location.”

• Choose “Search for the best driver in these locations.”

• Check the box for “Include this location in the search.”

• The USBi driver is located in C:\Program Files\Analog Devices Inc\Sigma Studio\USB drivers, click Next.

• If prompted to choose driver, select CyUSB.sys

• In XP click Continue Anyway if you are prompted saying the software hasn’t passed Windows Logo testing.

CONNECTING THE AUDIO CABLES For this example, we will set up the board to have stereo analog inputs and stereo analog outputs.

7. Connect the audio source to the ANALOG INPUT CHANNEL 0-1 jack J15 (marked blue in Figure 1) on the top of the board, using a 1/8” cable.

8. Connect the ANALOG OUTPUT CHANNEL 0-1 jack J18 (marked green in Figure 1) to your active speakers or headphones.

SWITCH AND JUMPER SETTINGS In order to configure the board for stereo analog in and out, make sure the switches and jumpers are set as indicated in Figure 3.

A black rectangle indicates a connected jumper or switch position.


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Figure 3. Evaluation Board Default Setup and Configuration

YOUR FIRST SIGMASTUDIO PROJECT – EQ AND VOLUME CONTROL 1. Create a new project. The Hardware Configuration Tab will be open.

2. Drag an AD1940 and a USBi cell into the blank white space.

3. Connect the USBi cell to the AD1940 cell by clicking and dragging from the top blue output pin to the green input pin.

Your screen should now look something like Figure 4.

Figure 4. Hardware Configuration Tab

4. Click on the Schematic tab at the top of the screen.

5. In the cell Toolbox expand the IO → Input. Click&Drag an Input cell to the work area.

6. Similarly, expand Filters → Second Order → Double Precision → 2 Ch and click&drag Medium Size Eq

7. Right click the General (2nd Order) cell labeled Gen Filter1, click Grow Algorithm → 1. 2 Channel – Double


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Precision → 4. This creates a five band EQ. Each band’s general filter settings can be modified by clicking the blue boxes on the cell.

8. Expand Volume Controls → Adjustable Gain → Shared Slider→ Clickless SW Slew and click&drag Single slew

9. Expand the IO → Output. Click&Drag two Output cells

10. Connect all the cells as depicted in Figure 3.

11. Make sure your board is powered and connected to the PC. Click the Link-Compile-Download button in SigmaStudio.

12. If the project compiled without error you will be in Ready-Download mode.

Your screen should now look something like Figure 5.

Figure 5. Schematic Tab Full Design

13. Start your audio source playing, and you should hear audio. You can now move the volume control and filter sliders and hear the effect on the output audio in real time.

The online documentation contains more tutorials and detailed information about every cell available.


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USING THE EVALUATION BOARD AD1940 SIGMADSP The AD1940 is a complete 28-bit, single-chip, multi-channel audio SigmaDSP™ for equalization, multiband dynamic processing, delay compensation, speaker compensation, and image enhancement. These algorithms can be used to compen-sate for the real world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of perceived audio quality.

The signal processing used in the AD1940 is comparable to that found in high end studio equipment. Most of the processing is done in full, 56-bit double-precision mode, resulting in very good, low level signal performance and the absence of limit cycles or idle tones. The dynamics processor uses a sophisticated, multiple-breakpoint algorithm often found in high end broadcast compressors.

The AD1940 is a fully programmable DSP. Easy to use software allows the user to graphically configure a custom signal processing flow using blocks such as biquad filters, dyna-mics processors, and surround sound processors. An extensive control port allows click-free parameter updates, along with readback capability from any point in the algorithm flow.

The AD1940’s digital input and output ports allow a glueless connection to ADCs and DACs by multiple, 2-channel serial data streams or TDM data streams. When in TDM mode, the AD1940/AD1941 can input 8 or 16 channels of serial data, and can output 8 or 16 channels of serial data. The input and output port configurations can be individually set. The AD1940 is controlled by a 4-wire SPI® port.

The EVAL-AD1940AZ should be used to evaluate both the AD1940 and the AD1941, which is equivalent to the AD1940 except for its I2C control interface.

POWER The evaluation board uses two ADP3339 low-dropout voltage reulators to generate the 3.3 V analog and digital supplies. The current consumption of the board is approximately 500 mA at a maximum.

The regulators’ inputs should be supplied with +5 to +6 V DC power on connector J14. The power supply should have a female cord plug with a 2.1 mm inner diameter, 5.5 mm outer diameter, and 9.5 mm length. The polarization should be positive-center.

A lab supply can also be used to power the board, and should be connected across test points TP48 (VIN+) and TP70 (GND).

CLOCKING THE EVALUATION BOARD The EVAL-AD1940AZ requires a master clock (MCLK) to operate. The master clock can be supplied from a variety of

sources, and is used to clock the AD1940 DSP, AD1974 ADCs, AD1939 ADCs/DACs, External Digital Audio Interfaces, and the S/PDIF Transmitter.

In most common board configurations, MCLK will be generated by the on-board AD1939. The AD1939 has an internal oscillator that drives a 12.288 MHz crystal to produce a 12.288 MHz master clock suitable for 48 kHz, 96 kHz, and 192 kHz processing applications.

For configurations utilizing the S/PDIF receiver, MCLK must be supplied to the system by the recovered MCLk of the S/PDIF stream. This recovered MCLK has a frequency 256 times the sample rate of the S/PDIF data.

A master clock can also be supplied from an external (off-board) source on the digital audio interface headers J22, J23, and J24. The corresponding MCLK direction switch should be set to IN or OUT as required.

A description of the jumpers used to route MCLK is given in Table 1. Examples of common MCLK configurations are given in the Example Configurations section of this document and in Figure 6.

Table 1. Master Clock Routing Component Function J1 Select MCLK Source/Destination J3 Enable AD1939 Crystal Oscillator Circuit SW3 Set direction of MCLK on H1 (J22) SW4 Set direction of MCLK on H2 (J23) SW5 Set direction of MCLK on H3 (J24)

J3

J1 J1J1J1

AD1939 CRYSTALOSCILLATOR MCLK

1939

XTAL

1939

RECOVEREDMCLK FROMS/PDIF RX

DIR

EXTERNAL MCLKDIGITAL AUDIOINTERFACE J22

H1

AD1939 CRYSTALOSCILLATOR MCLK,

OUTPUT ONDIGITAL AUDIOINTERFACE J22

H1

J3

EXT

J3

EXT

J3XTAL

SW3OUT

SW3OUT

SW3IN

SW3OUT

Figure 6. Example Master Clock Routing Settings

The AD1940 must be set up to properly receive MCLK as an input to its PLL. The board will most often be used with a 12.288 MHz master clock, which is equivalent to 256×Fs, with


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Fs= 48 kHz. In order to set up the AD1940 PLL in 256×Fs mode, switch SW1 must be set up as shown in .

12

34

AD1940MODE SELECTION

SW1 PLL-CTRL0PLL-CTRL1PLL-CTRL2ADR-SEL

Figure 7. PLL Mode Selection for 12.288 MHz Master Clock

A description of all possible PLL settings is shown in , with 0 corresponding to setting the switch to the right, a 1 corresponding to setting the switch to the left, and “don’t care” represented as an “X.”

Table 2. PLL Settings PLL Mode

PLL-CTRL0 SW1-1

PLL-CTRL1 SW1-2

PLL-CTRL2 SW1-3

64×fs 0 0 0 256×fs 0 1 0 384×fs X X 1 512×fs 1 0 0 Bypass 1 1 0

The ADR-SEL switch (SW1-4) determines the SPI address of the AD1940. The default is 0 (switch to the right).

INPUT ROUTING Audio data is routed to the AD1940 via four jumpers: J4, J5, J6, and J7. A description of these jumpers is in Table 3.

Table 3. SDATA_INx Routing Component Function J4 Select data to input to AD1940 – SDATA_IN0 J5 Select data to input to AD1940 – SDATA_IN1 J6 Select data to input to AD1940 – SDATA_IN2 J7 Select data to input to AD1940 – SDATA_IN3

Input clocks are configured via two jumpers: J8 and J9. A description of these jumpers is in Table 4.

Table 4. LRCLK_IN/BCLK_IN Routing Component Function J8 Select frame clock source for AD1940 serial

input ports J9 Select bit clock source for AD1940 serial input

ports

The AD1940 serial input ports are always configured as slaves, so clocks must always be supplied from another source in order for them to function.

ANALOG AUDIO INPUTS The EVAL-AD1940AZ has three stereo 1/8’ input jacks, allowing for a total of 6 channels of analog audio input. Input channels 0-3 are routed to the AD1939 ADCs and input channels 4-5 are routed to the AD1974 ADCs. In order to input

the converted audio data to the AD1940 DSP, it must be routed appropriately using the audio data routing jumpers.

Proper configuration for inputting all analog audio to the DSP is shown in Figure 8. Note that it is not necessary to use all analog audio inputs simultaneously, and the jumpers can be set in any desired configuration to allow for flexibility in routing a combination of analog, digital, and S/PDIF inputs.

J4 J5 J6 J7SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN31939_DATA1 1939_DATA2 1974_DATA1 DON’T CARE

Figure 8. Input Routing Jumpers - Analog Configuration

In an analog input configuration the AD1939 will most commonly be used as the source for LRCLK and BCLK signals. To route this signals to the AD1940’s LRCLK_IN and BCLK_IN pins, configure the jumpers J8 and J9 as shown in Figure 9.

J9J8BCLK_INLRCLK_IN1939_BCLK1939_LRCLK

Figure 9. LRCLK_IN/BCLK_IN Routing Jumpers - Analog Configuration

With the jumpers configured as shown in Figure 8 and Figure 9, the analog input signals will appear in SigmaStudio as input channels 0-5, as shown in Figure 10.

ANALOG INPUT 0ANALOG INPUT 1ANALOG INPUT 2ANALOG INPUT 3ANALOG INPUT 4ANALOG INPUT 5

Figure 10. Analog Inputs in SigmaStudio


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EXTERNAL DIGITAL AUDIO (I2S/TDM) INPUTS The EVAL-AD1940AZ has a digital interface input header (J22) with connections for MCLK, LRCLK, BCLK, and four serial data lines, allowing for a total of 8 channels of serial audio input (I2S, right-justified, or left-justified) or up to 16 channels when TDM modes are used. In order to input the audio data to the AD1940 DSP, it must be routed appropriately using the audio data routing jumpers.

Proper configuration for inputting all I2S/TDM audio to the DSP is shown in Figure 11.

J4 J5 J6 J7SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3INTF_IN0 INTF_IN1 INTF_IN2 INTF_IN3

Figure 11. Input Routing Jumpers - I2S/TDM Configuration

When data is supplied on the digital interface input header, there are two options for LRCLK and BCLK routing. First, the AD1939 can be the clock master. This configuration is shown in Figure 12.

J9J8BCLK_INLRCLK_IN1939_BCLK1939_LRCLK

Figure 12. LRCLK_IN/BCLK_IN Routing Jumpers - I2S/TDM Configuration -

AD1939 Master

Alternatively, the LRCLK and BCLK signals can be taken from an external source over the LRCLK_IN and BCLK_IN pins of the digital interface input header J22. This configuration is shown in Figure 13.

J9J8BCLK_INLRCLK_IN

BCLK_INTF_INLRCLK_INTF_IN

Figure 13. LRCLK_IN/BCLK_IN Routing Jumpers - I2S/TDM Configuration -

External Master

With the jumpers configured as shown in Figure 12 and Figure 13, the external I2S input signals will appear in SigmaStudio as input channels 0-7, as shown in Figure 14.

EXTERNAL I2S INPUT 0EXTERNAL I2S INPUT 1EXTERNAL I2S INPUT 2EXTERNAL I2S INPUT 3EXTERNAL I2S INPUT 4EXTERNAL I2S INPUT 5EXTERNAL I2S INPUT 6EXTERNAL I2S INPUT 7

Figure 14. I2S Inputs in SigmaStudio

If the input serial ports are configured in TDM modes (allowing for up to 16 channels), the input channels will appear in SigmaStudio as input channels 0-15, as shown in Figure 15.

EXTERNAL TDM INPUT 0EXTERNAL TDM INPUT 1EXTERNAL TDM INPUT 2EXTERNAL TDM INPUT 3EXTERNAL TDM INPUT 4EXTERNAL TDM INPUT 5EXTERNAL TDM INPUT 6EXTERNAL TDM INPUT 7EXTERNAL TDM INPUT 8EXTERNAL TDM INPUT 9EXTERNAL TDM INPUT 10EXTERNAL TDM INPUT 11EXTERNAL TDM INPUT 12EXTERNAL TDM INPUT 13EXTERNAL TDM INPUT 14EXTERNAL TDM INPUT 15

Figure 15. TDM Inputs in SigmaStudio

S/PDIF RECEIVER The EVAL-AD1940AZ has an S/PDIF receiver with both optical and coaxial connections, allowing for a total of 2 channels of S/PDIF audio to be input to the AD1940. In order to input the audio data to the AD1940 DSP, it must be routed appropriately using the audio data routing jumpers.

Proper configuration for inputting all S/PDIF audio to the DSP is shown in Figure 16.


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J4 J5 J6 J7SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3DON’T CARE DON’T CARE DON’T CARE SPDIF_RX_DATA

Figure 16. Input Routing Jumpers -S/PDIF Configuration

Because the S/PDIF receiver is always a clock master to the AD1940, the LRCLK_IN and BCLK_IN lines must be connected to the S/PDIF receiver as shown in Figure 17.

J9J8BCLK_INLRCLK_INSPDIF_BCLKSPDIF_LRCLK

Figure 17. LRCLK_IN/BCLK_IN Routing Jumpers - S/PDIF Configuration

The master clock must also be provided from the S/PDIF receiver. For proper operation, J1 should have a jumper on “DIR” and J3 should be set to “EXT.”

The S/PDIF receiver can only input data from one connector at a time. To select the optical connector, set switch SW6 in the up position. To select the coaxial electrical connector, set switch SW6 in the down position.

With the jumpers configured as shown in Figure 16 and Figure 17, the S/PDIF inputs will appear in SigmaStudio as shown in Figure 18.

S/PDIF INPUT 0S/PDIF INPUT 1

Figure 18. S/PDIF Inputs in SigmaStudio

OUTPUT ROUTING The AD1940 serial output ports are always connected to the DACs, digital audio output headers, and S/PDIF transmitter. These data signals do not require any jumpers or switches to be output properly. The AD1940 serial output ports can be configured as either masters or slaves. If the AD1940’s serial output ports are configured as masters, then jumpers J10, J11, J12 and J13 can be left disconnected. If the AD1940’s serial output ports are configured as slaves, then jumpers J10, J11, J12 and J13 must be connected in order to output data. The functionality of these jumpers is described in Table 5.

Table 5. Output Clock Routing Component Function J10 Connect LRCLK_OUT0 to LRCLK_IN. Must be

connected if serial output channels 0-7 are configured as slaves and not externally clocked.

J11 Connect BCLK_OUT0 to BCLK_IN. Must be connected if serial output channels 0-7 are configured as slaves and not externally clocked.

J12 Connect LRCLK_OUT1 to LRCLK_IN. Must be connected if serial output channels 8-15 are configured as slaves and not externally clocked.

J13 Connect BCLK_OUT1 to LRCLK_IN. Must be connected if serial output channels 8-15 are configured as slaves and not externally clocked.

ANALOG AUDIO OUTPUTS The EVAL-AD1940AZ has four stereo 1/8’ input jacks, allowing for a total of 8 channels of analog audio output. Output channels 0-7 are routed to the AD1939 DACs. The analog outputs are hardwired to the AD1940’s serial output ports and are always active.

The analog outputs 0-7 correspond to outputs 0-7 in SigmaStudio.

EXTERNAL DIGITAL AUDIO (I2S/TDM) OUTPUTS The EVAL-AD1940AZ has two external digital interface output headers, J23 and J24, with connections to all eight SDATA_OUT data lines, and two pairs of output LRCLK/BCLK lines. These output headers are hardwired to the AD1940’s serial output ports and are always active.

The I2S/TDM outputs 0-15 correspond to outputs 0-15 in SigmaStudio.

S/PDIF TRANSMITTER The EVAL-AD1940AZ has an S/PDIF transmitter with both optical and coaxial electrical outputs. These outputs are hardwired to the AD1940 and are always active.

The S/PDIF outputs 0-1 correspond to outputs 8-9 in SigmaStudio.


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EXAMPLE CONFIGURATIONS ANALOG IN/OUT MODE

ANALOG INANALOG OUTI2S/TDM INI2S/TDM OUTS/PDIF INS/PDIF OUT

ACTIVE CHANNELS:

= NOT ACTIVE

= ACTIVE INPUT

01

= ACTIVE OUTPUT

23

45

67

89

1011

1213

1415

J1 J9 J4 J5 J6 J7 J10/12 J11/13 J3J8MCLK BCLK_IN SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 LR/BCLK0 LR/BCLK1 MCLKLRCLK_IN1939 1939_BCLK 1939_DATA1 1939_DATA2 1974_DATA1 INTF_IN3 XTAL

SW3H1=MCLK

OUT 1939_LRCLK

AD1940 SERIAL OUT MA STER:CONNECT ALL JUMPE RS J10‐J13

AD1940 SERIAL OUT SL AVEDISCONNECT ALL JUMPE RS J10‐J13


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S/PDIF IN/OUT MODE

ACTIVE CHANNELS:

= NOT ACTIVE

= ACTIVE INPUT

= ACTIVE OUTPUT

ANALOG INANALOG OUTDIGITAL INDIGITAL OUTS/PDIF INS/PDIF OUT

01

23

45

67

89

1011

1213

1415

SW3H1=MCLK

OUT

J1 J9 J4 J5 J6 J7 J10/12 J11/13 J3J8MCLK BCLK_IN SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 LR/BCLK0 LR/BCLK1 MCLKLRCLK_INDIR SPDIF_BCLK 1939_DATA1 1939_DATA2 1974_DATA1 SPDIF_RX_DATA EXTSPDIF_LRCLK




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I2S/TDM IN/OUT MODE(AD1939 XTAL GENERATES MCLK)

ACTIVE CHANNELS:

= NOT ACTIVE

= ACTIVE INPUT

= ACTIVE OUTPUT


01

23

45

67

89

1011

1213

1415

SW3H1=MCLK

IN

J1 J9 J4 J5 J6 J7 J10/12 J11/13 J3J8MCLK BCLK_IN SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 LR/BCLK0 LR/BCLK1 MCLKLRCLK_INH1 BCLK_INTF_IN INTF_IN0 INTF_IN1 INTF_IN2 INTF_IN3



EXTLRCLK_INTF_IN


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I2S/TDM IN/OUT MODE(EXTERNAL MCLK INPUT ON H1)

ACTIVE CHANNELS:

= NOT ACTIVE

= ACTIVE INPUT

= ACTIVE OUTPUT


01

23

45

67

89

1011

1213

1415

SW3H1=MCLK

OUT

J1 J9 J4 J5 J6 J7 J10/12 J11/13 J3J8MCLK BCLK_IN SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 LR/BCLK0 LR/BCLK1 MCLKLRCLK_IN

1939, H1 (OUT) 1939_BCLK INTF_IN0 INTF_IN1 INTF_IN2 INTF_IN3



XTAL1939_LRCLK


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+

C17

10uF

TP6

R4 0R00

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

TP20

TP21

TP22

TP23

TP24

TP25

1 2 3 45678

SW

1

SPS

T_4SEC_SM

D

1 2 3 4 5 6 7 8 9 10

R5

NET_

BU

S_8RES_SM

D_10K0

1 3 5 7 9

2 4 6 8 10

J2H

EAD

ER_10W

AY_

POL

D1 YE

LLO

W

R6

604r

TP26

TP27

TP28

TP29

1940_SD

ATA

_IN

01940_SD

ATA

_IN

11940_SD

ATA

_IN

21940_SD

ATA

_IN

3

1940_BCLK

_IN

1940_LR

CLK

_IN

RESET

SPI

_CO

UT

SPI

_CLA

TCH

SPI

_CD

ATA

1940_PL

L_CTR

L11940_PL

L_CTR

L2

1939_M

CLK

OSPD

IF_RX_M

CLK

MCLK

EXT_

MCLK

_H

2EXT_

MCLK

_H

3

SPI

_CCLK

1940_PL

L_CTR

L0

1940_AD

R_SEL

EXT_

MCLK

_H

1

D3V3

D3V3

1940_M

CLK

1940_SD

ATA

_IN

0

1940_SD

ATA

_IN

1

1940_SD

ATA

_IN

2

1940_SD

ATA

_IN

3

1940_LR

CLK

_IN

1940_BCLK

_IN

1940_SD

ATA

_O

UT0

1940_SD

ATA

_O

UT1

1940_SD

ATA

_O

UT2

1940_SD

ATA

_O

UT3

1940_SD

ATA

_O

UT4

1940_SD

ATA

_O

UT5

1940_SD

ATA

_O

UT6

1940_SD

ATA

_O

UT7

1940_LR

CLK

_O

UT0

1940_BCLK

_O

UT0

1940_LR

CLK

_O

UT1

1940_BCLK

_O

UT1

1940_PL

L_CTR

L01940_PL

L_CTR

L11940_PL

L_CTR

L21940_AD

R_SEL

D3V3

SPI

_CO

UT

SPI

_CCLK

SPI

_CLA

TCH

SPI

_CD

ATA

SPI

_CCLK

SPI

_CD

ATA

SPI

_CO

UT

SPI

_CLA

TCH

VDD2P5V

INVDD3V3

1940_SD

ATA

_O

UT0

1940_SD

ATA

_O

UT1

1940_SD

ATA

_O

UT2

1940_SD

ATA

_O

UT3

1940_SD

ATA

_O

UT4

1940_SD

ATA

_O

UT7

1940_SD

ATA

_O

UT5

1940_SD

ATA

_O

UT6

1940_LR

CLK

_O

UT0

1940_BCLK

_O

UT0

1940_LR

CLK

_O

UT1

1940_BCLK

_O

UT1

Figure 19. AD1940 SigmaDSP and Communications Interface Schematics


Rev. PrA | of 30

PO

WER S

UPPLI

ES A

ND

RESET

5 t

o 6

Volts,

>700m

A

3.3

V D

igital

Supp

lyLi

nea

r Reg

ula

tors

3.3

V A

nal

og S

upp

ly

Res

et G

ener

ator

Mas

ter

Res

et S

witch

Rese

t Thre

shold

= 3

.08V

R13

604r

R14

604r

1A

2K

D2

RED

1 2

D3 GREEN

KA

D4

TP48 V

IN+

L52 13

J14

Coa

x Po

wer

Jac

k

3IN

2O

UT

1GND

4O

UT

U5

AD

P3339-3

.3V

C47

1.0

uF

C48

1.0

uF

TP49

TP50

3IN

2O

UT

1GND

4O

UT

U6

AD

P3339-3

.3V

C49

1.0

uF

C50

1.0

uF

TP51

TP52

C61

SW

2

R15

4VCC

3M

R

1G

ND

2RESET

U17

AD

M811TA

RTZ

+C179

100uF

16V

A3V3

D3V3

RESET

D3V3

D3V3

REG

VIN

DC-I

N

Figure 20. Power Supplies and Reset Schematics


Rev. PrA | of 30

AD

1939 C

OD

EC

AD

1939 D

AC S

erial Port

:AD

1939 D

ACs

are

alw

ays

Sla

ves

Set

AD

1940 S

eria

l Outp

ut

0 t

o M

aste

rAD

1940 O

utp

ut

Chan

nel

s 0-7

in I

2S M

ode

AD

1939 A

DC S

erial Port

:AD

1939 A

DCs

are

alw

ays

Mas

ter

AD

1940 I

npu

t is

alw

ays

Sla

veAD

1940 I

npu

t Chan

nel

s 0-3

in I

2S M

ode

To u

se D

ACs

and

Dig

ital

outp

ut

hea

der

2 s

imultan

eousl

y,se

t AD

1940 o

utp

uts

to

slav

e an

d ex

tern

al d

evic

e as

LRCLK

/BCLK

mas

ter

53

AD

C1LP

54

AD

C1LN

55

AD

C1RP

56

AD

C1RN

57

AD

C2LP

58

AD

C2LN

59

AD

C2RP

60

AD

C2RN

22

DLR

CLK

21

DBCLK

20

DSD

ATA

119

DSD

ATA

218

DSD

ATA

315

DSD

ATA

4

30

CIN

31

CO

UT

34

CCLK

35

CLA

TCH

2M

CLK

I/M

CLK

XI

3M

CLK

O/M

CLK

XO

61

LF

47

FILT

R

52

CM

14

PD/R

ST

36

DAC1LP

37

DAC1LN

38

DAC1RP

39

DAC1RN

40

DAC2LP

41

DAC2LN

42

DAC2RP

43

DAC2RN

6D

AC3LP

7D

AC3LN

8D

AC3RP

9D

AC3RN

29

ALR

CLK

28

ABCLK

27

ASD

ATA

126

ASD

ATA

2

10

DAC4LP

11

DAC4LN

12

DAC4RP

13

DAC4RN

32DVDD

17DVDD

62AVDD

51AVDD

45AVDD

5AVDD

25VDRIVE

24VSENSE

23VSUPPLY

33DGND

16DGND

46AGND

48AGND

44AGND

4AGND

1AGND

U3

AD

1939

C18

22pF

C19

27pFY1

12.2

88 M

Hz

R7

100R

C20

C21

C22

C23

C24

C25

AB

12

3

J3

C26

5.6

nF

C27

390pF

R8

562R

+C28

10uF

C29

0.1

0uF

+C30

100uF

C31

0.1

0uF

L3 600Z

R9

49R9

+

C32

10uF

+

C33

10uF

1 2 3 4 5 6 7 8910

11

12

13

14

15

16

R10

56R0

TP30

TP31

TP32

1939_IN

1L+

1939_IN

1L-

1939_IN

1R+

1939_IN

1R-

1939_IN

2L+

1939_IN

2L-

1939_IN

2R+

1939_IN

2R-

1940_LR

CLK

_O

UT0

1940_BCLK

_O

UT0

1940_SD

ATA

_O

UT0

1940_SD

ATA

_O

UT1

1940_SD

ATA

_O

UT2

1940_SD

ATA

_O

UT3

1939_ASD

ATA

21939_ASD

ATA

11939_AD

C_BCLK

1939_AD

C_LR

CLK

1939_O

UT0

+1939_O

UT0

-1939_O

UT1

+1939_O

UT1

-

1939_O

UT2

+1939_O

UT2

-1939_O

UT3

+1939_O

UT3

-

1939_O

UT4

+1939_O

UT4

-1939_O

UT5

+1939_O

UT5

-

1939_O

UT6

+1939_O

UT6

-1939_O

UT7

+1939_O

UT7

-

RESET

A3V3

MCLK

1939_M

CLK

O

A3V3

FILT

RCM

D3V3

D3V3

Figure 21. AD1939 Codec Schematics


Rev. PrA | of 30

AD

1974 A

DC

AD

1974

AD

1974 A

DC S

erial Port

:AD

1939 A

DCs

are

alw

ays

Mas

ter

AD

1974 a

nd

AD

1940 I

npu

t ar

e al

way

s Sla

ves

AD

1940 I

npu

t Chan

nel

s 4-5

in I

2S M

ode

1AGND2

2M

CLK

I/XI

3M

CLK

O/X

O

4AGND1

5AVDD1

6D

AC3L

7D

AC3R

8D

AC4L

9D

AC4R

10

PD/R

ST

11

DSD

ATA

4

12DGND

13DVDD

14

DSD

ATA

3

15

DSD

ATA

2

16

DSD

ATA

1

17

DBCLK

18

DLR

CLK

19

ASD

ATA

220

ASD

ATA

1

21

ABCLK

22

ALR

CLK

23

CD

ATA

24

CO

UT

25DGND

26

CCLK

27

CLA

TCH

28

DAC1L

29

DAC1R

30

DAC2L

31

DAC2R

32AGND2

33AVDD1

34AGND1

35

FILT

R

36AGND2

37AVDD2

38

CM

39

AD

C1LP

40

AD

C1LN

41

AD

C1RP

42

AD

C1RN

43

AD

C2LP

44

AD

C2LN

45

AD

C2RP

46

AD

C2RN

47

LF

48AVDD2

U4

C34

C35

C36

C37

C38

L4

600Z

+12

C39

10uF

+12

C40

10uF

R11

49R9

C41

5.6

nF

C42

390pF

R12

562R

+C43

10uF

C44

0.1

0uF

+C45

100uF

C46

0.1

0uF

TP33

A3V3

1974_IN

3L+

1974_IN

3L-

1974_IN

3R+

1974_IN

3R-

RESET

A3V3

D3V3

1939_AD

C_LR

CLK

1939_AD

C_BCLK

1974_ASD

ATA

1

MCLK

A3V3

Figure 22. AD1974 ADC Schematics


Rev. PrA | of 30

AN

ALO

G A

UD

IO I

NPU

T F

ILTERS

Anal

og I

npu

ts 0

-1

Anal

og I

npu

ts 2

-3Anal

og I

npu

ts 4

-5

Op-A

mp S

upplie

s

2-

3+

1

U18-A AD

8606AR

6-

5+

7

U18-B AD

8606AR

C62

C63

C64

120pF

R16

237r

R17

5k7

6

R18

5k7

6

R19

OPE

N

R20

5k7

6

R21

5k7

6

R22

237r

+

C65

10uF

+

C66

10uF

R23

237r

R24

5k7

6

R25

5k7

6

R26

OPE

N

R27

5k7

6

R28

5k7

6

R29

237r

C67

120pF

C68

C69

2-

3+

1

U19-A AD

8606AR

6-

5+

7

U19-B AD

8606AR

6-

5+

7

U21-B AD

8606AR

2-

3+

1

U21-A AD

8606AR

C70

C71

C72

120pF

R30

237r

R31

5k7

6

R32

5k7

6

R33

OPE

N

R34

5k7

6

R35

5k7

6

R36

237r

+

C73

10uF

+

C74

10uF

R37

237r

R38

5k7

6

R39

5k7

6

R40

OPE

N

R41

5k7

6

R42

5k7

6

R43

237r

C75

120pF

C76

C77

6-

5+

7

U20-B AD

8606AR

2-

3+

1

U20-A AD

8606AR

C78 C

79

C80

C81

C82

100pF

R44

49k9

TP53

C83

100pF

R45

49k9

TP54

C84

100pF

R46

49k9

TP55

C85

100pF

R47

49k9

TP56

RIN

G

SLE

EVE

TIP

J15

RIN

G

SLE

EVE

TIP

J16

R48

100R

C86

0.1

0uF

2-

3+

1

U22-A AD

8606AR

6-

5+

7

U22-B AD

8606AR

C87

C88

C89

120pF

R49

237r

R50

5k7

6

R51

5k7

6

R52

OPE

N

R53

5k7

6

R54

5k7

6

R55

237r

+

C90

10uF

+

C91

10uF

R56

237r

R57

5k7

6

R58

5k7

6

R59

OPE

N

R60

5k7

6

R61

5k7

6

R62

237r

C92

120pF

C93

C94

2-

3+

1

U23-A AD

8606AR

6-

5+

7

U23-B AD

8606AR

C95 C

96

C97

100pF

R63

49k9

TP57

C98

100pF

R64

49k9

TP58

RIN

G

SLE

EVE

TIP

J17

R65

100R

C99

0.1

0uF

R66

100R

C100

0.1

0uF

R67

100R

C101

0.1

0uF

R68

100R

C102

0.1

0uF

R69

100R

C103

0.1

0uF

4V-

8V+

U20-C

AD

8606AR

C51

4V-

8V+

U22-C

AD

8606AR

C52

4V-

8V+U

21-C

AD

8606AR

C53

4V-

8V+

U18-C

AD

8606AR

4V-

8V+

U19-C

AD

8606AR

C58

4V-

8V+

U23-C

AD

8606AR

C59

C60

1939_IN

1L-

1939_IN

1L+

1939_IN

1R+

1939_IN

1R-

1939_IN

2R-

1939_IN

2R+

1939_IN

2L+

1939_IN

2L-

1974_IN

3L-

1974_IN

3L+

1974_IN

3R+

1974_IN

3R-

FILT

R

FILT

R

FILT

R

FILT

R

FILT

R

FILT

R

A3V3

Figure 23. Analog Audio Input Filters Schematics


Rev. PrA | of 30

AN

ALO

G A

UD

IO O

UTPU

T F

ILTERS (

1)

Anal

og O

utp

uts

0-1

1V R

MS

Anal

og O

utp

uts

2-3

1V R

MS

+

C104

2-

3+

1

U24-A AD

8606AR

R70

1k6

51%

R71

5k4

91%

R72

3k3

21%

R73

11k0

1%

R74

5k4

9

1%

R75

2k7

4

1%

R76

49k9

1%

C105

220pF

C106

100pF

C107

2.2

nF

C108

330pF

C109

680pF

R77

604r

1%

TP59

C110

OPE

NRIN

G

SLE

EVE

TIP

J18

R78

0R00

+

C111

6-

5+

7

U24-B AD

8606AR

R79

1k6

51%

R80

5k4

91%

R81

3k3

21%

R82

11k0

1%

R83

5k4

9

1%

R84

2k7

41%

R85

49k9

1%

C112

220pF

C113

100pF

C114

2.2

nF

C115

330pF

C116

680pF

R86

604r

1%

TP60

C117

OPE

N

R87

0R00

+

C118

2-

3+

1

U25-A AD

8606AR

R88

1k6

51%

R89

5k4

91%

R90

3k3

21%

R91

11k0

1%

R92

5k4

9

1%

R93

2k7

4

1%

R94

49k9

1%

C119

220pF

C120

100pF

C121

2.2

nF

C122

330pF

C123

680pF

R95

604r

1%

TP61

C124

OPE

NRIN

G

SLE

EVE

TIP

J19

R96

0R00

+

C125

6-

5+

7

U25-B AD

8606AR

R97

1k6

51%

R98

5k4

91%

R99

3k3

21%

R100

11k0

1%

R101

5k4

9

1%

R102

2k7

41%

R103

49k9

1%

C126

220pF

C127

100pF

C128

2.2

nF

C129

330pF

C130

680pF

R104

604r

1%

TP62

C131

OPE

N

R105

0R00

C56

4V-

8V+

U24-C

AD

8606AR C57

4V-

8V+

U25-C

AD

8606AR

1939_O

UT0

-

1939_O

UT0

+

CM

1939_O

UT1

-

1939_O

UT1

+

CM

1939_O

UT2

-

1939_O

UT2

+

CM

1939_O

UT3

-

1939_O

UT3

+

CM

A3V3

Figure 24. Analog Audio Output Filters (1) Schematics


Rev. PrA | of 30

AN

ALO

G A

UD

IO O

UTPU

T F

ILTERS (

2)

Anal

og O

utp

uts

4-5

1V R

MS

Anal

og O

utp

uts

6-7

1V R

MS

+

C132

2-

3+

1

U26-A AD

8606AR

R106

1k6

51%

R107

5k4

91%

R108

3k3

21%

R109

11k0

1%

R110

5k4

9

1%

R111

2k7

41%

R112

49k9

1%

C133

220pF

C134

100pF

C135

2.2

nF

C136

330pF

C137

680pF

R113

604r

1%

TP63

C138

OPE

NRIN

G

SLE

EVE

TIP

J20

R114

0R00

+

C139

6-

5+

7

U26-B AD

8606AR

R115

1k6

51%

R116

5k4

91%

R117

3k3

21%

R118

11k0

1%

R119

5k4

9

1%

R120

2k7

41%

R121

49k9

1%

C140

220pF

C141

100pF

C142

2.2

nF

C143

330pF

C144

680pF

R122

604r

1%

TP64

C145

OPE

N

R123

0R00

+

C146

2-

3+

1

U27-A AD

8606AR

R124

1k6

51%

R125

5k4

91%

R126

3k3

21%

R127

11k0

1%

R128

5k4

9

1%

R129

2k7

41%

R130

49k9

1%

C147

220pF

C148

100pF

C149

2.2

nF

C150

330pF

C151

680pF

R131

604r

1%

TP65

C152

OPE

NRIN

G

SLE

EVE

TIP

J21

R132

0R00

+

C153

6-

5+

7

U27-B AD

8606AR

R133

1k6

51%

R134

5k4

91%

R135

3k3

21%

R136

11k0

1%

R137

5k4

9

1%

R138

2k7

41%

R139

49k9

1%

C154

220pF

C155

100pF

C156

2.2

nF

C157

330pF

C158

680pF

R140

604r

1%

TP66

C159

OPE

N

R141

0R00

4V-

8V+

U27-C

AD

8606AR

C54

4V-

8V+U

26-C

AD

8606AR C55

1939_O

UT4

-

1939_O

UT4

+

CM

1939_O

UT5

-

1939_O

UT5

+

CM

1939_O

UT6

-

1939_O

UT6

+

CM

1939_O

UT7

-

1939_O

UT7

+

CM

A3V3

Figure 25. Analog Audio Output Filters (2) Schematics


Rev. PrA | of 30

DIG

ITAL

AU

DIO

I/O

INOU

T

Dig

ital

Hea

der

1

Dig

ital H

eader

1AD

1940 I

npu

t is

Sla

ve b

y D

efau

ltSet

ext

ernal

sou

rce

to L

RCLK

/BCLK

Mas

ter

AD

1940 I

npu

t Chan

nel

s 0-7

in I

2S M

ode

Dual

Wire

8-C

han

nel

TD

M:

Ch 0

-7 o

n S

DATA

_IN

3, Ch 8

-15 o

n S

DATA

_IN

2Sin

gle

Wire

16-C

han

nel

TD

M:

Ch 0

-15 o

n S

DATA

_IN

3

OU

T

IN

Dig

ital

Hea

der

2

Dig

ital H

eader

2AD

1940 O

utp

ut

0 c

an b

e M

aste

r or

Sla

veAD

1940 O

utp

ut

Chan

nel

s 0-7

in I

2S M

ode

Dual

Wire

8-C

han

nel

TD

M:

Ch 0

-7 o

n S

DATA

_O

UT0

Sin

gle

Wire

16-C

han

nel

TD

M:

Ch 0

-15 o

n S

DATA

_O

UT0

OU

T

IN

Dig

ital

Hea

der

3

Dig

ital H

eader

3AD

1940 O

utp

ut

1 c

an b

e M

aste

r or

Sla

veAD

1940 O

utp

ut

Chan

nel

s 8-1

5 in

I2S M

ode

Dual

Wire

8-C

han

nel

TD

M:

Ch 8

-15 o

n S

DATA

_O

UT4

Sin

gle

Wire

16-C

han

nel

TD

M:

No

outp

uts

on t

his

hea

der

1 3 5 7 9

2 4 6 810

11

13

15

17

19

12

14

16

18

20

J22

HEAD

ER_20W

AY_

POL

5B1 4

A1

6O

1

U2-B

74H

C125

9B3

10

A3

8O

3 U2-C

74H

C125

12

3SW

3

Dig

ital

Hea

der

1 M

CLK

Direc

tion

R142

R143

R14522r1

TP67

R146

R147

12

3SW

4

Dig

ital

Hea

der

2 M

CLK

Direc

tion

9B3

10

A3

8O

3

U33-C

74H

C125

5B1

4A1

6O

1U33-B

74H

C125

1 3 5 7 9

2 4 6 8 10

11

13

15

17

19

12

14

16

18

20

J23

HEAD

ER_20W

AY_

POL

R148

22r1

TP68

R149

R150

12

3SW

5

Dig

ital

Hea

der

3 M

CLK

Direc

tion

2B0

1A0

3O

0

U33-A

74H

C125

12

B2

13

A2

11

O2U33-D

74H

C125

1 3 5 7 9

2 4 6 8 10

11

13

15

17

19

12

14

16

18

20

J24

HEAD

ER_20W

AY_

POL

R151

22r1

TP69

12

B2

13

A2

11

O2 U2-D

74H

C125

R171

C177

1.0

uF

C178

1.0

uF

LRCLK

_IN

TF_IN

BCLK

_IN

TF_IN

SD

ATA

_IN

TF_IN

1SD

ATA

_IN

TF_IN

2SD

ATA

_IN

TF_IN

3

EXT_

MCLK

_H

1

LRC

LK_IN

TF_IN

BC

LK_IN

TF_IN

SD

ATA_IN

TF_IN

1

SD

ATA_IN

TF_IN

2

SD

ATA_IN

TF_IN

3

D3V3

1940_LR

CLK

_O

UT0

1940_BCLK

_O

UT0

1940_SD

ATA

_O

UT1

1940_SD

ATA

_O

UT2

1940_SD

ATA

_O

UT3

EXT_

MCLK

_H

2

1940_LR

CLK

_O

UT0

1940_BC

LK_O

UT0

1940_SD

ATA_O

UT1

1940_SD

ATA_O

UT2

1940_SD

ATA_O

UT3

D3V3

D3V3

1940_SD

ATA

_O

UT7

1940_SD

ATA

_O

UT6

1940_SD

ATA

_O

UT5

1940_BCLK

_O

UT1

1940_LR

CLK

_O

UT1

EXT_

MCLK

_H

3

1940_LR

CLK

_O

UT1

1940_BC

LK_O

UT1

1940_SD

ATA_O

UT5

1940_SD

ATA_O

UT6

1940_SD

ATA_O

UT7D3V3

D3V3

D3V3

SD

ATA_IN

TF_IN

0SD

ATA

_IN

TF_IN

0

1940_SD

ATA

_O

UT0

H2_M

CLK

H3_M

CLK

1940_SD

ATA

_O

UT4

1940_SD

ATA_O

UT4

D3V3

H1_M

CLK

Figure 26. Digital Audio I/O Schematics


Rev. PrA | of 30

S/P

DIF

IN

TERFA

CE

S/P

DIF

Rx

Serial Port

:CS8416 is

Mas

ter

by D

efau

ltAD

1940 I

npu

t is

Sla

ve b

y D

efau

ltAD

1940 I

npu

t Chan

nel

s 6-7

in I

2S M

ode

S/P

DIF

Inpu

t Sel

ection

SPD

IF T

ransm

itte

r

S/P

DIF

Tx

Serial Port

:CS8406 is

Sla

ve b

y D

efau

ltSet

AD

1940 S

eria

l Outp

ut

1 t

o M

aste

rAD

1940 O

utp

ut

Chan

nel

s 8-9

in I

2S M

ode

Err

or

Audi

o

96kH

z

ISO

LATE G

RO

UN

D

ISO

LATE G

RO

UN

D

C160

10nF

C161

10nF

C162 0.1

0uF

R152

10k0

J25

CTP

-021A-S

-YEL

R153

75R0

L6

600Ohm @ 100MHz

2

GN

D

3 DVD

D

1O

UT

U35

TORX147L(

FT)

SW

6D

PDT

Slid

e

C163

0.1

0uF

C164

0.1

0uF

L7

600Ohm @ 100MHz

L8

600Ohm @ 100MHz

4RXP0

5RXN

8FI

LT6 VA

23 V

D

26

SD

OU

T28

OLR

CK

27

OSCLK

24

RM

CK

10

RXSEL1

11

RXSEL0

12

TXSEL1

13

TXSEL0

19

C18

U17

RCBL

14

NV/R

ERR

15

AU

DIO

3RXP1

2RXP2

1RXP3

20

TX

16

96KH

Z

21 V

L

9RST

25

OM

CK

7

AG

ND

22

DG

ND

U36

CS8416

C165

22nF

C166

1.0

nF

R154

3k0

1

C167

0.1

0uF

R155

47k5

R15

6

47k5

R157

47k5

R15

847

k5

R15

947

k5

+

C168

10uF

+

C169

10uF

TP70

1 4

5 8

2

6

U37

SC937-0

2_AES_TR

AN

SFO

RM

ER

1GN

D

2 DVD

D

3IN

PUT

U38

TOTX

147L(

FT)

R161

374R

R162

90R9

R163

10k0

L9

600Ohm @ 100MHz

C170

0.1

0uF

J26

CTP

-021A-S

-YEL

14

SD

IN

12

ILRCLK

13

ISCLK

21

OM

CK

3EM

PH

16

CEN

1CO

PY/C

28

ORIG

4SFM

T0

9RST

6VD

23VL

26

TXP

25

TXN

24

H/S

19

AU

DIO

10

APM

S

20

HW

CK0

11

TCBLD

27

HW

CK1

22GND

5SFM

T12

NC1

7N

C2

8N

C3

17

V15

TCBL

18

U

U39

CS8406_H

ARD

WARE

C171

0.1

0uF

C172

0.1

0uF

R164

47k5

+

C173

10uF

+

C174

10uF

C175

10nF

1

2

D5

Red

Diffu

sed

R165

392R

1

2

D6

Gre

en D

iffuse

dR166

392R

53A

63Y

U40-C

74H

C04D

-T

94A

84Y

U40-D

74H

C04D

-T

11

5A

10

5Y

U40-E

74H

C04D

-T

13

6A

12

6Y

U40-F

74H

C04D

-T

1

2

D7

Yello

w D

iffuse

dR167

392R

C176

0.1

0uF

11A2 1Y

U40-A

74HC04D-T

32A4 2Y

U40-B

74HC04D-T

R168

0R00

R169

0R00

1 2 3 4 5 6 7 8910

11

12

13

14

15

16

R160

56R0

SPD

IF_RX_SD

ATA

SPD

IF_RX_LR

CLK

SPD

IF_RX_BCLK

SPD

IF_RX_M

CLK

D3V3

D3V3

RESET

D3V3

D3V3

NV/R

ERR

AU

DIO

96KH

Z

LO

HI

D3V3

RESET

1940_BCLK

_O

UT1

1940_LR

CLK

_O

UT1

1940_SD

ATA

_O

UT4

MCLK

D3V3

D3V3

NV/R

ERR

AU

DIO

96KH

Z

D3V3

D3V3

Figure 27. S/PDIF Interface Schematics


Rev. PrA | of 30

AU

DIO

DATA A

ND

CLO

CK R

OU

TIN

G

gnit

uo

Rkc

olC

oid

uA

tu

ptu

Og

nitu

oR

kcol

Coi

du

At

up

nIg

nitu

oR

ata

Doi

du

At

up

nIBA

1

2

3J4BA

1

2

3J5BA

1

2

3J6BA

1

2

3J7

B A 12

3

4

J8

12

J10

12

J11

12

J12

12

J13

TP34

TP35

TP36

TP37

TP38

TP39

TP40

TP41

TP42

TP43

TP44

TP45

TP46

TP47

B A 12

3

4

J9

1939_ASD

ATA

1

SD

ATA

_IN

TF_IN

0

1940_SD

ATA

_IN

0

1939_ASD

ATA

2

SD

ATA

_IN

TF_IN

1

1940_SD

ATA

_IN

1

1974_ASD

ATA

1

SD

ATA

_IN

TF_IN

2

1940_SD

ATA

_IN

2

SPD

IF_RX_SD

ATA

SD

ATA

_IN

TF_IN

3

1940_SD

ATA

_IN

3

1939_AD

C_LR

CLK

LRCLK

_IN

TF_IN

SPD

IF_RX_LR

CLK

1939_AD

C_BCLK

BCLK

_IN

TF_IN

SPD

IF_RX_BCLK

1940_LR

CLK

_O

UT0

1940_LR

CLK

_IN

1940_LR

CLK

_O

UT1

1940_BCLK

_O

UT0

1940_BCLK

_O

UT1

1940_BCLK

_IN

1940_LR

CLK

_IN

1940_BCLK

_IN

1940_BCLK

_IN

1940_LR

CLK

_IN

Figure 28. Audio Data and Clock Routing Schematics


Rev. PrA | of 30

BOARD SILKSCREEN AND PARTS PLACEMENT

Figure 29. Board Top Layer Layout


Rev. PrA | of 30

BILL OF MATERIALS Reference Qty Value Manufacturer Part Number Description Vendor Vendor Order # C105 C112 C119 C126 C133 C140 C147 C154 8 220pF Murata ENA

GRM1555C1H221JA01D

Multilayer Ceramic 50V NP0 (0402) Digi‐Key 490‐1293‐1‐ND

C107 C114 C121 C128 C135 C142 C149 C156 8 2.2nF NP0

Murata Electronics

GRM1885C1H222JA01D

Multilayer Ceramic 50V NP0 (0603 ) Digi‐Key 490‐1459‐1‐ND

C108 C115 C122 C129 C136 C143 C150 C157 8 330pF Murata ENA

GRM1555C1H331JA01D


C109 C116 C123 C130 C137 C144 C151 C158 8 680pF Panasonic EC

GRM1555C1H681JA01D


C11‐12 C15‐17 C32‐33 C39‐40 C168‐169 C173‐174 13 10uF Rohm TCP0J106M8R

SMD Tantalum Capacitor 0805 6.3V Digi‐Key 511‐1447‐1‐ND

C160‐161 2 10nF TDK Corp C1608C0G1E103J Multilayer Ceramic 25V NP0 (0603) Digi‐Key 445‐2664‐1‐ND

C165 1 22nF Murata ENA GRM21B5C1H223JA01L


C1‐7 C9‐10 C13‐14 C20‐25 C29 C31 C34‐38 C44 C46 C51‐61 C86 C99‐103 C162‐164 C167 C170‐172 C176 51 0.10uF Panasonic EC ECJ‐0EX1C104K

Multilayer Ceramic 16V X7R (0402) Digi‐Key

PCC13490CT‐ND

C175 1 10nF Panasonic EC ECJ‐1VB1H103K Multilayer Ceramic 50V X7R (0603) Digi‐Key PCC1784CT‐ND

C18 1 22pF Murata ENC GRM1555C1H220JZ01D


C19 1 27pF Murata ENA GRM1555C1H270JZ01D


C26 C41 2 5.6nF TDK Corp C1608C0G1E562J Multilayer Ceramic 25V NP0 (0603) Digi‐Key 445‐2666‐1‐ND

C27 C42 2 390pF Murata ENA GRM1555C1H391JA01D


C28 C43 C65‐66 C73‐74 C90‐91 C104 C111 C118 C125 C132 C139 C146 C153 16 10uF Panasonic EC EEE‐FC1C100R

Alum Electrolytic Capacitor FC 105deg SMD_B Digi‐Key PCE3995CT‐ND

C30 C45 C179 3 100uF Panasonic EC EEE‐FC1C101P Alum Electrolytic Capacitor FC 105deg SMD_E Digi‐Key PCE3996CT‐ND

C47‐50 C177‐178 6 1.0uF Taiyo Yuden EMK107BJ105KA‐TR

Multilayer Ceramic 16V X7R (0603) Digi‐Key 587‐1241‐1‐ND

C64 C67 C72 C75 C89 C92 6 120pF Murata ENA GRM1555C1H121JA01D


C78‐81 C95‐96 C110 C117 C124 C131 C138 C145 C152 C159 14 OPEN n/a n/a Do not stuff anything here n/a n/a C8 C62‐63 C68‐71 C76‐77 C87‐88 C93‐94 C166 14 1.0nF Murata ENA

GRM1555C1H102JA01D


C82‐85 C97‐98 C106 C113 C120 C127 C134 C141 C148 C155 14 100pF Murata ENA

GCM1555C1H101JZ13D


D1 1 Yellow Diffused

CML Innovative Tech

CMD15‐21VYD/TR8

Yellow Diffused 4.0millicandela 585nm 1206 Digi‐Key L62307CT‐ND

D2 D5 2 Red Diffused Lumex Opto SML‐LX1206IW‐TR Red Diffused 6.0millicandela 635nm 1206 Digi‐Key 67‐1003‐1‐ND

D3 D6 2 Green Diffused Lumex Opto

SML‐LX1206GW‐TR

Green Diffused 10millicandela 565nm 1206 Digi‐Key 67‐1002‐1‐ND

D4 1 Micro Commercial Co. DL4001‐TP

Passivated Rectifier 1A 50V MELF Digi‐Key

DL4001‐TPMSCT‐ND

D7 1 Yellow Diffused

CML Innovative Tech

CMD15‐21VYD/TR8

Yellow Diffused 4.0millicandela 585nm 1206 Digi‐Key L62307CT‐ND

J1 1 2x6 3M PBC06DAAN or cut PBC36DAAN Digi‐Key S2011E‐06‐ND


Rev. PrA | of 30

J10‐13 4 2‐Jumper Sullins Electronics Corp

PBC02SAAN; or cut PBC36SAAN

2‐pin Header Unshrouded Jumper 0.10"; use Shunt Tyco 881545‐2 Digi‐Key S1011E‐02‐ND

J14 1 RAPC722X Switchcraft Inc. RAPC722X Mini Power Jack 0.08" R/A TH Digi‐Key SC1313‐ND

J15‐21 7 SJ‐3523‐SMT CUI Inc. SJ‐3523‐SMT Sterero Mini Jack SMT Digi‐Key CP‐3523SJCT‐ND

J2 1 2x5 3M N2510‐6002RB 10‐way Shroud Polarized Header Digi‐Key MHC10K‐ND

J22‐24 3 2x10 3M N2520‐6002RB 20‐way Shroud Polarized Header Digi‐Key MHC20K‐ND

J25‐26 2 CTP‐021A‐S‐YEL

Connect‐Tech Products Corp. CTP‐021A‐S‐YEL

RCA Jack PCB TH Mount R/A Yellow

connect‐tech‐products.com CTP‐021A‐S‐YEL

J3‐7 5 3‐Jumper Sullins PBC03SAAN; or cut PBC36SAAN 3‐pos SIP Header Digi‐Key S1011E‐03‐ND

J8‐9 2 3jumper + 1jumper Sullins

PBC03SAAN; or cut PBC36SAAN 3‐pos SIP Header + 1 extra pin Digi‐Key

S1011E‐03‐ND +S1011E‐01‐ND

L1‐4 L6‐9 8 600 Ohm @ 100 MHz TDK Corp MPZ1608S601A

Chip Ferrite Bead 600 Ohm @ 100 MHz Digi‐Key 445‐2205‐1‐ND

L5 1 600 Ohm @ 100 MHz Steward HZ1206E601R‐10

Chip Ferrite Bead 600 Ohm @ 100 MHz Digi‐Key 240‐2415‐1‐ND

Q1 1 ZXTP25040DFHTA Zetex Inc. ZXTP25040DFHTA PNP Transistor 40V 3A SOT‐23 Digi‐Key

ZXTP25040DFHCT‐ND

R1 1 1k00 Panasonic EC ERJ‐2RKF1001X Chip Resistor 1% 63mW Thick Film 0402 Digi‐Key P1.00KLCT‐ND

R145 R148 R151 3 22R1 Vishay/Dale CRCW040222R1FKED

Chip Resistor 1% 63mW Thick Film 0402 Digi‐Key

541‐22.1LCT‐ND

R15 R142‐143 R146‐147 R149‐150 R152 R163 9 10k0 Rohm MCR01MZPF1002


RHM10.0KLCT‐ND

R153 1 75R0 Panasonic EC ERJ‐3EKF75R0V Chip Resistor 1% 100mW Thick Film 0603 Digi‐Key P75.0HCT‐ND

R154 1 3k01 Rohm MCR03EZPFX3011 Chip Resistor 1% 100mW Thick Film 0603 Digi‐Key

RHM3.01KHCT‐ND

R155‐159 R164 6 47k5 Rohm MCR01MZPF4752 Chip Resistor 1% 63mW Thick Film 0402 Digi‐Key

RHM47.5KLCT‐ND

R16 R22‐23 R29‐30 R36‐37 R43 R49 R55‐56 R62 12 237R Vishay/Dale

CRCW0402237RFKED

Chip Resistor 1% 63mW Thick Film 0402 Digi‐Key 541‐237LCT‐ND

R161 1 374R Rohm MCR03EZPFX3740 Chip Resistor 1% 100mW Thick Film 0603 Digi‐Key

RHM374HCT‐ND

R162 1 90R9 Rohm MCR03EZPFX90R9 Chip Resistor 1% 100mW Thick Film 0603 Digi‐Key

RHM90.9HCT‐ND

R165‐167 3 392R Rohm MCR03EZPFX3920 Chip Resistor 1% 100mW Thick Film 0603 Digi‐Key

RHM392HCT‐ND

R17‐18 R20‐21 R24‐25 R27‐28 R31‐32 R34‐35 R38‐39 R41‐42 R50‐51 R53‐54 R57‐58 R60‐61 24 5k76 Panasonic EC ERJ‐2RKF5761X

Chip Resistor 1% 63mW Thick Film 0402 Digi‐Key P5.76KLCT‐ND

R19 R26 R33 R40 R52 R59 6 OPEN Do Not Stuff OPEN Do Not Stuff OPEN OPEN

R2‐3 R10 R160 4 56R0 CTS Corp. 741X163560JP Resistor Network Isolated 8Res Digi‐Key 741X163560JPCT‐ND

R4 R78 R87 R96 R105 R114 R123 R132 R141 R168‐169 R171 12 0R00 Panasonic EC ERJ‐3GEY0R00V

Chip Resistor 5% 125mW Thick Film 0603 Digi‐Key P0.0GCT‐ND

R44‐47 R63‐64 R76 R85 R94 R103 R112 R121 R130 R139 14 49k9 Vishay/Dale

CRCW040249K9FKED


541‐49.9KLCT‐ND

R5 1 10k0 Panasonic EC EXB‐D10C103J Resistor Network Bussed 8Res Digi‐Key U9103CT‐ND R6 R13‐14 R77 R86 R95 R104 R113 R122 R131 R140 11 604R Vishay/Dale

CRCW0402604RFKED


R7 R48 R65‐69 7 100R Rohm MCR01MZPF1000 Chip Resistor 1% 63mW Thick Film 0402 Digi‐Key

RHM100LCT‐ND


Rev. PrA | of 30

R70 R79 R88 R97 R106 R115 R124 R133 8 1k65 Vishay/Dale

CRCW04021K65FKED


541‐1.65KLTR‐ND

R71 R74 R80 R83 R89 R92 R98 R101 R107 R110 R116 R119 R125 R128 R134 R137 16 5k49 Rohm MCR01MZPF5491


RHM5.49KLCT‐ND


CRCW04023K32FKED


541‐3.32KLCT‐ND

R73 R82 R91 R100 R109 R118 R127 R136 8 11k0 Yageo RC0402FR‐0711KL


311‐11.0KLRCT‐ND


CRCW04022K74FKED


541‐2.74KLCT‐ND

R8 R12 2 562R Vishay/Dale CRCW0402562RFKED


R9 R11 2 49R9 Rohm MCR01MZPF49R9 Chip Resistor 1% 63mW Thick Film 0402 Digi‐Key

RHM49.9LCT‐ND

SW1 1 8x SPST CTS Corp 219‐4LPST 4 Section SPST SMD Switch Raised Act Digi‐Key

CT2194LPST‐ND

SW2 1 SPST‐NO Tyco/Alcoswitch FSM6JSMA Tact Switch 6mm Gull Wing Digi‐Key 450‐1133‐ND

SW3‐5 3 SPDT Copal Electronics CAS‐120TA SPDT Slide Switch SMD J Hook Digi‐Key CAS120JCT‐ND

SW6 1 DPDT Slide E‐Switch EG2207 DPDT Slide Switch Vertical Digi‐Key EG1940‐ND

TP1‐70 70 5002 Keystone Electronics 5002 Mini Test Point White .1" OD Digi‐Key 5002K‐ND

U1 1 AD1940YSTZ Analog Devices Inc. AD1940YSTZ

SigmaDSP Multi‐Channel 28‐bit Audio Processor

Analog Devices Inc. AD1940YSTZ

U17 1 ADM811TARTZ‐REEL7

Analog Devices Inc.

ADM811TARTZ‐REEL7

uP Voltage Supervisor Logic Low RESET Output

Analog Devices Inc.

ADM811TARTZ‐REEL7

U18‐27 10 AD8606ARZ Analog Devices AD8606ARZ Low‐Noise Rail‐to‐Rail CMOS Op Amp

Analog Devices AD8606ARZ

U2 U33 2 74AC125SC Texas Instruments 74AC125SC

IC BUFFER QUAD 3 STATE 14‐SOIC DigiKey 74AC125SC‐ND

U3 1 AD1939YSTZ Analog Devices AD1939YSTZ 4 ADC/8 DAC with PLL Analog Devices AD1939YSTZ

U35 1 TORX147L(FT) Toshiba TORX147L(FT)

15Mb/s Fiber Optic Receiving Module w/ Shutter Digi‐Key

TORX147LFT‐ND

U36 1 CS8416‐CZZ Cirrus Logic CS8416‐CZZ 192KHZ DGTL RCVR 28‐TSSOP Digi‐Key 598‐1124‐5‐ND

U37 1 SC937‐02 Scientific Conversion SC937‐02

110 Ohm AES/EBU Transformer

www.scientificonversion.com SC937‐02

U38 1 TOTX147L(FT) Toshiba TOTX147L(FT)

Fiber Optic Transmit Module 15Mb/s w/ Shutter Digi‐Key TOTX147L‐ND

U39 1 CS8406‐CZZ Cirruc Logic CS8406‐CZZ 192kHz SPDIF Transmiter Newark In One 88H6508

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ORDERING GUIDE ORDERING GUIDE Model Description EVAL-AD1940AZ Evaluation Board

ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

functional block diagram - analog devices€¦ · board layout block diagram analog inputs analog...

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