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VLSI II Analog TP-2006/2007: VLSIANA2007_TP01.doc

V0.0 LSM March 2007

VLSI II PRACTICAL LABORATORY SESSION No. 1

First Name Family Name

Date Evaluation Document

Visa Evaluation Design

Visa

1. OBJECTIVES During this first practical exercise session, you will get familiar with the working environment and software that you will use throughout the next few weeks. You will first learn how to properly configure and run the Design Framework, after what you will start doing schematic entry while learning the basics of using the software. Note that this document contains important information that will help save you lots of trouble during the remaining exercise sessions, so it is your best interest to read it from start to finish, even though the manipulations may seem very simple.

2. INTRODUCTION TO THE DESIGN FRAMEWORK The software used throughout these practical exercises is referred to as Cadence Design Framework II (DFII). It consists of a number of tools integrated in a common environment:

• The Command Interpreter Window (CIW) is the main window that gives access to the different tools through menu commands, or through direct entering of commands in the scripting language named SKILL. It is also the windows where information and error messages are reported.

• The Library Manager is the tool to manage your design data such as circuit schematics, layouts, simulation testbenches etc...

• Virtuoso is the platform for creating and simulating your designs. It consists of the Schematic Editor, the Layout Editor, and the Analog Design Environment (ADE) which is the graphical front-end to the circuit simulator.

LABORATOIRE DE SYSTEMES MICROELECTRONIQUES

EPFL STI – IMM – LSM

ELD

Station nº 11

CH-1015 Lausanne

Téléphone :

Fax :

E-mail :

Site web :

+4121 693 6955

+4121 693 6959

lsm@epfl.ch

lsm.epfl.ch

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• Assura is the suite for full-custom layout verification and parasitics extraction. It allows to check your layout against your schematic using the LVS (Layout vs Schematic) tool, to verify that your layout is compliant with the foundry’s design rules using the DRC (Design Rules Check) tool, and to extract from your layout a detailed schematic containing parasistics for accurate post-layout simulation with the RCX (Parasitics Extraction) tool.

3. CONFIGURING AND RUNNING THE SOFTWARE

3.1. SETTING UP YOUR WORKING ENVIRONMENT Each project is usually held in a separate directory, which groups together the different configuration files and the design data. Because many tools use configuration files that are stored in the current directory, the project directory actually defines a working environment. We will now create a directory for our project. You will use the same directory throughout the laboratory sessions.

Create a directory for your project.

[5]edatp0@immsunsrv1-edatp0> mkdir vlsi2007_analog [6]edatp0@immsunsrv1-edatp0> cd vlsi2007_analog

3.2. RUNNING DFII FOR THE FIRST TIME When you run the software for the first time, some additional configuration steps need to be taken. We will proceed step-by-step for the first time.

Make sure you are in your project directory

edatp0> cd ~/vlsi2007_analog

It is extremely important to always start the tools from your project directory. Because your project directory will contain many configuration files, the tools will not work as expected when run from a different place. Even worse, it may override other configuration files, especially when run from your home directory – this is a common mistake.

Run the software by typing :

vlsi2007_analog> cds ams_cds –tech c35b4 –mode fb &

Since this is our first time running the design framework, we need to specify the technology to be used (-tech option). We chose the c35b4 technology, which stands for

0.35μm CMOS with 4 metal layers. The software can run in different modes (-mode option), but we will allways chose the front-to-back (fb) mode for our needs. The trailing & runs the command in the background, so that the terminal does not freeze.

At this point, the software should start and the CIW window should appear, followed by the Library Manager.

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Figure 1 - The CIW (Command Interpreter Window)

Figure 2 - The Library Manager Window

A window will pop up prompting you to select a process option to use. Select the C35B4M6 option.

Figure 3 - Process option selection

A text window displaying information about the design kit will also pop up. You don’t need to read its content. Select File→Off At Startup from the window menu to keep this window from showing up every time at startup.

Exit the design framework by either :

• choosing File→Exit from the CIW menu,

• closing the CIW window, or

• typing exit in the command prompt at the bottom of the CIW window.

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3.3. THE LIBRARY MANAGER AND DESIGN HIERARCHY The Library Manager is the graphical interface to manipulate the design data in the DFII environment. It should appear automatically at startup, but if it does not or if you accidentally close it, you can always open it by choosing Tools→Library Manager from the CIW menu.

In the DFII environment, all the design data is stored in a collection of libraries. Libraries gather together sets of related cells, each cell in a library being an individual circuit. Cells have multiple views, that are different ways of representing the circuit. For example, the same circuit can be represented as a symbol, a full circuit schematic, or a mask layout. The figure below pictures the organisation of cells and views in a library as a tree. The term cellview refers to a particular view of a particular cell, i.e. actual design data.

Figure 4 - Sample library structure

By default, a number of libraries will be available to you: some are the tool’s default, and some are provided by the foundry design kit. Following is a list with a brief description of the most important ones:

basic contains mostly graphical elements for circuit schematics.

analogLib contains many elements useful for simulation such as voltage and current sources, ideal resistors, capacitors and inductors, switches etc… These cells are mostly used to create simulation testbenches.

PRIMLIB contains all the primitive devices (MOSFETS, resistors, capacitors, inductors, …) from the foundry design kit. You will use these devices to create your own designs.

CORELIB contains standard logic cells from the foundry design kit. In the next steps, we will create a new library for your designs, and experiment some features of the library manager.

Make sure you are in your project directory, and start the software.

edatp0> cd ~/vlsi2007_analog

vlsi2007_analog> ams_cds –m fb &

Now that the tool has been configured, specifying the technology(-tech) is not necessary anymore. We still must specify the mode (-mode, abbreviated as –m).

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Creating an new library

Using the library manager, create a new library by choosing File→New→Library… from the menu. You are prompted to enter a name for your library : enter VLSITP. Below is a space to specify the directory where the data will be physically stored on the disk. You don’t have to change anything there.

You will be prompted to attach a technology file to the new library. The technology file contains technology-specific information, mostly related to layout, and is provided by the foundry design kit. Select Attach to an existing techfile and then choose the technology library TECH_C35B4.

Creating cellviews

Now create a cellview in your new library. Select VLSITP in the Library field, and then choose File→New→CellView… from the menu. Enter test as the cell name, and schematic as the view name.

Notice the Tool field. When changing the tool, the view name changes. This is because different tools are associated with different views : schematic editor, symbol editor, layout editor (Virtuoso), etc… Each view type has a standard name (i.e. schematic for a circuit schematic) but they can be changed.. It is however advised to keep the default names to avoid problems.

A cell named test is created, with one view named schematic, and the schematic editor appears to edit your new cellview.

Choose Design→Check And Save from the schematic editor menu, to have the cellview data written to the disk. Then close the schematic editor.

Deleting, copying and renaming cellviews

In the Library Manager, select the VLSITP library, then right-click on the test cell. In the context menu, choose Delete… then press OK. The cell is deleted with all its views.

You can experiment with different commands such as copying, renaming and deleting libraries, cells and views.

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3.4. THE GRAPHICS EDITOR Different tools that need graphical editing, as the schematic editor, symbol editor and the layout editor, use a similar interface named the graphics editor. We will now experiment with the features of graphical editing by creating a simple circuit schematic.

Create a new schematic cellview named DiffPair / schematic in your VLSITP library. The schematic editor will appear.

In the next steps, we will create a simple schematic shown on the figure below, while learning to use the graphics editor.

Figure 5 - The schematic Editor Window

Creating instances

The term instance denotes the occurrence of a cell inside of another. A cell can be instanciated multiple times in another. Instances define a hierarchical relationship between cells, where the containing cell is higher in the hierarchy than the instanciated cell.

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Choose Add→Instance from the menu, or use the keyboard shortcut for this command by simply pressing i on the keyboard.

Most commands have a keyboard shortcut, or bindkey. They are shown on the right of the command name on the menus. Learn to use these bindkeys to save you a lot of time.

An option form appears, which prompts you for the library / cell / view name of the cellview you wish to instantiate. Type PRIMELIB / nmos4 / symbol, or, alternatively, click on the Browse button and select this cell in the library manager.

Use the nmos4 and pmos4 cells from the PRIMLIB library for N- and P- MOS transistors.

Set appropriate size of transistors. Select the object (being one of the transistors in your design) with the left mouse button. Use either the Edit→Properties→Objects pull-down menu or press “q”.

A pop-up window will appear as show in the previous Figure. Set the gate width and length as provided in Figure 5.

Repeat this process until you have modified all the transistors in the design

When you are done, Check and Save your schematic. Correct any errors or warnings, until no more are reported.

Notice how you can add more instance as long as you do not cancel the command. Many commands work in this way: activating the commands bring you into a new “mode” that lasts until you press Escape. Some don’t, and work only once.

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Creating pins

Pins define the connections between a cell and its environment. Pins have a name and a direction (input, output or inputOutput). The direction is used to check for wrong connections (i.e. two outputs shorted together, or floating inputs). inputOutput pins are typically used for power supplies.

Choose Add→Pin from the menu. The option form appears, prompting you to enter the name of the pin as well as different options (see figure below). Enter vin as the pin name, and place the pin on the schematic. Once this is done, return to the option form and enter the name vo for the second pin. Change the pin direction to output and place the pin on your schematic. Then press Escape or click Cancel on the form. Repeat this work for the rest of pins.

Creating wires and labeling nets

Wires define the connections between the different instances in a cell. Wires connect to the pins or to other wires. All connecting wires – that are electrically at the same potential – define a net. Nets can be labeled to make the schematic and simulation results more readable – if they are not labeled, they are assigned an automatic name.

Choose Add→Wire (narrow) from the menu, and add wires to your schematic to connect the different elements as shown on the figure.

Use the Zoom (Window→Zoom→Zoom In… or z) and Fit (Window→Fit… or f) commands to adjust the zoom. You can even use these commands while in the middle of creating a wire without interrupting.

Choose Add→Wire Name from then menu. In the option form, type ABC as the wire name and place it anywhere on the wire which connects the three inverters together.

If your label is not placed on a wire, you will be prompted to click on a wire to which the label should be attached..

Moving and stretching objects

Left click on an inverter instance to select it. It should highlight. Then choose Edit→Move from the menu or press Shift+m. Left click anywhere to define the reference point,

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then drag the inverter to a new location and left click again to execute the move.

Multiple objects can be selected at the same time. Left-click and drag the mouse to select multiple objects. Hold the Shift key whick clicking to add objects to the selection, and the Ctrl key to remove objects from the selection.

Choose Edit→Undo or press u to cancel the move. Then press Ctrl+d to clear the selection. Then press Shift+m to start a new move. Click on an inverter, then drag it to a new location and release it. Press u to undo the move, and click on another inverter then move it. Undo the move again and press Escape.

Commands that work on objects, such as move, stretch or delete,need a selection to work on. If an object or a set of object is selected before applying the command, it will operate on this existing selection. If not, you are prompted to select objects first.

Notice two differences : when there is an exisiting selection, you need to select a reference point. Also, when there is an existing selection, you can move the object only once before the command exits, while you can move multiple objects when there is no prior selection. Thus, in one case you can apply multiple actions, sqeuentially, to a set of selected objects, and in the other case you can apply the same action to a number of sequentially selected objects. Remember Ctrl+d to clear the selection.

Repeat the same manipulations with the Stretch command instead (Edit→Stretch or m).

Observe that with the stretch command, wires connected to the instance are rerouted to keep the connections, while with the move command, the selected objects were moved regardless of the connections.Stretch also allows to reshape existing wires.

When moving or stretching an object, try pressing the F3 key before releasing the object to its new location. In the option form showing up, there are buttons for rotating and mirroring the instance. Try these.

Many commands have an option form which does not allways show up automatically. Use the F3 key to show or hide this option form.

Deleting objects The Delete command (Edit→Delete or Del) works in the same way as Move or Stretch with respect to the

selection. Objects can be accidentally deleted if they are selected prior to pressing Del.

Checking and saving the schematic

Choose Design→Check and Save (or Shift-X) to save your design. The schematic will be checked for errors, and a dialog box will inform you if there is any error or warning.

When something goes wrong, always check the CIW for error or warnings. Much more information is reported there.

Generating the symbol A symbol is a graphical abstraction of a cell that provides only the necessary information for using the cell at a higher hierarchical level – that is, it provides information on how to connect the cell from the outside. Symbols also provide visual clue on the function of the underlying circuit. As such, symbols are only made of pins (connections) and graphical shapes.

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Symbols can be created manually by choosing the Composer-Symbol tool when creating a new cellview, then drawing the shapes and pins. However, it is also possible and much more convenient to have them generated automatically. A square box with pins is generated, that can then be modified if wanted – it provides a good starting point.

From the Schematic Editor menu, choose Design→Create Cellview->From Cellview.

In the first form coming up, all options should be set correctly. Press Ok.

In the second form, you get a chance to specify the location of the pins on your symbols. It is common to have input pins on the left, output pins on the right, and power/ground pins on the top and bottom of the symbol. When you are done, press Ok.

Do any changes you like to your symbol, then Check and Save it.

3.5. CREATING A HIERARCHICAL CIRCUIT In the following steps, you will create the circuit schematic for a 4-to-1 multiplexer. You will first create the schematic for a 2-to-1 multiplexer using standard cells, then use this cell to create the 4-to-1 multiplexer in a hierarchical manner.

Create a new schematic in your VLSITP library. Name it DiffPair2.

Draw the schematic as shown on figure 6. Use the DiffPair subcircuits from the VLSITP library ..

Figure 6 - The circuit schematic of two differential pairs

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When you are done, Check and Save your schematic. Correct any errors or warnings, until no more are reported.

Create a symbol for the DiffPari2.

Create another new schematic in your VLSITP library. Name it ADC2.

Figure 7 - The 2-bit ADC circuit schematic

Draw the schematic as on figure 7, using your own ADC2 symbol.

Create a symbol for the 2-bit ADC.

Checkpoint Please call an assistant and show him/her that you have reached this point before working on further steps Visa

Moving up and down the hierarchy Now that you have designed a hierarchical schematic, you can experience moving up and down the hierarchy.

Open the ADC2 schematic.

Select one of the instances of your ADC2 cell.

Choose Design→Hierarchy→Descend Edit or press Shift+e. You will be prompted to select a view: choose the schematic view.

The current schematic will be changed to DiffPair2. To return up the hierarchy to ADC2, choose Design→Hierarchy→Return or press Ctrlt+e.

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4. CREATING THE TEST BENCH

Create a new schematic view in your library (VLSITP) named DiffPair2_tb.

Instantiate the symbol of the ADC2 schematic that you have already generated in previous section into the new schematic entry window. Then complete the schematic as shown in Figure 6.

Figure 8 - The schematic of the test bench for the ADC2

For the DC source use vdc component from analogLib library, and set the DC voltage property to 3.3V.

For the load capacitors shown in the schematic, use the cap element from analogLib, and edit the capacitance property to enter the provided value in the schematic (50 fF).

For the ground symbol, use gnd cell symbol view from analogLib library. gnd symbol

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will provide the zero reference voltage level for your simulation.

Use Add→Wire Name or pres “l” to place labels accordingly on to input/output signals as shown in Figure 86.

Check and Save your design.

Parameter Value

DC voltage: V2 vdc V

DC Voltage: V0 3.3 V

DC Voltage: V1 0.0 V

DC Current: I0 100u A Table. 1. Parameters for the inputs.

Checkpoint Please call an assistant and show him/her that you have reached this point before working on further steps Visa

SIMULATING THE PERFORMANCE OF THE DESIGN

For opening of the simulation environment click on Tools→Analog Environment on the very left upper corner of the schematic window. Analog Design Environment window will pop-up, Fig. 9.

Figure 9- The Analog Design Environment (ADE) Window

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Setting up Variables and Outputs

Copy your design using Variables→Copy from Cellview menu command.

The variables will appear in the “Design Variables” pane (Figure 10).

Double click on each of the variables available in the list and set their values to nominal value (in this case vdc = 1.6 V).

Use Outputs→To be Plotted/Select on Schematic command in the Analog Design Environment.

Select vi, b0 and b1 nets by clicking on them sequentially (by this all selected nets will be highlighted in different colours).

Also, select the vdd pin of your ADC2 to monitor the current consumption of the design (a coloured circle will appear around the selected pin).

All selected signals should appear in the “Outputs” pane of the Analog Design Environment. The final setup for the DC simulation should look like the one shown in Figure 10.

DC ANALYSIS

Setup a DC analysis in order to simulate the voltage transfer curve (VTC) of the NAND2 gate. This analysis allows you to verify the DC characteristics of the design, like switching threshold, noise margins, logic levels, etc.

Use Analysis→Choose in order to select the type of the simulation you would like to run.

In the pop-up window, edit the necessary properties as shown in Figure 10.

Use Session→Save State to save your simulation setup so you can reload it at a future time

To run simulation use Simulation→Netlist and Run command from the Analog Design Environment window.

This command will generate the netlist of your design automatically and run the specified simulation setup on this netlist. The progress of the simulation is displayed on the screen as a text window. As soon as the simulation is completed, a “Waveform Window” appears with all the selected signals displayed in a single graph.

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Figure 10- DC simulation setup

Working with the “Waveform Window”

To split the Waveform window view into multiple graphs use Axes→To Strip command.

To combine the waveforms on one graph drag and drop them. The final waveform should look like the one presented in Figure 11 (combine only voltage curves).

To zoom, use the Zoom menu or press “z”

X/Y coordinates pointed by the mouse are displayed on the top of the window, near the title bar.

Figure out the switching threshold from the waveforms.

Now quit the Analog Design Environment by simply selecting Session→Quit.

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Figure 11- DC simulation results

5. CREATING LAYOUT

THE LAYOUT EDITOR

As mentioned in the laboratory session no.1 there are different tools used for graphical editing. The tool used as a layout editor is called Virtuoso Layout Editor. To start a tool you create a new cellview in your library. The goal of this session will be to draw a layout for DiffPair gate and check it for Design Rules.

Now create a cellview in your new library. Select VLSITP library and DiffPair cell and choose File→New→CellView.

Select layout as the view name.

Notice the Tool field. There it should be written Viruoso for a layout editor.

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All available layers and their related design rules are provided in the AMS 0.35um technology Design Rule Manual (DRM) – confidential yellow notebook. Minimum spacing between various layers and minimum width specification of all layers are the most critical rules to be respected.

Figure 12 – Cross-Section and MOS transistor Layout In the Figure 13 you can see the initial Virtuoso Layout Editor window in which you will draw your layout and LSW-Layer Selection Window.

For each layer that you can observe in LSW - Layer Selection Window (Figure 13) there is a separate page in DRM containing a certain number of rules. Most important layers are NTUB, DIFF, POLY1, PPLUS, NPLUS, CONT and MET1 (see Figure 12).

Each rule in DRM consists of a “Rule” code, “Description” and “Value”. For example look at the page 21 at the rule with the code CO.S.1. Description is: Minimum CONT spacing and Value is 0.3um.

In the following online Layout tutorial for any of the drawing steps a page and a Rule code will be given.

Wafer Cross-Section MOS Transistor Layout

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Figure 13 – Initial Layout Editor window

Each layer in LSW consists of layer texture, layer name and layer type (Figure 14 is an example for POLY1 dg layer). You should always use dg layer type (not pn) unless it is explicitly said to use other.

Left click on the layer in LSW which makes that layer selected (marked with red frame in Figure 16) and then you can use it for drawing.

There are 4 possible types of selection in the LSW window. AV which means all the layers are visible, NV makes all the layers invisible, AS which means that all the layers are selectable and NS which makes none of the layers selectable (NV clicked in Figure 14).

Figure 14 – LSW in detail

Detailed steps for drawing a layout of NOR circuit are shown in an online Layout Tutorial that you can access at http://moodle.epfl.ch/mod/resource/view.php?id=9282. Please pass carefully through this tutorial in order to learn how to do basic operations. Each step is explained and keyboard shortcut as well as menu shortcut is given. Moreover in each

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step involved design rules are listed with their names and pages in DRM.

Short list of the most important keyboard shortcuts is given in the following table.

Design Rules Check (DRC)

After drawing a layout it is necessary to do a Design Rules Check (DRC).

Do a Design→Save or press “F2”.

Use Assura→Run DRC from Layout Editor menu to start DRC dialog.

Click on Set Switches field and do the selection according to Figure 15.

Click OK to run DRC.

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Figure 15 – Assura set-up

After DRC finishes in case there are errors the Error Layer Window will pop-up (example in Figure 16). To correct the error do the following

Select error in Error Layer Window. The error will be marked in the Layout Editor.

Read description and if necessary find the error according to Rule code in DRM.

Correct the error.

Repeat the procedure until all the errors are corrected.

Do a Design→Save or press “F2”.

Use Assura→Close Run from the menu to stop current check.

Repeat DRC procedure until you get the message “No DRC errors found” (Figure 17).

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Figure 16 – Example for error in layout and its description

Figure 17 – Clean DRC – no errors

Checkpoint Please call an assistant and show him/her that you have reached this point before working on further steps Visa

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Once you have a DRC clean layout, run the LVS tool (Assura -> LVS). LVS tool is to compare the netlist of your main schematic to the netlist which is extracted from layout. You should find the reason for each mismatch report and try to solve it on your layout.

Figure 18- LVS windows pops up after running LVS

Figure 19- Typical LVS error report page

Once your LVS is clean, create an extracted view (Assura -> RCX) of the layout. In this way the netlist extracted from your layout will be created. Now, you can re-run your simulation with the new netlist includes parasitic effects raised in layout.

Then run a post layout simulation using the same simulation environment that you used for the pre layout simulation. For this purpose you just need to change the set-up of your ADE. In ADE just add “av_extracted” in Setup -> Environment menu as the first item on the switch view list:

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Figure 20- Set up for post-layout simulation

Checkpoint Please call an assistant and show him/her that you have reached this point before working on further steps Visa