frequency synthesizers -...

Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Frequency Synthesizers

Phase-Locked Loops

10-1 Ching-Yuan Yang / EE, NCHUPLL ICs

One-port oscillators

Decaying impulse response of a tank

Adding of negative resistor to cancel loss in RP

Use of an active circuit to provide negative resistance


Oscillator using negative input resistance

Oscillator using negative input resistance of a source follower with positivefeedback. For oscillation build-up, RP 2/gm 0. If the small-signal resistance presented

by M1 and M2 to the tank is less negativethan RP, then the circuit experienceslarge swings such that each transistor isnear off for part of the period, therebyyielding an “average” resistance of RP.

Differential version


Calculation of Intrinsic Phase Noise in Oscillators

Noise sources in oscillators are put in two categories Noise due to tank loss Noise due to active negative resistance

We want to determine how these noise sources influence the phase noise ofthe oscillator.


Separation into Amplitude and Phase Noise

Equipartition theorem (see Tom Lee, p 659) states that noise impact splitsevenly between amplitude and phase for Vsig being a sine waveAmplitude variations suppressed by feedback in oscillator

22012 ( )

Phase 2out

pv fkTF f Rf Q f

(single-sided)


Output Phase Noise Spectrum (Leeson’s Formula)

All power calculations are referenced to the tank loss resistance, Rp

( ) 10 logL f Spectral density of noise

Power of carrier

22 2, / 2 1, ( )sig rms out

sig noisep p p

AV vP S fR R R f

20( ) 2 ( ) 1( ) 10 log 10 log

2noise

sig sig

S f fkTF fL fP P Q f


Example: Active Noise Same as Tank Noise

Noise factor for oscillator in this case is

Resulting phase noise

22

( ) 1 2pn nRnR iiF f

f f

204 1( ) 10 log

2sig

fkTL fP Q f


Phase noise in oscillators

Measured in dB below carrier per unit bandwidth.

32

1/02( ) 10 log 1 12

f

sig

ffFkTL fP Q f f

Hajimiri, IEEE JSSC, Mar. 2000

Phase noise:

sigPFkT2

log10

Note: Leeson assumed that F(f) was constant over frequency.


Phase Noise of A Practical Oscillator

Phase noise drops at -20 dB/decade over a wide frequency range, butdeviates from this at: Low frequencies – slope increases (often -30 dB/decade) High frequencies – slope flattens out (oscillator tank does not filter all

noise sources) Frequency breakpoints and magnitude scaling are not readily predicted by

the analysis approach taken so far.

210 logsig

FkTP


Phase noise contributions from LC tank

2

2 2 2max

8( )

4p okT R f

L fV Q f

IT Vmax Phase noise L(f) where Vmax is below saturated voltage.

Discussion:Phase noise contributions from tail current

2

2 2 2max max

32( )

4T p p oI R kTR fL fV V Q f

= channel noise factor

If Vmax is constant (saturated), IT Phase noise L(f) .

Phase noise contributions from differential pair2

2 2 2max

32( )

4m p p og R kTR fL f

V Q f

If Vmax is constant, gm (or W/L) Phase noise L(f) .J. Rael and A. Abidi, IEEE CICC, 2000

Vout

Rp LCpCpRpL

VDD

IT


General Transceiver Block Diagram

LNA

BasebandI

BasebandQ

90o

BasebandQ

BasebandI

LO2FrequencySynthesizer

PA Buffer

LO1FrequencySynthesizer

RxRF

TxRF

1st IF

TxIF

2nd IFTo De-modulator

From Modulator


Classical PLL Block Diagram

The TCXO provides a reference frequency to the synthesizer circuit so that itmay accurately produce a wide range of signals that are stable and relativelylow in phase noise.

By changing the value N, the output frequency FVCO can be tuned across thefrequency band of interest. The only constraint to the frequency output of thesystem is that the minimum frequency resolution, or minimum channel spacing,is equal to FR. Channel spacing = FVCO / N = FR

TCXO

FX R

N

FR FVCO

PhaseDetector

LoopFilter VCO

FrequencyTuning

FVCO

N

TCXO: Temperature CompensatedCrystal Oscillator

VCO: Voltage Controlled Oscillator

In the locked state:FVCO = N FR, N FVCO / N = FX / R = FR


PLL Frequency Synthesizer Employing a Prescaler

TCXO

FX R

N

FR FVCO

PhaseDetector

LoopFilter VCO

FrequencyTuning

FVCO

NV

V

High-SpeedDivider

Low-SpeedDivider

Prescaler

In the locked state:FVCO = N V FR = N (VFR)

N, V Channel spacing = FVCO / N = VFR


PLL Frequency Synthesizer Employing a Dual-Modulus Prescaler


High-Speed Dual-Modulus Dividers

D

Q

Q

CLK

D

Q

Q

CLK

D

Q

Q

CLK

Q

Q

D

CLK

Q

Q

D

CLK

Q

Q

D

CLK

Q

Q

D

CLK

Q

Q

D

CLK

fin

Mode

foutMC

Divide-by-4/5 counterSW

ModeSW

0 0

0

1

1

1

0

1

fout

fin/128

fin/129

fin/64

fin/65

FF1 FF2 FF3

Q1

Q2 Q3

Divide-by-32 counter

High-speed


Divide-by-4/5 divider

fin

Q1

Q2

Q3

Q1

Q2

Q3

MC = 0

MC = 1

D

Q

Q

CLK

D

Q

Q

CLK

D

Q

Q

CLK

fin

MC

Divide-by-4/5 counter

FF1 FF2 FF3

Q1

Q2 Q3


Two Kinds of Divider Structure

Analog: Regenerative (Dynamic)

Regenerative Frequency Divider

Proposed by Miller, 1939

Digital: Flip-Flop Based (Static and Dynamic)

fi fofifo fo

fo

fo = fi/2

Mixer LPF AMP


Toggle Flip-Flop Based Frequency Divider

D Q

QLatch

D Q

QLatch

CKin

CKout

CKin

CKout


All Kinds of Latches can be used……


Dynamic TSPC CMOS DFFs

TSPC DFF proposed by Yuan and Svensson

An improved TSPC DFF

CK CK

CK

CK

D

Q

CK

CK

CK

CKD

Q

Q. Huang, IEEE JSSC, Mar. 1996


High-Speed Differential DFFs

ECL, CML, SCFL(SCL): Very High Speed Digital Circuits ECL: Emitter Coupled Logic CML: Current Mode Logic SCFL: Source Coupled FET Logic

All uses Current Switches Basic Structure of SCFL(SCL), ECL, CML


Advantages of SCFL(SCL), ECL, CML Low logic swing High Speed

Differential Structure High sensitivity, easy interface

Easy Combinational Logic embedded

Basic structure of a latch

D

Q

CK


An Conventional ECL Mater-Slave Delay Flip-Flop

Edge trigger DFF

D-latch without source followers

D Q

QD

D Q

QD

D Q

QD

Din Vout

CK

Din Vout

D

Q

CK

D

Q

CK


- Divide-by-2 circuit

CK

CKOUT


State-of-the-art Synchronous Pipeline Stage

The critical cycle time of the synchronous building block is composed of: the propagation delay of the combination logic block (tpdL) the set-up time (tsuS) and the propagation delay (tpdS) of the storage

element The maximum operating frequency

In order to increase the maximum operating frequency, two concerns wouldbe discussed. How to reduce the insertion delay of the storage element (tsuS + tpdS). How to reduce the delay of the logic block (tpdL).

)(1

pdSsuSpdLmax ttt

f


High-Speed Logic Flipflops (LFFs)

Divide-by-4/5 prescaler

NOR-FF

D Q

QD

D Q

QD

D Q

QD

NOR-FF NOR-FFDFF

CK MC

B

CK

Q

A VREF

frequency synthesizers -...

Documents