fpga compiler ii™ getting starteddift6221/getstart.pdf · 2001. 1. 16. · introduction to fpga...

FPGA Compiler II™Getting StartedVersion 2000.11-FC3.5, November 2000

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Contents

Preface

1. Introduction to FPGA Compiler II

What Is FPGA Compiler II? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Known Limitations and Workarounds . . . . . . . . . . . . . . . . . . . . . . . 1-5

2. Methodology and Basic Operations

Understanding Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Understanding Design Flow Options . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Push-Button Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Constraint-Driven Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Script-Based Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Launching the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . 2-8

Tip Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Output Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Mouse Buttons and Context Menus. . . . . . . . . . . . . . . . . . . . . . 2-9

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Running the FPGA Scripting Tool . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

How Do I…? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Learning More . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Vendor-Provided Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Compiler Reference Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

3. Tutorial

Creating Design Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Setting Up the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Creating the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Adding the Design Source Files to the Project . . . . . . . . . . . . . 3-4

Debugging the Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Elaborating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Identifying the Top-Level Design . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Specifying the Target Architecture . . . . . . . . . . . . . . . . . . . . . . . 3-11

Setting the Target Clock Frequency . . . . . . . . . . . . . . . . . . . . . . 3-12

Choosing Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Working With Design Constraints and Controls . . . . . . . . . . . . . . . 3-14

Entering Design Constraints, Attributes, and Controls. . . . . . . . 3-15

Editing Table Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

Optimizing the Design Implementation . . . . . . . . . . . . . . . . . . . . . . 3-17

Analyzing Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

Viewing Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

Viewing RTL Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

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Viewing Optimized Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

Viewing Timing Results Graphically Using TimeTracker . . . . . . 3-25

Generating Netlists, Reports, and Project Databases. . . . . . . . . . . 3-26

Generating Netlist Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

Generating a Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

Generating Project Databases. . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

Using the DesignWizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

4. Advanced Features

Using an ASIC-Compatible Design Flow. . . . . . . . . . . . . . . . . . . . . 4-2

Working With Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Exporting an ASCII Constraint File . . . . . . . . . . . . . . . . . . . . . . 4-3

Importing an ASCII Constraint File . . . . . . . . . . . . . . . . . . . . . . 4-5

Understanding the Format of the ASCII Constraint File. . . . . . . 4-7Header Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7Clock Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8Object Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8Path Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9Port Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11Module Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12Register Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13Vender Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Index

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Figures

Figure 1-1 FPGA Compiler II Design Flow Overview . . . . . . . . . . . 1-2

Figure 2-1 FPGA Compiler II in Your Design Environment . . . . . . . 2-3

Figure 3-1 The Project Window After Design Source Files Are Added. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 3-2 Text Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Figure 3-3 Identifying the Top-Level Design. . . . . . . . . . . . . . . . . . . 3-11

Figure 3-4 Create Implementation Dialog Box . . . . . . . . . . . . . . . . . 3-12

Figure 3-5 Creating the Design Implementation . . . . . . . . . . . . . . . 3-14

Figure 3-6 Constraint Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Figure 3-7 Optimization Results in the Clocks Constraint Table . . . 3-19

Figure 3-8 Optimization Results in the Paths Constraint Table . . . . 3-20

Figure 3-9 Optimization Results in the Ports Constraint Table. . . . . 3-20

Figure 3-10 Optimization Results in the Modules Constraint Table . . 3-21

Figure 3-11 Schematic Viewer—RTL View . . . . . . . . . . . . . . . . . . . . 3-22

Figure 3-12 Schematic Viewer—Optimized View. . . . . . . . . . . . . . . . 3-23

Figure 3-13 Export Netlist Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . 3-27

Figure 3-14 Generate Project Report Dialog Box . . . . . . . . . . . . . . . 3-29

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Figure 3-15 Export Netlist Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . 3-30

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Tables

Table 2-1 Mouse Behavior in FPGA Compiler II . . . . . . . . . . . . . . . 2-9

Table 2-2 Common Tasks in FPGA Compiler II . . . . . . . . . . . . . . . 2-10

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Preface FIX ME!

This Getting Started guide provides information for users of FPGA Compiler II. The guide explains how to apply the program’s basic features to your chosen design flow and FPGA architecture. For information about features not covered in this manual, see the online Help or man pages for individual commands.

This guide supports FPGA Compiler II version 3.5.

This preface includes the following sections:

• Audience

• Related Publications

• FPGA Compiler II Online Help

• FPGA Compiler II Man Pages

• SOLV-IT! Online Help

• Customer Support

• Conventions

xi

Audience

This guide is for logic designers or engineers who use the FPGA Compiler II synthesis tool to implement FPGA designs.

Related Publications

Related publications include

• FPGA Compiler II Installation Guide

• FPGA Compiler II / Express VHDL Reference Manual (online)

• FPGA Compiler II / Express Verilog HDL Reference Manual (online)

These documents are delivered with the program in portable document format (PDF) files.

In addition, the program’s Help menu also provides access to a selection of FPGA-vendor documents provided by FPGA vendors.

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FPGA Compiler II Online Help

FPGA Compiler II includes these forms of online Help:

• Topic-based

• Context-sensitive

To access the topic-based online Help system, choose Help Topics from the Help menu. You can then access specific Help topics through the table of contents, the alphabetic index, or the text-search feature. The Help system also includes a glossary of FPGA Compiler II terminology.

When working in FPGA Compiler II, you can display a context-sensitive description of a specific feature. Click the question mark button on the product’s toolbar, or press Shift-F1 and then click an object on the screen.

FPGA Compiler II Man Pages

The FPGA Compiler II man pages contain the most up-to-date command usage and syntax information. To access the man pages, enter man, followed by the command of interest, in the FPGA Compiler II shell (fc2_shell). For example,

fc2_shell> man script_chip

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SOLV-IT! Online Help

SOLV-IT! is the Synopsys electronic knowledge base. SOLV-IT! contains information about Synopsys and its tools and is updated daily.

To obtain more information about SOLV-IT!,

1. Go to http://solvnet.synopsys.com.

2. If prompted, enter your user name and password. If you do not have a SOLV-IT! user name and password, you can obtain them at http://www.synopsys.com/registration.

Customer Support

If you have problems, questions, or suggestions, contact the Synopsys Technical Support Center in one of the following ways:

• Open a call to your local support center from the Web:Go to http://solvnet.synopsys.com (SOLV-IT! user name and password required). Then click “Enter a Call.”

• Send an e-mail message [email protected]

• Telephone your local support center.

- Call (800) 245-8005 from within the continental United States.

- Call (650) 584-4200 from Canada.

- Find other local support center telephone numbers at http://www.synopsys.com/support/support_ctr.

xiv

For more information about FPGA Compiler II, see the Synopsys Web page at http://www.synopsys.com/products/fpga.

xv

Conventions

The following conventions are used in Synopsys documentation.

Convention Description

Courier Indicates command syntax.

In command syntax and examples, shows system prompts, text from files, error messages, and reports printed by the system.

italic Indicates a user specification, such as object_name

bold In interactive dialogs, indicates user input (text you type).

[ ] Denotes optional parameters, such as pin1 [pin2 ... pinN]

| Indicates a choice among alternatives, such as low | medium | high(This example indicates that you can enter one of three possible values for an option: low, medium, or high.)

_ Connects terms that are read as a single term by the system, such as set_annotated_delay

Control-c Indicates a keyboard combination, such as holding down the Control key and pressing c.

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

Edit > Copy Indicates a path to a menu command, such as opening the Edit menu and choosing Copy.

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1Introduction to FPGA Compiler II 1

FPGA Compiler II, your Synopsys FPGA logic-synthesis solution, brings a powerful combination of Synopsys logic-synthesis and optimization technology, high-level design methodology, and an easy-to-use user interface to the FPGA design desktop.

This chapter includes the following sections:

• What Is FPGA Compiler II?

• Features and Benefits

• Known Limitations and Workarounds

1-1

Introduction to FPGA Compiler II

What Is FPGA Compiler II?

FPGA Compiler II is a powerful synthesis tool for leading FPGA architectures. With the tool, you can create optimized netlists from VHDL code, Verilog HDL code, and existing, unoptimized EDIF or Xilinx Netlist Format (XNF) netlists.

Figure 1-1 summarizes the way that FPGA Compiler II fits in your design flow.

Figure 1-1 FPGA Compiler II Design Flow Overview

In this flow, use FPGA Compiler II to follow this general procedure:

1. Use a text editor to enter VHDL or Verilog HDL source code for your design.

Verilog or VHDL

Optimized FPGA netlists

Design

FPGA place and route

1. Enter HDL design source code.2. Set up project and analyze source code.3. Elaborate for target architecture.4. Optimize and generate netlists5. Analyze timing.

constraints

Functional simulation netlists(VHDL, Verilog)(EDIF, XNF)

FPGACompiler II

scripts dc_shell

Project database

HDL EDIF or XNF netlists

1-2


2. Set up your project, add the design source files to it, and analyze the HDL design source files for correct syntax.

3. Elaborate logic from HDL, and netlist source files, targeting a specific architecture and device.

4. Optimize logic for speed or area as directed by your design constraints, generating an netlist file that is ready for place and route by FPGA vendor tools.

5. Analyze timing. Extract and display accurate post-synthesis delay information for timing analysis and debugging.

Features and Benefits

FPGA Compiler II is a superset of the next-generation FPGA Express synthesis technology. It also includes enhancements and features that especially benefit high-density FPGA design flows:

• Architecture-specific mapping and optimization for all leading programmable logic vendors

• Industry-leading quality of results (QOR)

• Support for industry standard HDL

• Easy-to-use design flows and graphical user interfaces

• Integrated static timing analysis with TimeTracker

• Schematic viewing with tight links to TimeTracker

• Scripting support based on Tool command language (Tcl)

• Block-level incremental synthesis for Xilinx Virtex devices.

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• Support for register retiming and pipelining to balance delays between input-to-register, register-to-register, and register-to-output

• Design Compiler shell (dc_shell) scripting support for migration between ASICs and FPGAs

• Support for instantiated DesignWare Foundation components

• Ability to export Synopsys database format (.db) files, so that projects created in FPGA Compiler II can be integrated into your design flow with other Synopsys tools

Users of the original FPGA Compiler software should install the new FPGA Compiler II to take advantage of the latest FPGA technology. All in-maintenance FPGA Compiler customers have been automatically upgraded to FPGA Compiler II.

FPGA Compiler II, version 2000.11-FPGA3.5 includes many new features. For more information about new features, see the Release Notes. For instructions on how to view the Release Notes, see “Known Limitations and Workarounds” on page 1-5.

If you are migrating from a schematic-based to an HDL-based design methodology, FPGA Compiler II adds HDL logic synthesis and optimization to your current FPGA design environment. You can completely define a design with HDL source code, or use a mixture of schematics and HDL source code to enter a design into FPGA Compiler II.

1-4


Using an HDL-based design methodology increases productivity because HDL source code is vendor-independent, retargetable, and reusable. The built-in optimization algorithms, which are specifically tuned for each FPGA vendor’s device family, provide the smallest, fastest designs in the shortest time.

The FPGA Compiler II Windows-compliant GUI uses standard commands and procedures to accept all your input values; no command scripts are required.

FPGA Compiler II accommodates a variety of design styles and performance goals with multiple synthesis design flows. Your FPGA design can be either complex or simple. It can push the limits of minimum area or maximum speed, or it can be driven by a minimum design cycle.

Known Limitations and Workarounds

Information about known problems, limitations, and workarounds is available in the FPGA Compiler II Release Note, available from the Help menu in the GUI.

To view the Release Notes,

• Choose Help > Release Notes.

The Release Notes are also available in SOLV-IT! at the Synopsys website.

1-5


To use SOLV-IT! to see the release notes,

1. Go to the Synopsys Web page at http://www.synopsys.com and click SolvNET.

2. If prompted, enter your user name and password. If you do not have a SOLV-IT! user name and password, you can obtain them at http://www.synopsys.com/registration.

3. Click Release Notes, then open the FPGA Compiler II Release Note.

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2Methodology and Basic Operations 2

This chapter introduces you to many of the basics of running FPGA Compiler II. It includes the following sections:

• Understanding Methodology

• Understanding Design Flow Options

• Launching the Graphical User Interface

• Running the FPGA Scripting Tool

• How Do I…?

• Learning More

For information on features not listed here, see the online Help and man pages.

2-1

Methodology and Basic Operations

Understanding Methodology

Your particular design methodology determines the details of how you use FPGA Compiler II in your design flow. However, you can use the general methodology outlined here to understand how FPGA Compiler II best fits into your design flow.

Design creation and validation occurs before you use FPGA Compiler II. You can use the following design creation methodologies:

• For an HDL-based design methodology, write the HDL source code for the design.

• For a schematic-based methodology, capture the design schematics and export in an HDL format, netlist format, or a combination.

• For a mixed (HDL and schematic) design methodology, write the HDL source code for the parts of the design you decide to describe in HDL. Capture the schematics for the rest of the design.

If you choose to verify the design functionality, use an HDL simulator for HDL code; for schematics, use a gate-level simulator.

2-2


Figure 2-1 shows the flow of FPGA Compiler II with other tools in these design environments. The steps in this procedure are similar for each environment; only the method of entering the design into FPGA Compiler II differs. Note that simulation is optional.

Figure 2-1 FPGA Compiler II in Your Design Environment

HDL and schematic

design Schematic

design HDL

design

Functionalsimulation

FPGA Compiler II

Synthesis

Timinganalysis

Designconstraints

Optimization


Timingsimulation

ProgramFPGA device

Place androute


EDIF, XNF netlistsVHDL, Verilog netlists

RTL (VHDL, Verilog) EDIF, XNF

Integration withother Synopsys

tools

.db file

Key:- - - Optional

2-3


To use FPGA Compiler II in your design environment,

1. Create design source files.

2. Launch FPGA Compiler II.

3. Set up the design project and analyze the design source files.

This step creates an FPGA Compiler II project. The project is a working directory that holds internal and intermediate files. See “Setting Up the Project” on page 3-2.

4. Elaborate the designs.

In this step you identify the top-level design, select the target device, set the clock frequency, optionally enter design constraints, and create the implementation. See “Elaborating the Design” on page 3-10.

The tool elaborates each subdesign module, creating and linking the design hierarchy.The resulting implementation is a generic gate-level representation of your design.

After the elaboration, the tool generates a schematic that represents the hierarchy of your design.

5. Optimize the design implementation.

During optimization, the tool uses architecture-specific algorithms to analyze the timing of your design, compare timing to your requirements, and make changes to meet your design goals. See “Optimizing the Design Implementation” on page 3-17.

The tool can also generate reports and an optimized schematic of your design.

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6. (Optional) Analyze timing information to verify circuit performance.

The tool displays timing information in tables beside your design constraints and highlights timing violations. This information is linked directly to the schematic for easy debugging. See “Analyzing Timing” on page 3-18.

7. Export an optimized EDIF or XNF netlist for place and route.

The tool can generates an optimized netlist ready for place and route by FPGA vendor tools.See “Generating Netlist Files” on page 3-26.

8. (Optional) Generate VHDL or Verilog netlists for functional simulation.

Using a standard HDL simulator, you can verify that the optimized netlist is functionally identical to the RTL input. See “Generating Netlist Files” on page 3-26.

9. (Optional) Export the .db file for integration with other Synopsys tools.

To finish the design process, complete the following steps outside of FPGA Compiler II:

1. Place and route the design with the FPGA vendor’s development system.

2. (Optional) Simulate the design with post–place and route timing delays.

3. Program the FPGA device.

2-5


Understanding Design Flow Options

FPGA Compiler II supports a variety of design flows:

• Push button

• Constraint driven

• Script based

Choose the flow that meets your design’s requirements.

Push-Button Design Flow

Use a push-button flow when quick results are more important than detailed design goals. Push-button flow skips the step of setting or adjusting design constraints.

In only two steps you can go from an HDL description or schematic netlist to an optimized netlist ready for place and route. The steps are simple: First, add your design’s source files to the FPGA Compiler II project. Then select the target device (vendor, family, package, and speed grade).

To use the push-button flow, select the Skip constraint entry option in the Create Implementation dialog box (this is the default setting). FPGA Compiler II elaborates and optimizes your design in one step.

Constraint-Driven Design Flow

Use a constraint-driven flow when QOR is most important or when you want to refine your design goals.

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With FPGA Compiler II you can specify design requirements and constraints to tailor the results to your design goals.

To use a constraint-driven flow, deselect the Skip Constraint Entry option in the Create Implementation dialog box. FPGA Compiler II creates just the elaborated implementation, thus allowing you to specify constraints before you optimize the implementation.

Script-Based Design Flow

You can access all of the functionality of FPGA Compiler II via the FPGA scripting tool and the FPGA Compiler II Tcl-based command-line language. You can use the scripting tool to synthesize any designs, either in batch mode or interactively, from the shell command line.

Use a script-based flow if

• You prefer command-line or keyboard-based interfaces to graphical interfaces.

• You understand the capabilities of the tool fully and want to specify operations as quickly as possible.

For example, an action that requires multiple mouse clicks and keyboard entries using the graphical interface could be entered as a single command.

For details on running the scripting tool, see See “Running the FPGA Scripting Tool” on page 2-9.”

2-7


Launching the Graphical User Interface

You can launch FPGA Compiler II on Windows, Solaris, and HP-UX.

• Windows

From the Start menu, choose Programs > Synopsys > FPGA Compiler II.

• Solaris and HP-UX

Ensure that bin/fc2 is in your path. Then type fc2 to start the program.

Tip Bar

The tip bar provides information at each stage of the design flow. It automatically detects the state of the design, identifies the next logical step in the design flow, and provides a brief explanation of the function and purpose of that step.

Output Window

The Output window displays errors, warnings, and other messages about your actions as you use FPGA Compiler II.

2-8


Mouse Buttons and Context Menus

Table 2-1 provides information to help you use FPGA Compiler II more efficiently.

Running the FPGA Scripting Tool

The FPGA scripting tool is a Tcl-based command-line interface to all of the synthesis and optimization features of FPGA Compiler II.

You can run scripts from the command line of the FPGA Compiler II shell, or execute batch files of script commands.

Table 2-1 Mouse Behavior in FPGA Compiler II

Action Result

Left-click Selects and deselects.

Left-double-click In the Design Sources and Chips windows, expands or contracts the hierarchy of the project, library, or design source file.

On an error in the Output window, starts the text editor and opens the design source file to the selected error.

Right-click Displays a context menu of actions for

• The design source file in the Design Sources window and the editor

• Unoptimized or optimized implementations in the Chips window

• The messages in the Output window• Subpaths in the Paths constraint table

2-9


To run the scripting tool,

1. Start the shell either by choosing Start > Programs > Synopsys > FPGA Compiler II Shell in Windows or by typing fc2_shell in a UNIX shell or command window.

2. In the fc2_shell, execute script commands. All of the commands are documented in the man pages.

- To obtain a list of all available commands, at the fc2_shell prompt enter

help

- To access FPGA Compiler IIman pages, enter

man commandname

- To display Help about the man pages, enter

man help

How Do I…?

Table 2-2 lists common tasks and how to accomplish them.

Table 2-2 Common Tasks in FPGA Compiler II

If you want to . . . Do this . . .

Expand or contract a project, library, or file tree

Double-click the icon.

Add to a library Click the Add Sources button on the toolbar, or choose Synthesis > Add Source Files.

View extended Help about an error or warning

In the Output window, double-click the error number.

Use the Help Index to locate the error number.

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Learning More

In addition to the sources mentioned in “Preface,” you can learn more about FPGA Compiler II by consulting these sources:

• Vendor-provided documents

• Compiler reference manuals

Modify a design source file by using the editor

In the Design Sources window, right-click the file icon and choose Edit File.

In the Output window, double-click the error text.

Enter constraints for an implementation

Right-click the implementation and choose Edit Constraints. Click the cell to edit.

Specify timing constraints on arbitrary timing paths

In the Paths constraint table, right-click a timing group and choose New Subpath.

Copy data within a row or column

Copy the selection with Edit > Copy, and paste it into the destination cell with Edit > Paste.

Select the cell containing the data you want to copy and the cells to which the data should be copied. Press Control-d, or choose Edit > Fill down.

Run timing analysis on an implementation

Right-click the optimized implementation and choose View Results.

Run the program from the command line

Start the scripting shell.

Run batch files of script commands

Start the scripting shell and execute your batch files.

Table 2-2 Common Tasks in FPGA Compiler II (continued)

If you want to . . . Do this . . .

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Vendor-Provided Documents

A selection of documents provided by FPGA vendors is available from the Help menu. You might find these documents helpful in answering your vendor-specific questions.

Compiler Reference Manuals

Online compiler reference manuals for VHDL and Verilog HDL contain recommended coding styles and their application to FPGA Compiler II synthesis and optimization.

You can find all compiler reference manuals on the FPGA Compiler II CD-ROM or by clicking the Help menu.

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3Tutorial 3

One of the fastest ways to learn to use FPGA Compiler II is to complete this tutorial, which follows the program design flow.

The tutorial includes the following sections:

• Creating Design Source Files

• Setting Up the Project

• Elaborating the Design

• Working With Design Constraints and Controls

• Optimizing the Design Implementation

• Analyzing Timing

• Viewing Schematics

• Generating Netlists, Reports, and Project Databases

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• Using the DesignWizard

• Summary

Creating Design Source Files

The first step in the design flow is to create HDL source files. You can use any text editor to enter VHDL and Verilog HDL source code for your design. FPGA Compiler II source files can be any combination of VHDL, Verilog HDL, EDIF, or XNF netlist files.

This step is usually performed outside of FPGA Compiler II. However, you can use the integrated HDL Editor (described in the section “Debugging the Source Files” on page 3-8) to edit a design source file once it has been read into a project.

Setting Up the Project

An FPGA Compiler II project is a working directory that holds a project file and subdirectories for internal and intermediate files. The key components of a project are the source files that describe the FPGA design or designs. The types of source files FPGA Compiler II supports are VHDL, Verilog HDL, EDIF, and XNF netlists. Netlist files usually originate from schematic capture systems or preoptimized macro libraries.

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To set up a project in FPGA Compiler II, follow these procedures:

1. Create the project.

2. Add the design source files to the project.

3. Debug the source files.

The following sections describe these procedures.

Creating the Project

After you create the design source files, start the design flow by creating a project. To create a project, FPGA Compiler II creates a new folder (directory) in which to store the project information.

To create a new project in FPGA Compiler II,

1. Launch FPGA Compiler II as described on page 2-8. This step opens the main window, which includes the toolbar, tip bar, Design Sources window, Chips window, and Output window.

2. Click Cancel in the DesignWizard window.

Use the DesignWizard later, after running the tutorial. For information, see “Using the DesignWizard” on page 3-31.

3. When you start FPGA Compiler II, you can either open an existing project or create a new one. For now, create a new project by clicking the New Project button on the toolbar or by choosing New Project from the File menu.

In the main window, FPGA Compiler II displays the Create New Project dialog box.

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The dialog box includes a default location and name for the project. You can change the location, name, or both. Use the drop-down list in the Save In field to navigate your directory tree, or click the Create New Folder icon to create a new directory.

4. Type tutor in the Name field. The tutor directory is where project files will be stored.

5. Click the Create button to create the new project.

After the program creates the tutor project, the Add Sources dialog box opens.

Adding the Design Source Files to the Project

After you create the project, you add the design source files to it. When you add these files to a project, FPGA Compiler II automatically analyzes them for errors.

Whenever you create a project, a default library named WORK automatically appears in the project folder. You add the source files to the library. FPGA Compiler II source files can be any combination of VHDL, Verilog HDL, or EDIF netlist files.

VHDL environments sometimes require multiple libraries. You can add a library at any time by right-clicking in the Design Sources window and choosing New Library. Then add design source files to that library in the same way as you do for WORK.

When you add the design source files to the project, FPGA Compiler II automatically analyzes them, using the Synopsys industry-standard HDL language support, which includes the ability to recognize instantiated DesignWare Foundation components.

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When you add VHDL source files to a project, the order you use can be important. For example, if a package defined in file1 uses another package defined in file2, add file2 before adding file1. This order of addition causes the tool to analyze file2 before file1.

If the source files contain errors, the Output window helps you find and correct problems. You can use the integrated text editor on the design source files to facilitate easy debugging.

To understand the problems, read the topic-based Help system’s explanations of the messages.

Note: FPGA Compiler II does not copy design source files. When you add these files, the program analyzes them in their current location. If you changed the files (a ? icon beside a file name indicates a change), you must click the Update button on the toolbar so that FPGA Compiler II reanalyzes the files. Alternatively, you can right-click in the Design Sources window and choose Update File.

To add source files,

1. Be sure the Add Sources dialog box is open.

If it is not open, you can access it by clicking on the toolbar, by choosing Synthesis > Add Source Files, or by right-clicking WORK in the Design Sources window and choosing Add Sources in WORK.

2. Select source files in the Add Sources dialog box.

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For this tutorial, use the tutor design files written in VHDL (tutor.vhd, counter.vhd) or Verilog (tutor.v, counter.v). These files are located in the installation_directory/samples/tutorial/vhdl or verilog directories.

3. After you select your design source files, click Open.

Note:

On a PC, you can also drag source files into the Design Sources window to add them to the project.

After you select your design source files, FPGA Compiler II displays the project window and extends the menu bar. The project window has two subwindows—the Design Sources window and the Chips window (see Figure 3-1).

- The Design Sources window displays the name, location, and status of each of the design source files.

- The Chips window displays information for individual design implementations, such as name and device type.

Note that the project window’s title bar displays the name of the project.

FPGA Compiler II automatically analyzes each source file as it is added in the Design Sources window. The icon to the left of each file name indicates the results of the analysis, as illustrated in Figure 3-1.

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Figure 3-1 The Project Window After Design Source Files Are Added

In this tutorial, the counter file has at least one error (indicated by the red cross) that must be corrected. The green check marks next to the other files indicate that the files have no errors or warnings.

The error in the problem source file is reflected up the hierarchy. Therefore the library and the project icons are also marked with a red cross. (For a list and explanation of analysis status icons, see the topic-based online Help.)

The Output window at the bottom of the screen displays error messages about the selected source file.

To display this menu, right-clicka source file name.

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Debugging the Source Files

Use the Errors, Warnings, and Messages tabs of the Output window to help find and correct errors and warnings in source files. The Output window shows the file name, line number, and type of each error or warning. After viewing the messages, you can use the built-in text editor to investigate and fix the source files.

To view and correct errors and warnings,

1. Select the design counter in the Design Sources window and view the errors in the Output window. Read the error and warning messages.

2. Correct any errors in the design source file. There are two ways to open the text editor window directly to an error in a design source file:

- At the location of the first error, open the source file for editing by right-clicking in the Design Sources window and choosing Edit File.

- At the location of a specific error, open the source file for editing by double-clicking the text for that error in the Output window.

If you selected the internal source editor as the default source file editor (by choosing Synthesis > Options > General screen), FPGA Compiler II uses the built-in text editor to edit the selected file. You can use the Edit menu to navigate in the text file. You can also use the text editor menu that is displayed when you right-click in the text editor window.

If you did not select the internal source editor, choosing Edit File starts the editor associated with the file’s type and opens the file.

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Figure 3-2 shows the text editor window and its menu of commands.

Figure 3-2 Text Editor Window

3. The text editor indicates that the errors in the design counter are caused by a typing error in the if statement. Change the text from fi to if in the counter file.

4. Save the file. The tutor.vhd icon contains a question mark, indicating that the file is out-of-date.

5. Update the file: Either go to the Design Sources window and click

on the toolbar, or right-click in the text editor window and choose Analyze File before closing the text editor window.

Depending on the extent of your modifications, you update the file, the library, or the project. FPGA Compiler II reanalyzes only the files you modify.

To display this menu, right-clickin the HDL Editor window.

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If your changes are not evident to FPGA Compiler II (for example, if the changes are in a dependent file), right-click in the Design Sources window and choose Force Update File (Library or Project).

After adding, analyzing, and debugging source files, you are ready to elaborate the design.

Elaborating the Design

Elaboration creates a unique, unoptimized implementation from your design source files. FPGA Compiler II translates the text-based description of the design (from the HDL) to a logical gate-level description that uses technology-independent primitives.

To elaborate the design,

1. Identify the top-level design.

2. Specify the target architecture.

3. Set the target clock frequency.

4. Choose synthesis options.

Identifying the Top-Level Design

To begin building a design implementation from analyzed source files, you identify the top-level entity (VHDL), module (Verilog), or schematic netlist. FPGA Compiler II uses this information to start building design hierarchy and interconnections.

For this example, choose tutor as the top-level entity. You can identify the top-level design in any of these ways:

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• Click the drop-down list of top-level designs on the toolbar to see a list of all entities, modules, and netlist designs in the source files. Scroll through the list to find and choose the top-level design. (See Figure 3-3.)

Figure 3-3 Identifying the Top-Level Design

• Alternatively, in the Design Sources window (shown Figure 3-1) you can double-click the source file you want to use as the top level. This step expands the file and displays an icon for the top-level design. Right-click the icon and choose Create Implementation.

• As a third alternative, when the icon of the top-level design is

selected, you can click the Create Implementation button on the toolbar.

Specifying the Target Architecture

After selecting a top-level design, specify a target architecture in the Create Implementation dialog box (see Figure 3-4).

To specify a target architecture,

1. Enter an implementation name. If you do not enter a name, FPGA Compiler II automatically creates a unique implementation name based on the name of the top-level design.

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2. Specify the target device and speed grade for the design.

For this tutorial, the design is small enough to fit into any device supported by FPGA Compiler II.

Figure 3-4 Create Implementation Dialog Box

Setting the Target Clock Frequency

Set the target clock frequency for the design in the Create Implementation dialog box. This target frequency is used as the default value for all clocks in the design. After you elaborate the design, you can change target clock frequencies in the design constraint tables.

For this tutorial, enter a target clock frequency of 25 MHz.

Note: Overconstraining a design can adversely affect the place and route results. Therefore, specify only what is really required.

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Choosing Synthesis Options

After you set the target architecture and clock frequency, FPGA Compiler II is ready to create a design implementation.

To create the implementation, the program elaborates logic for each source file. It determines the complete hierarchical structure and topology of the design, including multiple-level links and references between subdesigns. With this information, FPGA Compiler II produces an intermediate, unoptimized design implementation.

To choose synthesis options,

1. In the Create Implementation dialog box, verify the target architecture, clock frequency, and implementation name.

2. (Optional) Select options in this dialog box, including:

- Optimizing for speed or area with high, fast, or low CPU effort.

- Preserving or eliminating hierarchy in the design.

- Inserting I/O pads, if appropriate.

- Skipping constraint entry at this time (see the topic “Push-Button Design Flow” in the topic-based Help). For this tutorial, do not select Skip constraint entry.

3. Click OK.

When FPGA Compiler II finishes elaboration, an implementation icon, implementation name, target device, and speed grade appear in the Chips window. The icon indicates the implementation’s status (see Figure 3-5).

4. Check the Output window to investigate errors and warnings.

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Figure 3-5 Creating the Design Implementation

Working With Design Constraints and Controls

Before you start to optimize a design for a target device, you can set performance constraints, attributes, and optimization controls. Design constraints guide FPGA Compiler II with specific optimization requirements.

Using the graphical user interface, you can enter constraints for your design in editable tables. The constraints contain performance requirements and optimization options for architecture-specific optimization engines.

To display this menu, right-clickan implementation icon.

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Constraint information can be exported to ASCII files for easy editing. For more information, see “Working With Constraint Files” on page 4-3.

FPGA Compiler II separates constraint entries into logically related groups (for example, clocks, paths, ports, and modules). The tool automatically extracts design-specific information, such as clock names, port names, and design hierarchy, from the design and displays it in tables. You enter performance constraints, attributes, and optimization options directly into the tables.

Each set of constraint tables and dialog boxes is specific to a particular target FPGA architecture.

Specifying constraints is optional, but highly recommended. Entering your requirements in the constraint tables can significantly improve place and route results.

For example, if you enter constraints for an output port with restrictive speed requirements, it is easier for the place and route tool to fulfill those requirements. If a design is very large and has many hierarchical levels, you can improve place and route results by entering hierarchy constraints. Note, however, that overconstraining a design can adversely affect place and route results. Therefore, specify only what is really required.

Entering Design Constraints, Attributes, and Controls

To enter design constraints, attributes, and controls,

1. Right-click the elaborated implementation and choose Edit Constraints to open the Constraints window.

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Figure 3-6 shows how the constraints and synthesis controls (Altera options) are logically grouped by function into separate Clocks, Paths, Ports, and Modules tabs. An additional tab, called Registers, is available for selected FPGA technologies.

Figure 3-6 Constraint Tables

2. Click the tabs to display tables for the constraint groups.

Use the topic-based online Help if you need instructions and information about specific constraints, attributes, and optimization options.

3. Explore the tables for the tutor implementation.

The contents of the tables reflect the architecture you chose earlier. Note that the Clocks and Paths constraint tables are preloaded with the clock frequency (and corresponding period) that you entered for the target clock frequency.

4. After entering any constraints, attributes, and option information, close the Constraint window. This action automatically saves any changes you’ve made in the tables.

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Editing Table Cells

To edit table cells,

1. Click in the table cell.

A down arrow appears.

2. Click the down arrow.

A menu or editable field appears.

3. Choose a menu item or enter text as appropriate.

Optimizing the Design Implementation

After entering constraint, attribute, and option information, you are ready to optimize the design implementation.

In this step, you optimize the design implementation elaborated earlier, guided by the constraints and controls you entered in the constraint tables.

To optimize an elaborated implementation,

1. Click the elaborated implementation in the Chips window to select it. Its name is displayed on the top-level design field of the toolbar.

2. Right-click the implementation and choose Optimize Chip, or click

on the toolbar.

A new optimized implementation icon appears beneath the original implementation.

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When you optimize a design implementation, FPGA Compiler II analyzes the actual timing of your design against your requirements. After optimization, the design implementation tables display the constraints you specified with your design results so that you can compare them.

Analyzing Timing

After you create an elaborated implementation, you can determine circuit performance by checking the results of optimization and analyzing timing information. The post-synthesis timing data is displayed in the same formats as the tables you used to enter constraints.

To view the results of optimization,

1. Right click an optimized implementation and select View Results.

2. Check the Clocks constraint table to see the maximum clock frequencies that FPGA Compiler II estimated for each of the clocks in the design. Clock frequency violations appear in red. Figure 3-7 shows the Clocks constraint table after optimization.

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Figure 3-7 Optimization Results in the Clocks Constraint Table

3. Check the Paths constraint table for more information about timing violations:

- Select a path group to see a list of paths in that group.

- Select a path from the list to see the details of path composition, cumulative delays, and fanout.

- See the topic-based online Help for a description of timing analysis in FPGA Compiler II.

Figure 3-8 shows the Paths constraint table after optimization.

Note:

All pins of primitive cells on the timing path are displayed. Therefore two rows on the right pane correspond to a single cell (source and load).

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Figure 3-8 Optimization Results in the Paths Constraint Table

4. Check the Ports constraint table for information about input and output delays.

Figure 3-9 shows the Ports constraint table. The results include the slack for input arrival time and output delay for each port.

Figure 3-9 Optimization Results in the Ports Constraint Table

5. Check the Modules constraint table for information about the device resources used. Double-click the items in the Area column for details about cell count.

Figure 3-10 shows the Modules constraint table after optimization.

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Figure 3-10 Optimization Results in the Modules Constraint Table

Viewing Schematics

You can view and analyze your design graphically by using the integrated schematic viewer and the TimeTracker feature. You can view an RTL view of the design, as shown in Figure 3-11, or an optimized (mapped) view of the design, as shown in Figure 3-12.

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Figure 3-11 Schematic Viewer—RTL View

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Figure 3-12 Schematic Viewer—Optimized View

Viewing RTL Designs

To view an RTL design,

1. In the Chips window, right-click the elaborated implementation called tutor.

2. From the pop-up menu, choose View Schematic. The windows auto-arrange to maximize the viewable area.

3. Maximize the main window in the screen area.

4. Navigate around the schematic by clicking the Zoom In, Zoom Out, Zoom In Tool, and Zoom Full-Fit buttons on the toolbar.

5. To view an area, click the Zoom In Tool button on the toolbar and drag the pointer over the area of interest.

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6. View the contents of the my_counter(counter) block by double-clicking the block.

7. Return to the next level up by right-double-clicking anywhere in the schematic.

8. Navigate around the hierarchy by using the Chips window:

- Double-click a level of hierarchy to expand it.

- Select one of the blocks to view that level.

Note that all cells are generic—not mapped to a particular technology at this stage. All hierarchy is preserved because operators have not been implemented at this stage.

9. When you are comfortable with the navigation features, close the RTL view.

Viewing Optimized Designs

To view an optimized design,

1. In the Chips window, right-click the optimized implementation called tutor-Optimized.

2. From the pop-up menu, choose View Schematic.

The windows auto-arrange, displaying the project window on the left, and the TimeTracker and schematic windows on the right.

3. Navigate around the schematic by clicking the Zoom In, Zoom Out, Zoom In Tool, and Zoom Full-Fit buttons on the toolbar.

4. To view an area, click the Zoom In Tool button on the toolbar, and drag the pointer over the area of interest.

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Viewing Timing Results Graphically Using TimeTracker

To view timing results in the schematic viewer,

1. Click the Paths tab to view the Paths constraint table.

2. Select the RC–CLK RC–CLK row in the path groups pane (the upper-left pane).

The paths constrained by this path group are now displayed in the paths area (the bottom-left pane).

For any paths that fail timing, the timing values are displayed in red in the TimeTracker window, and in the schematic the paths are highlighted.

3. Select the first path from this group of paths.

The right side of the TimeTracker window displays the cells contained in this path. The instance name, cell type, delay, and fanout are shown for each cell.

In the schematic window, the critical path is highlighted in red, allowing you to see the path graphically.

4. Select a path and pause the pointer over each cell of the path in turn.

A pop-up window displays the cell name, cell type, pin numbers, delay, fanout, and slack values.

5. Select a pin from the pin list.

Note that the cell to which the pin is attached is highlighted in yellow in the schematic window.

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6. Move along the path by clicking the Previous Pin and Next Pin buttons on the toolbar, or by clicking each pin in the path in TimeTracker.

7. With a cell selected and highlighted in yellow, click the Fan In and Fan Out buttons on the toolbar to display the fanin and fanout logic cones.

Generating Netlists, Reports, and Project Databases

When the design implementation is optimized, you can generate two kinds of netlist files:

• EDIF or XNF files formatted for place and route by FPGA vendor tools

• VHDL or Verilog files for functional simulation

You can generate a report file to review and document the project.

You can also export the project database in .db format to enable integration with other Synopsys tools.

Generating Netlist Files

FPGA Compiler II generates EDIF or XNF netlists that place and route tools from FPGA vendors can process directly. FPGA Compiler II can also generate VHDL and Verilog netlists for simulation.

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To generate netlist files,

1. Either select the optimized implementation and click on the toolbar, or right-click the implementation and choose Export Netlist. The Export Netlist dialog box appears (see Figure 3-13).

Figure 3-13 Export Netlist Dialog Box

2. Choose an export directory for the netlist files.

3. To change directories, either type the new directory name or click Browse.

4. Specify whether to export timing constraints with the netlist, using the Export Timing Specifications check box.

5. Select an output format for your netlist:

- Select NONE in the Output Format list box to export only the netlist for place and route.

- Select Verilog or VHDL to also export a netlist for simulation.

6. Click OK.

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Caution!

To avoid overwriting your source files, always export netlists into a separate directory to be sure that they are manageable. Many files might be exported from a single design.

Generating a Report

You can generate the following reports:

• Library report

A library report shows errors, warnings, and messages for each design source file in the library.

• File report

A file report shows errors, warnings, and messages for the selected design source file.

• Chip report

A chip reports shows implementation settings such as target device, synthesis goal, optimization effort, clock frequency, and other timing information.

• Project report

Project reports contains all the information in the library, file, and chip reports.

To generate a report,

1. Select the project, library, file, or chip in the project window and

click on the toolbar.

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Alternatively, right-click the project, library, file, or chip and choose Report from the pop-up menu.

2. In the dialog box that appears (see Figure 3-14), specify the name and location for the report.

Figure 3-14 Generate Project Report Dialog Box

3. Click Save. FPGA Compiler II creates a text file containing summary information for the whole project, the library, the design file, or the chip.

4. Open the report file in a text editor or word processor.

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Generating Project Databases

FPGA Compiler II generates project databases in .db format. The .db format enables integration with other Synopsys tools.

To generate project database files,

1. Either select the optimized design implementation and click on the toolbar, or right-click the implementation and choose Export Netlist. The Export Netlist dialog box appears (see Figure 3-15).

Figure 3-15 Export Netlist Dialog Box

2. Specify whether to export the Synopsys design database with the netlist, using the Generate Synopsys db Files check box.

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Using the DesignWizard

After completing the tutorial and becoming familiar with FPGA Compiler II concepts, you can use the DesignWizard to create future projects. The DesignWizard leads you from creating a project to optimizing your chip in as few as two steps.

There are two ways to access DesignWizard:

• When you first start the tool, the DesignWizard starts automatically.

• You can start the DesignWizard manually by choosing DesignWizard from the File menu.

The first DesignWizard screen (FPGA Project dialog box) allows you to

• Create a new project or open an existing one.

• Disable the DesignWizard for subsequent starts of the tool.

The default directory in which the DesignWizard stores the tool outputs is at the same hierarchical level as the file for your top-level design. The default base name of the default directory is identical to that of the top-level design.

The DesignWizard follows this flow:

1. Add design source files and specify the top-level design.

2. Set synthesis parameters.

- Select target technology

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- (Optional) Set optimization parameters such as Clock frequency, CPU effort, and whether to preserve or eliminate hierarchy.

- (Optional) Change one or more of the following: project name, location in which the DesignWizard stores tool outputs, and various netlist settings.

3. Click Run (Finish).

The DesignWizard stores the tool outputs in a default directory. The default directory is at the same hierarchical level as the file for your top-level design. The default base name of the default directory is identical to that of the top-level design.

At the end of the DesignWizard flow, all results are reflected in the FPGA Compiler II GUI, and you can work on them as usual there. For a more detailed design flow, including setting optimization constraints, see “Performance (Constraint-Driven) Design Flow” in the online Help.

Summary

You have now completed the FPGA Compiler II design flow tutorial. You have learned how to perform these tasks:

1. Creating design source files

2. Setting up an FPGA Compiler II project, and adding, analyzing, and debugging source files

3. Creating a design implementation, specifying the top-level design and target device, and elaborating the design

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4. Entering performance constraints and controls to guide the optimization process

5. Optimizing the design

6. Analyzing timing

7. Viewing schematics

8. Generating netlists, reports, and project databases

Now you are ready to use FPGA Compiler II for your own designs.

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4Advanced Features 4

This chapter includes the following sections:

• Using an ASIC-Compatible Design Flow

• Working With Constraint Files

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Advanced Features

Using an ASIC-Compatible Design Flow

With FPGA Compiler II, you can easily migrate between ASIC and FPGA. For example, you can

1. Synthesize the same design in Design Compiler and FPGA Compiler II.

Both Design Compiler and FPGA Compiler II support the same set of industry standard Verilog and VHDL. Any design that can be optimized by Design Compiler can be optimized by FPGA Compiler II.

2. Translate dc_shell scripts to fc2_shell scripts.

FPGA Compiler II has a built-in command-line translator that translates dc_shell scripts to fc2_shell scripts.

3. Export FPGA Compiler II projects in Synopsys standard .db format.

After you synthesize your design you can export the project in .db format for use with other Synopsys tools such as PrimeTime and Formality.

For detailed information, refer to the online application note “ASIC to FPGA Migration Using FPGA Compiler II”. To view application notes, choose Help > Help Topics.

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Working With Constraint Files

FPGA Compiler II can export and import files of constraint information in ASCII format.

When you export a constraint file, you create a file that contains the constraint settings of the current chip. You can edit the ASCII constraint file and reapply the new constraint information to the current chip. When you import a constraint file, the tool sets the constraints on the current chip.

This method of exporting, editing, and importing the constraint file is useful for designers who use a scripting methodology. However, GUI users can find this method of editing constraints useful as well—for example, in order to avoid keyboard and mouse tasks required by data entry in the GUI constraint tables.

Exporting or importing a constraint file always acts on the current chip. Set the current chip with the current_chip command before exporting or importing a constraint file.

Note: To support current methodologies that require doing so, you can continue to import constraint files in binary format. Exporting binary constraint files is no longer supported.

Exporting an ASCII Constraint File

You can export an ASCII file of constraint commands for the current implementation by using menu commands or the command line (scripting tool).

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Advanced Features

To use GUI commands to export an ASCII constraint file,

1. Right-click the elaborated implementation in the Chips window.

2. Choose Edit Constraints from the pop-up menu.

Steps 1 and 2 set the current implementation and enable the menu items in step 3.

3. Choose File > Export Constraints.

The Export Constraint File dialog box opens.

4. Enter the file name you want and click Save.

When saving the file, the tool appends the .scf ending for an ASCII constraint file.

To use the shell to export an ASCII file of constraint commands for the current implementation,

1. Run the scripting tool.

See “Running the FPGA Scripting Tool” on page 2-9 for instructions.

2. Set the current chip. At the shell prompt, enter

current_chip my_chip

3. At the shell prompt, enter

export_constraint -ascii file_name

where file_name is the output file name you choose. When saving the file, the tool appends the .scf ending for a constraint file in ASCII format.

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Advanced Features

See the man page for export_constraint for complete information about syntax and function.

Importing an ASCII Constraint File

You can import an ASCII file of constraint commands for the current chip by using menu commands or the scripting tool.

To use GUI commands to import an ASCII constraint file for application to the current implementation,

1. Right-click the elaborated implementation in the Chips window.

2. Choose Edit Constraints from the pop-up menu.

Steps 1 and 2 set the current chip and enable the menu items in step 3.

3. Choose File > Import Constraints.

The Import Constraints File dialog box opens.

4. Enter the file name and click OK.

To use the shell to import an ASCII file of constraint commands for the current implementation,

1. Run the scripting tool.

See “Running the FPGA Scripting Tool” on page 2-9 for instructions.

2. Set the current implementation. At the shell prompt, enter

current_chip my_chip

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Advanced Features

3. At the shell prompt, enter

import_constraint -ascii -f file_name

where file_name is the name of the file of constraint commands to apply to the current implementation.

See the man page for import_constraint for complete information about syntax and function.

When importing a constraint file, the tool skips any lines that contain errors and issues an error message. For debugging the constraint file, a line number appears with each error message. Lines with errors are not processed.

Messages are issued at the command line for the following problems:

• The constraint is unknown (misspelled, for example).

• The constraint is not supported for the object. For example, the architecture does not support the constraint, or the constraint name is misspelled.

• The target object cannot be found. For example, the object name is misspelled.

• The constraint is outside the valid range.

• The object is invalid for the constraint. For example, the object and constraint both exist, but are inappropriate for each other.

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Advanced Features

Understanding the Format of the ASCII Constraint File

In the ASCII constraint file you can find

• Header information that identifies the chip name and target architecture

• Constraint information and commands in sections that correspond to the tabs in the constraint tables.

• Comments that show valid constraint settings and other information

The ASCII constraint file contains constraint information, comments, and defaults for

• Clocks

• Object groups (as commented information in the export file)

• Paths

• Ports

• Modules

• Registers

• Vendor options

Comments in the file begin with a hash mark (#).

Header Information

Header information consists of the chip name and the architecture. The header appears at the beginning of the file. Header information is optional when you are importing an ASCII constraint file.

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Advanced Features

Examplechip_name = tutor;arch_name = APEX20K;

Clock Constraints

The clock constraints portion of the file contains default information and user settings. The first line defines the default clock period, rise time, and fall time. Subsequent lines contain the clock names followed by the clock period, rise time, and fall time for each clock. If the clock uses a default value, -1 appears.

Example######## Clock Constraints ########

clock <default> 20/0/10clock data_clk1 -1/-1/-1clock clk2 -1/-1/-1

Object Groups

Logically related groups of design objects appear as comments in the ASCII constraint file. In the following example, (I) is the group of input objects, (O) is the group of output objects, and (RC, data_clk1) is the group of objects triggered by the rising clock edge of data_clk1.

Example# Members of Group (I):# /d/vcc# /d/data_clk1# /d/clk2# /d/clrn# /d/ena1

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Advanced Features

# /d/ena2# /d/data[3]# /d/data[2]# /d/data[1]# /d/data[0]

# Members of Group (O):# /d/regout# /d/vcc# /d/data[3]# /d/data[2]# /d/data[1]# /d/data[0]# /d/done

# Members of Group (RC,data_clk1):# /d/u1/q_reg

Path Constraints

The path constraints section sets the required delay between objects or object groups.

In the following example, the first line defines required timing in nanoseconds between all inputs (I) and outputs (O). The second line defines required timing in nanoseconds between all inputs and objects triggered by the rising edge of the data_clk1 clock.

Example######## Path Constraints ########

path -from (I) -to (O) -delay 33path -from (I) -to (RC,data_clk1) -delay 34

To define subpaths, you define a name for the subpath and the explicit sources and destinations of the subpath.

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Advanced Features

In the following example, the first path command defines a subpath called my_from:my_to between five input objects and one output object.

In the second path command, the subpath is called m_f:m_t. The subpath starts at input /d/ena2 and terminates at output /d/regout.

For clarity, the export file prints the -from objects, -to objects, and -delay value on separate lines.

Examplepath my_from:my_to

-from(I:

/d/data_clk1, /d/clk2, /d/clrn, /d/ena1, /d/ena2)

-to (O:

/d/regout) -delay 43;

path m_f:m_t -from (I:

/d/ena2) -to (O:

/d/regout) -delay 53;

Note: Be sure that the path you define exists. The tool does not validate the path you define.

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Advanced Features

Port Constraints

The port constraints section of the constraint file contains user-defined defaults and port constraints.

Example######## Default Port Constraints ########

port <default> use_io_reg "OFF";# Valid ’use_io_reg’ values are:# <default># ON# OFF

port <default> slew_rate "FAST";# Valid ’slew_rate’ values are:# <default># SLOW# FAST

Example######## Port Constraints ########

# Port clk2, direction = input

port clk2 input_delay 34/(RC,data_clk1);

# Port clrn, direction = input

port clrn input_delay 34/(RC,data_clk1);port clrn location "data location";

# Port done, direction = output

port done output_delay 20/(RC,data_clk1);

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Advanced Features

Module Constraints

The module constraints section of the constraint file contains user-defined defaults and module constraints.

Example########## Default module constraints ###########

module <default> hierarchy "preserve"# Valid module ’heirarchy’ values are:# inherit# preserve# eliminate

module <default> primitive "preserve";# Valid module ’primitive’ values are:# inherit# preserve# optimize

Example######## Module Constraints #######

# module test - Root design

module d hierarchy "inherit";module d primitive "inherit";module d dont_touch "false";module d optimize_for "inherit";module d effort "inherit";module d dup_reg_merge "<default>";

# module dflipflop - u1

module /d/u1 hierarchy "inherit";module /d/u1 primitive "inherit";module /d/u1 dont_touch "inherit";

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Advanced Features

module /d/u1 optimize_for "inherit";module /d/u1 effort "inherit";module /d/u1 dup_reg_merge "<default>";

Register Constraints

The register constraints section displays information from the Registers constraint table. The estimated fanout for registers is shown in comment lines.

Example

# Register Constraints :#------------------------ register <default> max_fanout 3;

register sdatc_reg<11> max_fanout 5;# register sdatc_reg<11> estimated fanout = 1# register sdatb_reg<4> estimated fanout = 1

Vender Options

The vender options section contains options specific to the target architectures available in FPGA Compiler II.

Examplelucent_option ignore_unlinked_cells "disable";xilinx_option ignore_unlinked_cells "enable";xilinx_option buffer_internal_nets "enable";actel_option max_fanout 16;actel_option advanced_optimization "disable";

general_option use_lpm "enable";

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Advanced Features

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Advanced Features

Index

Aadding files

design source files 3-4ASIC-compatible design flow 4-2

Bback-annotation 2-5benefits 1-3

Cchip, current, setting 4-4Chips window 3-6, 3-23, 3-24clock frequency, setting 3-12clocks constraint table 3-18command-line interface, running 2-9compiler reference manuals 2-12constraint file

ASCII, exporting 4-4ASCII, importing 4-5error checking 4-6subpath caution note 4-10subpaths 4-9working with 4-3

constraint tables 3-18editing cells in 3-17how to open 3-15

constraint-driven design flow 2-6constraints

comparing to actual results 3-18entering 3-14

context-sensitive Help xiiicreating a new project 3-3creating source files 3-2current chip, setting 4-4

Ddatabases, project 3-30.db files 3-30dc_shell scripting 1-4debugging source files 3-8delay extraction 1-3, 3-18design constraints

comparing to actual results 3-18entering 3-14

design flow 1-2, 2-2, 2-6, 3-1(see also tutorial)ASIC-compatible 4-2constraint-driven 2-6debugging source files 3-8

IN-1

DesignWizard 3-31HDL-based 2-2push-button 2-6script-based 2-7summary of steps 3-32synthesizing a design 3-10

design implementation 3-13design methodology (see design flow)design source files

adding libraries of 3-4adding to project 3-5updating from project 3-9

design sources window 3-6DesignWizard, using 3-31documentation see help

EEDIF 3-2editing table cells 3-17elaboration 1-3, 3-10error checking

constraint file, when importing 4-6errors and warnings 3-8

Fformats, supported 3-2FPGA Compiler II, definition 1-2FPGA scripting tool (FST) (see scripts)FST, scripting tool 2-9

Ggenerating

netlists 3-26project databases 3-30reports 3-28

HHDL design methodology, migrating to 1-4HDL editor see text editorhelp

compiler reference manuals 2-12context-sensitive xiiiman pages xiiiOutput window 2-8Synopsys Technical Support Center xivtip bar 2-8topic-based xiiivendor-provided documents see online Help

Iimplementation

current chip, setting the 4-4design, creating 3-13

Kknown problems 1-5

Llaunching the program 2-8libraries of design source files 3-4

Mman pages xiiimethodology, using DesignWizard 3-31migration, between ASIC and FPGA 4-2modules constraint table 3-20mouse behavior 2-9

Nnetlist formats supported 3-2netlists, generating 3-26

IN-2

Ooptimization

how to accomplish 3-17place in overall flow 1-3viewing results 3-18

Output windowdescription 2-8figure of 3-7information in 3-8

PPaths constraint table 3-19, 3-25place and route 2-5Ports constraint table 3-20project database 3-30project window 3-6project, setting up 3-2push-button design flow 2-6

Rrelated publications xiiRelease Note, viewing 1-5reports, generating 3-28running scripts 2-9

Sschematic viewer 1-3, 3-21script-based design flow 2-7scripts 1-3, 2-7

dc_shell 1-4running scripting tool 2-9shell, running 2-9

setting up a project 3-3shell, running 2-9simulation 2-2, 2-5, 3-26, 3-27

source filesdebugging 3-8types 1-3

subpathcautionary note 4-10specifying in constraint file 4-9

Support Center, Synopsys Technical xivsupported formats 3-2

Ttable cells, editing 3-17target architecture, specifying 3-11target clock frequency, specifying 3-12task summary 2-10text editor 3-8, 3-9TimeTracker 3-25timing analysis 1-3, 3-18tip bar 2-8topic-based Help xiiitop-level design

identifying 3-10tutorial 3-1

creating a new project 3-3creating source files 3-2debugging source files 3-8generating netlists 3-26generating project databases 3-30generating reports 3-28identifying top-level design 3-10setting clock frequency 3-12setting up a project 3-3summary 3-32synthesizing a design 3-10top-level design, identifying 3-10viewing errors and warnings 3-8viewing results of optimization 3-18

Uupdating source files 3-9

IN-3

Vvendor-provided documents see online Helpviewing errors and warnings 3-8viewing results of optimization 3-18viewing schematics 3-21

mapped 3-24

optimized 3-24RTL or generic 3-23

viewing timing results 3-25

XXNF 3-2

IN-4