fpga-based system design: chapter 7 copyright 2004 prentice hall ptr topics n bus interfaces. n...

FPGA-Based System Design: Chapter 7 Copyright 2004 Prentice Hall PTR

Topics

Bus interfaces. Platform FPGAs.


Bus interfaces

Requirements:– High performance.– Variable signal environment.

Techniques:– Asynchronous logic.– Handshaking-oriented protocols.


Timing diagrams

a

b

c

stable

0 1

changing

Timing constraint


Asynchronous logic

Distribute timing information with values.– No global clock.

Clock signal paths must have the same delay as data values.


Latching an asynchronous signal

D Qadrs

adrs_ready

adrs


Asynchronous timing constraints

Must satisfy setup, hold times.

adrs

Setup timeHold time


Bus system design

Requirements:– Imposed by the other side of the system.

Constraints:– Imposed by this side of the system.

a b

requirements

constraints


ba

Views of the bus

Hardware:

D Q D Q

Combinationallogic


Views of bus system, cont’d.

Timing diagram:

ba

D Q D Q

Combinationallogic

x

y

x y


Bus protocols

Basic transaction:– four-cycle handshake.

a

b


Handshake machine

Each side is an FSM (possibly asynchronous):

a b0 1

Go

ackack

enq

0 1

enq

ack


Basic protocols

Handshake transmits data:


Box 1 logic


Box 2 logic


Bus timing

td1 = d stable

td2 = d not stable

tc1 = c rises

tc2 = c falls

tack1 = ack rises

t1 = tc1 - td1 >= tr

t2 = tack1 - tc1 >= th

t3 = tc2 - tack1 >= th


Busses and systems

Microprocessor systems often have several busses running at different rates:

CPU

bridge

mem

I/O

High-speed

Low-speed


Basic signals in a bus


Bus characteristics

Physical– Connector size, etc.

Electrical– Voltages, currents, timing.

Protocol– Sequence of events.


Advanced transactions

Multi-cycle transfers:– Several values on one handshake.– May use implicit addressing.


PCI bus

Used for box-level system interconnect. Two versions:

– 33 MHz.– 66 MHz.

Supports advanced transactions.


PCI bus read


Multi-rate systems

Logic blocks running at different clock rates may communicate:– Multi-chip.– Single-chip.

» Slow bus connects to fast logic.

Logic 1 Logic 2

100 MHz 33 MHz


Metastability

Registers capturing transitioning signals may take an arbitrarily long time to settle.


Resynchronization

Use cascaded registers to minimize the chance of using a metastable value.

D Q D Qd dout


Platform FPGAs

Put all the logic for a system on one FPGA. Requires large FPGAs plus:

– Specialized logic:» I/O support;

» memory interface.

– CPUs.


Example: Virtex II Pro

Major features:– Large FPGA fabric.– High-speed I/O.– PowerPC.


Virtex II Pro High-speed I/O

Rocket I/O:– parallel/serial or serial/parallel transceiver.

Clock recovery circuitry. Transceivers for multiple standards: Gigabit

Ethernet, Fibre Channel, etc. Programmable decoding features. Interface to FPGA fabric.


Virtex II Pro CPUs

Up to 4 PowerPC 405s per chip:– 5 stage pipe, static branch prediction, etc.

Separate instruction, data caches. MMU. Timers. Scan-based debug support.


PowerPC CoreConnect


Altera Stratix

Combines FPGA fabric, memory blocks, multipliers.


Stratix DSP block

fpga-based system design: chapter 7 copyright 2004 prentice hall ptr topics n bus interfaces. n...

Documents

fpgabased system design

prentice hall ptr box

prentice hall ptr busses

prentice hall ptr pci

bus slide

t h slide

prentice hall ptr ba

n constraints