FPGA Based Digital Logic Emulator for Educational Purposes

Vladimir Kasik 1, Ibrahim Salem Jahan 2, Ales Kurecka 3

1,3 VSB – Technical University of Ostrava, FEECS, DMC, 17. listopadu 15,

708 33 Ostrava-Poruba, Czech Republic 2 Higher Institute of Medical Technology, Department of Maintenance of Medical Instruments Misurata,

Libya

Abstract. Great development of digital technology requires effective practical approach to teaching this technique. For the implementation of practical problems can be advantageous to use a programmable logic device, especially a Field Programmable Logic Device - FPGA . In one such circuit is easy to demonstrate and to practice basic and advanced systems from the gate across the state machines and memory to several processors and complette computing systems. This papers deals with a digital design and realisation of the Digital Logic Emulator with FPGA Development Board.

Keywords: FPGA, Logic Emulator, VGA, Finite State Machine

1. Introduction

Digital Logic Emulator should be able to implement the above basic combinational and sequential logic functions. The basic combinational logic functions are represented with logic gates as logical AND, NAND, OR, NOR, XNOR and negation. The enhanced features include the combination circuit as a decoder, encoder, multiplexer, adder / subtracter, comparator and multiplier. The basic sequential circuits are D-type flip-flops or J-K, T or R-S type flip-flops. The extended sequential functions include counters, shift and data registers, frequency dividers and more. The number of implemented logic functions is restricted only by the size of the FPGA.

Fig. 1: Block Structure of the Digital Logic Emulator with FPGA.

2011 International Conference on Software and Computer Applications IPCSIT vol.9 (2011) © (2011) IACSIT Press, Singapore

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In the case of used parts are implemented also more complex circuits such as synchronous or asynchronous memory, stop-watch or traffic lights.

2. Structure of the Digital Logic Emulator

To realize the logic functions and many others have been proposed structure of the system as in Fig. 1. It contains several functions (from function 1 to n in Fig. 1). These functions are designed in VHDL code and they are implemented concurrently inside FPGA chip. Choosing between functions is implemented using multiplexer function, which is controlled by the user button B3. The value of the set logic function is indicated on the seven-segment LED display. The seven-segment LED driver as well as several sequential logic functions is clocked by an external 50MHz clock signal generator.

The used Xilinx Spartan3 Development Kit contains following controls used for logic emulator functions: 4 buttons, 8 switches, 8 LEDs and four-digits seven-segment LED display. Currently, the emulator is implemented with 35 logic functions that can be extended and modified at any time. Some examples of implemented circuits are shown in the following figures.

Fig. 2: Example of the Sequential Logic Circuit – Loadable Synchronous Circuit.

Many options are there for memory emulation. Emulator can emulate both synchronous and

asynchronous memory, single-port to three-ports type. In the case of emulation of two-port memories one port is used for user control and the second port is used to periodically read the memory contents and display it as a picture through the VGA connector (Fig. 3).

Fig. 3: RAM memory Output on VGA Display

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As an example of a complex sequential function algorithm was implemented traffic lights (Fig. 3), which is described as FSM - Finite State Machine. Light outputs are realized with LEDs and also as the picture on the VGA connector.

Fig. 4: FSM of Traffic Lights Control

The traffic lights for cars has 3 possible values (uppercase): red R, green G, yellow Y, the walker has 2 possible values (lowercase): red r, and green g. There are input signal A (walker push button) to controller that has 2 possible value, 1 (pressed), and 0 (not-pressed). The state machine of traffic lights for this case is shown in Fig. 4, that consists of six states (G r, Y r, R r, R g, R r, R Y r). The first state G r repeats to itself, when the signal A = 0, and the state machine will go to next stage Y r, when signal A = 1 (when, the “walk-

request” push button is pressed), after that the state machine continue to next time-flip.

a) b)

Fig. 5: Traffic lights function: a) output on VGA Monitor, b) FSM States

Among the specific features typical of FPGAs include accumulator (Fig. 6), which is the basis of a DSP - Digital Signal Processing. It is essential that this circuit is again implemented as a hardware function.

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Fig. 6: Digital Accumulator Function

3. Design Verification

All the functions of the digital emulator has been successfully tested in real hardware. As an example the binary counter circuit has been chosen for demonstrative verification. The results are shown in following figures.

Fig. 7: Timing Diagram of Binary Counter Circuit

Fig. 8: Testing of Binary Counter Circuit on the Spartan-3 Starter Kit

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4. Conclusion

This work has shown advantages of using programmable logic FPGA in the design of various logic functions. These circuits, which are nowadays commonly used in many areas can be easily programmed using a language such as VHDL. Such use of a suitable FPGA design entry and facilitates the design allows for easy expansion and changes in the circuit. This work also demonstrates the benefits of a single FPGA against using a plenty of logic ICs, more external cables, PCB size, time-consuming, the possibility of errors, etc. 5. Acknowledgements

The work and the contribution were supported by the project: Ministry of Education of the Czech Republic under Project 1M0567 “Centre of applied cybernetics”, student grant agency SV 4501141 “Biomedical engineering systems VII” and TACR TA01010632 “SCADA system for control and measurement of process in real time”. Also supported by project MSM6198910027 Consuming Computer Simulation and Optimization.

6. References

[1] Xilinx, Inc: Spartan-3 Starter Kit [online]. [cit. 2011-04-06]. URL: < http://www.xilinx.com/products/devkits/HW- SPAR3-SK-UNI-G.htm>.

[2] O. Krejcar. Problem Solving of Low Data Throughput on Mobile Devices by Artefacts Prebuffering, In EURASIP Journal on Wireless Communications and Networking, Article ID 802523, 8 pages. Hindawi publishing corp., New York, USA, DOI 10.1155/2009/802523 (2009)

[3] M. Augustynek,, M. Penhaker, D. Korpas. Controlling Peacemakers by Accelerometers. In 2010 The 2nd International Conference on Telecom Technology and Applications, ICTTA 2010. March 19-21, 2010, Bali Island, Indonesia, Volume2 NJ. IEEE Conference Publishing Services, 2010, p. 161–163. ISBN 978-0-7695-3982-9, DOI:10.1109/ICCEA.2010.288 (2010)

[4] M. Stankus, M. Penhaker, J. Kijonka, P. Grygarek. Design and Application of Mobile Embedded Systems for Home Care Applications In Proceedings of 2010 Second International Conference on Computer Engineering and Application,s ICCEA 2010, 19. – 21. March 2010, Bali Island, Indonesia, Volume 1NJ. IEEE Conference Publishing Services, 2010 p. 412-416. ISBN 978-0-7695-3982-9, DOI: 10.1109/ICCEA.2010.86 (2010)

[5] M. Penhaker, M. Rosulek, M. Cerny, L. Martinák. Design and Implementation of Textile Sensors for Biotelemetry Applications. In Abstracts of the 14th Nordic – Baltic Conference on Biomedical Engineering and Medical Physics IFBME, 16.-20.6.2008 Riga, Latvia. Riga: Riga Technical University, 2008. s.54. ISBN 978-9984-32-231-5. (2008)

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