fpga based 32 bit risc processor design
DESCRIPTION
fpga based 32 bit risc processor reportTRANSCRIPT
Seminar Report on
FPGA Based Implementation of 32-Bit RISC
Processor
Presented By
Nilesh Kulkarni
Suraj Wagaskar
Achit Yadav
Guided By
Prof.N.B.Hulle
Assistant Professor, GHRIET
Department of Electronics Engineering
G.H.Raisoni Institute of Engineering & Technology, Pune
G.H.Raisoni Institute of Engineering & Technology,
Pune – 412207
(Affiliated to University of Pune)
Department of Electronics Engineering
This is to certify that the seminar project report entitled “FPGA Based
implementation of 32-bit RISC processor” being submitted by
Mr. Nilesh Kulkarni
Mr. Suraj Wagaskar
Mr. Achit Yadav
in the partial fulfillment for the award of the degree of Bachelor of
Engineering in ELECTRONICS to the G.H.Raisoni Institute of Engineering &
Technology, Pune is a record of Bonafied work Carried out by him under my
guidance and supervision.
This results embodied in this project have not been submitted to any other
University or institute for the award of any degree or Diploma for the academic
year 2012-2013.
Prof.N.B.Hulle Prof.A.D.Bhoi
(Project Guide) (Head, Electronics Engg)
CONTENTS
Chapter.1 Acknowledgements
Chapter.2 Abstract
Chapter.3 Introduction
Chapter.4 Block Diagram of the RISC Processor
Chapter.6 Explanation & Description
Chapter.7 Design Methodology
Chapter.8 FPGA Architecture
Chapter.9 FPGA Implementation Advantages
Chapter.10 References
Acknowledgements
I take my opportunity to complete the thesis of this project and have
allowed me to extend my knowledge and skills. I would like to thank everyone
who has been involved with allowing this to happen, and who assisted me during
the course of
My work. In particular:
Prof.N.B.Hulle, Assistant Professor, Electronics Engineering Department,
G.H.Raisoni Institute of Engineering & Technology, Pune.
Abstract
History has marked a large number of man endeavors towards
building machines that are capable of performing arithmetic operations more
efficiently than he can do himself. These started with very primitive instruments
but evolved over the course of time due to the accumulative knowledge of
mankind. In the recent decades, many computer architectures exhibiting various
design methodologies and computation models have been developed. One of the
most widely accepted of which is von-Neumann architecture.
This thesis introduces Micro6, A microprocessor that adopts von-
Neumann architecture and will be implemented on FPGA. In addition to that, the
thesis presents a software development environment for Micro6.
In this way we are designing a 32 bit RISC Processor core and
implementing in hardware on Xilinx Spartan 3E FPGA. The design has been
achieving using VHDL (Very High Speed Integrated Circuits Hardware
Description Language).
Introduction
As the high capacity ,low –cost FPGA devices train continues its
revolutionary journey through the electronics design Landscape, an ever-increasing
number of design landscape, an ever-increasing number of designers are jumping
on board trading their traditional hardware-based systems for the attractive ness of
the FPGA‟s „soft‟ programmability.
Creation of soft processor based systems, destined to run within a
chosen Target FPGA device, becomes second nature –utilizing one of the many
supported flavors of 32 –bit RISC processor, wired up to access peripheral I/O and
memory over a standard bus interface.‟ Soft processors are processors that are
defined as part of the FPGA design that is programmed into the physical FPGA
device, rather than physical, discrete devices connected to the FPGA, or processors
that are immersed as part of the physical FPGA‟s makeup. Such processors are
typically 32-bit and have simple, RISC architectures.
Embedded software refers to the code the software smarts – that
gets downloaded to the physical FPGA device and which will run on a soft
processor defined within the FPGA design. The beauty of using soft processors in
FPGA designs are that you are not locked to a physical device. We can change
processor or modify the code running on it simply by reprogramming the physical
FPGA device with a modified hardware design or updated embedded
code – leading to true field upgradeable hard ware and software‟.
Block Diagram of the RISC Processor
Architecture
RP is a 32-bit processor which contains a data memory, a program
memory, an ALU, registers, and a controller, as shown in Figure 1. Its features
include a Harvard architecture which permits simultaneous data and program
memory accesses in each instruction cycle, a large register address space which
allows fast register-to-register access for more operands, & special purpose
registers which enhance array data transfer both to and from the data memory. The
RP also provides a simple hardware mechanism for automatic loopback at the end
of an inner loop based on loop length and loop count. The register space (RS) of
RP contains 256 32-bit registers, divided into two blocks of 128 registers each.
The first block, called data registers, consists of vector access
registers (VARs), accumulators, and registers for temporary operand storage. The
second RS block, called the interface registers, consists of less frequently used
control and I/O registers. The memory space (MS) of RP contains internal and
external memory. Internal memory includes program memory and data memory. In
our model, external memory is restricted to data RAM, though it can be extended
to include program memory as well. The internal data memory and the external
data memory share the same address space, and they are accessed via the same
address and data buses.
The ALU performs arithmetic, logic, and bit-manipulation
operations. It is supplied with two operands from RS and, depending on the
instruction, the operands are directed to the adder-shifter or multiply-accumulate
unit. The result of the operation is returned to RS .The controller generates signals
to initiate transfer of data via the buses, control the operation of ALU, and store
data into registers or memories, according to the instruction currently stored in the
instruction register (IR) as well as the status word.
The I/O features of RP include a serial receiver/transmitter port
(SRT interface), and an 8-bit parallel port (host interface).
The host interface consists of a 32-word 8-bit circular buffer. The
circular buffer can be simultaneously accessed by RP and the host device.
Typically, while one
Device is writing to the circular buffer the other could be reading from it. The
SRT interface consists of a controller, a transmitter and a receiver. The transmitter
and the receiver both contain a 16-bit buffer. The transmitter can be transmitting
data to the peripheral device while the receiver is receiving data.
In addition, clock divider and timer units are provided. The clock
divider generates pulses by dividing the frequency of the original RP clock
according to a user-specified parameter. The timer counts clock pulses and sends
an interrupt signal to the controller when a pre-specified number is reached
Design Methodology
Design Methodology:
I. Modeling at Specification Level:
The basic idea of our modeling technique is to iteratively refine a
high-level design description down to the layout level by systematically
developing a hierarchy of VHDL models. The modeling hierarchy is illustrated in
figure.
Initially, the system specification is captured in a high-level
description called the specification level model". The designer then refines this
model by adding architectural details until the design consists of functional blocks
and interconnections. The resulting model is called the functional level model".
Functional blocks can be further refined to produce a register-transfer level (RTL)
model, from which the layout may be synthesized .
The specification level model (SLM) is a coarse-grain model of
the system. At this stage of the design process, the modeler may have very little
information about architectural details such as the number and width of internal
buses, the number of ports on the memory, the number of pipeline stages etc. Since
these details are unavailable, it is not possible to Incorporate timing (such as
functional unit delays, propagation delays on buses, memory access times etc.) in
the model. It should be noted that the SLM may be rewritten several times if
simulation reveals improper functionality. However, modeling time for SLM is
typically a small percentage of the entire design cycle.
The SLM test environment must be developed together with test
vectors to provide a mechanism for simulating and monitoring the unit under
design. The same test vectors can be used to verify models at successive levels of
refinement in the design process.
In the RP example, the initial specification consists of the instruction set and a set
of protocols that define communication between the processor and its peripherals:
host processor, external memory, and the serial receiver and transmitter.
II. Modeling at Functional Level:
In a functional level model (FLM), the design is modeled as a set
of functional blocks, such as ALU, register files, or memory, that communicate via
signals and buses. The main purpose of FLM is to verify timing and balance delay
paths in the design. This cannot be done effectively with the SLM, which models
the design as an abstract process with no architectural details. It is to be noted that
a detailed timing description, including propagation delays for functional units and
setup and hold time for storage elements, can be incorporated into FLM.
III. Refined Specification Model:
In order to increase the data transfer rate we decided to use
hardware interfaces for
the communication. The RP controls the interfaces by issuing instructions to set,
reset or monitor interface signals. Thus the instruction set must be modified. Some
instructions used to control or monitor the communication signals between the RP
and the peripherals are removed, and instructions used to control the interfaces are
added. The communication protocols are also changed.
IV. Modeling in VHDL:
In this section, we discuss the basic modeling strategy for
specification level and functional level models in VHDL. VHDL was selected as
our modeling language because it allows simulation over many different levels of
abstraction and is widely accepted as a standard for modeling hardware. In all our
models, we follow the VHDL modeling conventions listed below.
1. High-level behaviors are modeled as processes or sets of communicating
processes.
2. All the registers or buffers are modeled as variables within processes.
3. Processes communicate with each other using global signals.
4. Separate processes must be used to model different concurrent behaviors.
FPGA Architecture & Philosophy
FPGA (Field Programmable Gate Array) is an integrated circuit
containing gate matrix which can be programmed by the user “in the field” without
using expensive equipment. An FPGA contains a set of programmable logic
gates and rich interconnect resources, making it possible to implement complex
digital circuits. FPGA devices are produced by a number of semiconductor
companies: Xilinx, Altera, Actel, Lattice, Quick Logic and Atmel.
FPGA‘s are generally classified as following:
a) SRAM based FPGA.
b) SRAM based FPGA with Internal flash memory.
c) Anti-fuse based FPGA.
Modern SRAM-based FPGAs have highest densities, but consume a lot of
power and need an external non-volatile memory to store configuration bit
stream. SRAM-based FPGAs with an internal flash module doesn't need an
external configuration memory. Flash-based and Antifuse based FPGAs
consume much less power than their SRAM-based counterparts. Antifuse-based
FPGAs can only be programmed once.
BLOCK DIAGRAM OF FPGA
VHDL Terms:
Entity: The entity is the building blocks of the model design.
Architecture: All entities after the simulation and compilation consist of
architectural description.
Configuration: By using the configuration statement, all components are tied to
entity architecture.
Package: It is a set of data types and subprograms that are commonly used in the
design.
Driver: It is the drive signal.
Bus: As the name indicates it brings all the bunch of signal together to
communicate inside the hardware.
Attributes: it is the data that are added to the VHDL objects.
Generic: It passes data to the entity.
Process: it is the fundamental unit of execution in VHDL.
Advantages of FPGA implementation
1) FPGA has very fast custom logic of design.
2) FPGA is faster than conventional microprocessor and controller.
3) FPGA has good reprogrammable capacity.
4) FPGA is more flexible than dedicated chipsets due to its general purpose
architecture.
5) FPGA shows high performance with low cost.
References
[1]Imyong lee, Dongwook Lee, Kiyoung choi “ODALRISC: A Small, Low power
and Configurable 32-bit RISC processor” International SOC design conference
2008.
[2]Michael Gschwind, Valentina Salapura, and Dietmar Maurer “FPGA
prototyping of a RISC Processor Core For Embedded Applications” IEEE
transaction on VLSI systems, vol 9, no.2, April 2001
[3]P.Athanas and H.Silverman. “Processor Reconfiguration Through Instruction-
set Metamorphosis”. IEEE Computer, 26(3):11-18, Mar. 1993..
[4] A. Abd-alla and D. Kartlgaard, “Heuristic Synthesis of Micro programmed
Computer Architectures,” IEEE Trans. on Computers Vol. 23, No. 8, Aug. 1974,
pp. 802-807.
[5] D. L. Perry, VHDL, McGraw-Hill, Inc., 1991.