fpga-accelerator attractor computation of scale free gene
TRANSCRIPT
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FPGA-accelerator Attractor Computation of Scale Free Gene Regulatory Networks
Ricardo Ferreira, Julio Vendramini
Departamento de Informática,
Universidade Federal de Viçosa, Brazil
FPL 201020th Field Programmable Logic Conference31 Aug 2 Sept – Milan, Italy
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Contents• Basic Concepts
– Gene Regulatory Networks and Scale Free Networks
• Problem– Attractor Computation
• Contributions– FPGA-accelerator– Architecture Node Framework– Dynamic Interconnections
• Results and Conclusions
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Gene Regulatory Networks
• Dynamic Model of System Behaviour• Applications
– Cell differentiation and Evolution– Drug design process
• Perturbations– Robust – Adaptable
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Gene Regulatory Networks
• Dynamic Model of System Behaviour• Applications
– Cell differentiation and Evolution– Drug design process
• Perturbations
–Robust – Adaptable
Cell A Cell A
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Gene Regulatory Networks
• Dynamic Model of System Behaviour• Applications
– Cell differentiation and Evolution– Drug design process
• Perturbations– Robust
–AdaptableCell A Cell A1
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Gene Regulatory Networks● Models
– Ordinary Differential Equations, Bayesian Networks, Petri Nets, .....
– Boolean Networks [Kauffman, 69], “The Origins of
Orders: Self Organization and Selection of Evolution” [Kauffman, 93]
Random Graph, where each Node: Gene (1 or 0) K neighbours; Random Boolean function
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Network TopologyRandom Scale Free Hierarchical
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Network TopologyRandom Scale Free Hierarchical
Internet, citations, social networks.....•Science [Barabásie e Albert, 1999]•Nature - [Watts e Strogatz, 1998]
Kauffman
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Scale FreeRandom Scale Free Hierarchical
Scale Free Gene regulatory networks•[Aldana, 2003], [Irons, 2006],[Iguchi,2007]
Yeast protein Interaction Network
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Network Attractors ● Network State = All node states● Network Dynamics
– State Evolution;– System converges to stable cycles, called
attractors
Network
Network state
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Network Attractors ● Network State = All node states● Network Dynamics
– State Evolution;– System converges to stable cycles, called
attractors
Network One Step on Time
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Network Attractors ● Network State = All node states● Network Dynamics
– State Evolution;– System converges to stable cycles, called
attractors
Network Attractor or cycle
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Attractors● Cycles - Biological
– Could be observed (experiments)– Cell type
●Example:
State Diagram of Network
network
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Attractor Complexity● Large State Space 2gene
– 2100 ~ 10 27 states...– NP-Hard
●Example:
State Diagram of Network
network
gene
3 genes → 8 states
State transition =All nodes and edgesMust be visited
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Attractor Computation
●Synchronous model●Two Simulation instances: S
0 and S
1
Network State diagram
One stepTwoSteps
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Attractor Computation
●Synchronous model●Two Simulation instances: S
0 and S
1
Network State diagram
One stepTwoSteps
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Sequential Algorithm
● For each step– Visit all nodes and all edges O( N + E )
Network State diagram
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Sequential Algorithm
● Several steps to find an attractor....
Network State diagram
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Sequential Algorithm Complexity
● O( (T+C) steps ) = O( (T+C) * (N+E))– Where C = cycle size, T = transient size
Network State diagram
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Our Approach: Parallel Step Computation O(1)
One clock cycle to visit all Nodes and all Edges
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Simulation Based Model
• 100 genes, 2100 states– Impossible to visit all state space
• Generate a large number of random networks and sample
BiologicalKnowledge
models
Revise Models(topologies,
Boolean functions....)
MapNetwork
Initial statesimulate
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Simulation Based Model
• 100 genes, 2100 states– Impossible to visit all state space
• Generate a large number of random networks and sample
BiologicalKnowledge
models
Revise Models(topologies,
Boolean functions....)
MapNetwork
Initial statesimulate
GenerateNetworks
10 000 Randomnetworks
1000Initialstates
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Previous Approaches on FPGA
NetworkGeneration
SíntesePlace & Route
para FPGA
SynthesisPlace & Route
FPGA
SíntesePlace & Route
para FPGAFPGA
Configuration
SíntesePlace & Route
para FPGAExecution
TimeConsuming > Configuration Execution
Time Time.
[Zerarka, 2004], [Pournara, 2005]Synthesis Time is not reported
Minutes, hours μs
Map NetworkOn FPGA
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Our Approach
NetworkGeneration
Size N
SíntesePlace & Route
para FPGA
SynthesisPlace & Route
FPGA
FPGAConfiguration
ArchitectureFramework
Map GenericFree ScaleNetwork
interconnections
NodeVhdl generator
Dynamic Reconfiguration
To generate severalnetworks
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Our Approach
NetworkGeneration
Size N
SíntesePlace & Route
para FPGA
SynthesisPlace & Route
FPGA
FPGAConfiguration
ArchitectureFramework
Map GenericFree ScaleNetwork
interconnections
SynthesisOnce !
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Proposed Architecture Framework
ArchitectureFramework
interconnections
Each node isMapped on
Process Element (PE)Which implement a
FSM
S0
S1
FSM
Receive data fromThe neighbour
Compute new state
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We propose Dynamic InterconnectionsMultistage Interconnection
O( N log2 N)
Edges are mapped
networkmappednetwork
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Change configuration
New Network remapped
network
Generate a new randomNetwork
reconfigure Multistage
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Generation and Simulation
Newnetwork
DynamicInterconnection
Network
V1
V2
Vn
Several Networks are generated
FPGA
NewConfig.
returnAttractor
size
InitialStates
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Scale Free Networks and Architecture
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Scale Free Networks and Architecture
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Scale Free PE architecture
Network PE Size Distribuition
Size 1 2 4 8 16 32
100 49 28 11 12
200 98 57 25 15 5
300 176 44 30 30 15 5
400 248 80 30 30 8 5
Large numberOf poorly connected
Few number ofStrongly connected
Generic PE distribution
Few number ofStrongly connected
Each random Scale Free
Has different PEdistribution
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Scalable Architecture
Network PE Size Distribuition FPGA
Size 1 2 4 8 16 32 Occupancy
100 49 28 11 12 4.4%
200 98 57 25 15 5 9.5%
300 176 44 30 30 15 5 10.9%
400 248 80 30 30 8 5 12.2%
Double Size
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CPU and FPGA Execution Time
Network sub- CPU FPGA
size edges steps (ms) (μs) speed-up
100 933 5 8.12 13 706
200 2331 7 55.9 43 1300
300 4285 14 104.4 98 1128
400 4816 19 69.0 70 976
3 order of magnitude
10.000 networks + 100 Initial states → 27 hours 10.000 networks + 100
Initial states → 2 minutes
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Dynamic Interconnection Size and configuration bits
Multistage FPGA memories
Size LUTs occupancy (max. 416)
128 1015 0.6% 14
256 1777 1.2% 32
512 4065 2.3% 72
1024 8447 5.6% 160
O(n log2 n)
ConfigurationBits
Up to 512 differentconfigurations
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Conclusions
• FPGA acellerators• Bioinformatics – Large amount of Data
and parallelism• Proposed Implementation
– Speed up : 2-3 Order of Magnitude– Dynamic Interconnection Reconfiguration – Real World: 100-2000 nodes
• Suitable for FPGA Technology
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Conclusions
• Model Scale Free Network on FPGA• FPGA Embedded Memories
– Reduce space of reconfiguration bits
• Multistage Interconnection– Dynamic
– O(n Log2 n)
• Generic Architecture Framework– FSM computation → nodes– Multistage → edges
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Future Works
• Exploration of Gene Regulatory Networks– Boolean Functions– Topologies– Probabilistic Models
• Generic Architecture– Nodes + Dynamic Edges– Model others Cellular Automata Problems