flow sensor circuitry eduard stikvoort 00/1a the work was done in philips reaearch eindhoven
TRANSCRIPT
Flow sensor circuitryEduard Stikvoort
00/1A
The work was done in Philips Reaearch Eindhoven
1.0 Overview
01/1A
1 Introduction
2 Amplifiers
3 A/D
4 Comparator
5 Test ICs
6 Discussion
7 Conclusions
1.1 Introduction
02/1A
- wireless flowsensor for infuse pumps
- sensor heats the liquid (e.g. 1 degree) and measures
temperature difference
- output of the sensor is a few mV
- powered by incoming E.M. field
- output data transmitted
IC process: 0.18 um CMOS
1.2 Overview flow sensor
03/1A
input antenna
heater
thermo pile A/D
transmit antenna
22-26
supply timing
1x
modulator
transmitter
2.0 Amplifiers
04/1A
Flow sensor
2 switched cap. amplifiers: - switched gain 4x ,... , 64x - 1x buffer for capacitive load of A/D
For test IC's 1x buffer for driving off chip load
A / D
50 pF
2.1 Switched Cap. amplifier
05/1A
-
Vin
Ca
Cb
ref
Vu
+
-
+
-
Vo+
- Cb/Ca sets the gain- offset
+
+
gnd
OTA
2.2 Two-phase operation
06/1A
-
Vin
Ca
Cb
sample offset and signal data transfer
ref
.
-
Vin
Ca
Cb
ref
Vu
+
-
+
-
Vo+
+
-
VoVu
+
-
Ca + QCb = Ca (-Vo) +Cb (Vin-Vo)Ca+ QCb = Ca (Vu-Vo) + Cb (-Vo)
Cb Vin = Ca Vu Vu / Vin = Ca / Cb
Q Q
results in or
+
++
+
2.3 OTA circuit
07/1A
dacref
in 20 nA
out
in
0
180f
+ 1,7
20/1 60/2.2
60/2.2
60/2.2
10/4.7
10/4.7
15/6.8
30/2.230/2.2
50/3.350/3.3 6.8/3.36.8/3.3
3.3/3.3
15/6.8
transistordimensions in
um
bias current 0.7 uA
2.4 Simulation results S.C. Amp.
08/1A
simulated input, output and clock
2.5 IC-output buffer
09/1A
in 1 uA
uit
in
0
+ 310/1
60/1
60/1
60/1
200/2.2200/2.2
140/3.3140/3.320/3.33.3/3.3
20/0.34
10/1
820k
820k
for driving off chip loadoscilloscope + cable e.g. 50 pF
Bias current 150 uA0 - 1 MHz in 68 pF
0A/1A
simulated frequency response off-chip output (load = 68 pF)
2.6 Simulation IC-output buffer
3.0 A/D
0B/1A
cold side capacitors to ground or regulated supplycomparator input to Vstab/2 = Vref
SC
Clad Clad2CladSC
bit 0 (msb)
bit 1
bit 2
bit 3
bit 9 (lsb)
3 > 8
thermometercoder
1.7V stab.
1.7V stab.
1.7V stab.
1.7V stab.
SARregister
in
outCber
Clad2
V stab/2
Clad 2d
input sampled in capacitor bank (MSB=1, other bits 0)
3.1 A/D input range
0C/1A
Cber
Ck+
Vs
Vin
Vin = Vs Ck / (CAD + Cber)
CAD = Cbit0+Cbit1 + . . . CMSB
peak-to-peak input range =
Vs CAD / (CAD+Cber)
3.2 A/D timing diagram
0D/1A
bit0bit1bit2bit3bit4bit5bit6bit7bit8bit9
SCClad
comparator gives ‘1’
3.3 Thermometer coding 3 MSB's
0E/1A
- improves linearity when segments spread
0 1 2 3 4 5 6 7in
out
0 1 2 3 4 5 6 7in
out
4.0 Comparator circuit
0F/1A
in
ref.
aa bb
aa
bb outpos
outneg
en
in uit
en
in uit
Clad2 Clad2d
3/0,5 3/0,5
36/0,3436/0,34
4/0,34
2/0,34
2/0,34 2/0,34
2/0,34
3/0,34
3/0,34 3/0,34
3/0,34
0,24/0,47
0,24/0,47
0,24/0,34 0,24/0,34
0
+
0
220k
+
comparator output latch
input stage NOR flipflop
Clad
4.1 Comparator simulations
10/1A
input, output and clocknot output changes with delayed clocknot
5.0 Test ICs
11/1A
- input amplifier
- 1x amplifier, IC-output Amp.
- comparator
- A/D
5.1 Test IC with first amplifier
12/1A
on
off
on
off on
off
on
off
on
off
on
offon
off
on
off
on
off
end
g5
g6
g2
g3
on
off
in (sel) in (sel)
selekt
Clamina
VrefVref
+ -
10f10f
20f
160f
160f320f
out+ -
5.2 Layout of amplifier IC
13/1A
5.3 Test IC with 1x amplifier
14/1A
IC ouput buffer output + 1x S.C. Amp.
5.4 Test IC with comparator
15/1A
5.5 Test IC with A/D
16/1A
VstabVpos
daad
CLad
CLad2
SC
SAR register(digital)
mm
nn
oo
pp
rr
ss
bit3
bit4
bit5
bit6
bit7
bit8
bit9
SCanot
A/D in
Cber
Clad2
outpos
outneg
comparator
in
ref
2,7M 10 p
2,7M
Vstab
CladClad2d
Vpos
verg.
5.6 A/D test IC
17/1A
supplies:- stabilised - digital - for I/O
one ground
MIM capacitors (M5/M6,M4 shield) on top of the circuit
6 Discussion
18/1A
- signal path was presented, other parts were not
(clock oscillator, timing, modulator, supply,
stabiliser, transmitter)
- adjustable gain for uncertenty of sensor sensitivity
- 2 switched cap. amplifiers (gain of the OTA)
- gates of the SAR directly drive the bit capacitors
- standard logic not used for less dissipation
7 Conclusions
19/1A
- test ICs for a wireless flow sensor
- switched capacitor amplifiers, latched comparator
- 10 bits A/D
- test ICs have home-made analogue IC-ouput, standard digital I/O