Floating Point Unit

8087 Coprocesor

8087: a 40-pin Coprocessor

Connection to Processor

FPU: Floating Point Unit• Helps the Processor for floating point calculations• Part of a cpu. (Inside Pentium and 486)• Direct support for:

– floating-point– Extended integer– BCD data types

• Supports Standard IEEE 754 & 854 • Compatible with object code for

– 8087 for 8086– Intel287 for 80286– Intel387 DX & SX – Intel487 DX – Intel486 DX: when in 66MHz = 1/3 Performance of Pentium (66

MHz)

Comparison of 8087 and 8086 Clock Times

In some cases the differences of run times is hours between

PCs with and without math-coprocessor.

Real Number Representationb b bb b b

b

b

Numeric Data Types

Floating-Point Manipulation

• IEEE Floating Point Format• FPU Registers• DATA TRANSFER• BASIC ARITHMETIC• COMPARISON• TRANSCENDENTAL• LOAD CONSTANTS• FPU CONTROL

FPU CONTROL• FINCSTP Increment FPU register stack pointer• FDECSTP Decrement FPU register stack pointer• FFREE Free floating-point register• FINIT Initialize FPU after checking error conditions• FNINIT Initialize FPU without checking error conditions• FCLEX Clear floating-point exception flags after checking for error• conditions• FNCLEX Clear floating-point exception flags without checking for error• conditions• FSTCW Store FPU control word after checking error conditions• FNSTCW Store FPU control word without checking error conditions• FLDCW Load FPU control word• FSTENV Store FPU environment after checking error conditions• FNSTENV Store FPU environment without checking error conditions• FLDENV Load FPU environment• FSAVE Save FPU state after checking error conditions• FNSAVE Save FPU state without checking error conditions• FRSTOR Restore FPU state• FSTSW Store FPU status word after checking error conditions• FNSTSW Store FPU status word without checking error conditions• WAIT/FWAIT Wait for FPU• FNOP FPU no operation

Branch Preparation

FCOMI, FCOMIP, FUCOMI, and FUCOMIP) compare two floating-point values and set the ZF, PF, and CF flags in the EFLAGS register directly.(Pentium Pro Only)

LOAD CONSTANTS

• FLD1 Load +1.0• FLDZ Load +0.0• FLDPI Load • FLDL2E Load log2e• FLDLN2 Load loge2• FLDL2T Load log210• FLDLG2 Load log102

TRANSCENDENTAL• FSIN Sine• FCOS Cosine• FSINCOS Sine and cosine• FPTAN Partial tangent st(0)=tan(st(0)); 1push register stack• FPATAN Partial arctangent• F2XM1 st(0)=2^st(0) 1• FYL2X ylog2x• FYL2XP1 ylog2(x+1)

COMPARISON• FCOM m32/m64/st(I)/none st(0):src flags:c0,c1,c2• FCOMP Compare real and pop• FCOMPP Compare real and pop twice• FUCOM Unordered compare real Does not generate an invalid-

arithmetic-operand exception• FUCOMP Unordered compare real and pop• FUCOMPP Unordered compare real and pop twice• FICOM m16/m32 Compare with integer• FICOMP Compare integer and pop• FCOMI Compare real and set EFLAGS(Z,P,C)• FUCOMI Unordered compare real and set EFLAGS• FCOMIP Compare real, set EFLAGS, and pop• FUCOMIP Unordered compare real, set EFLAGS, and pop• FTST Test real Compare St(0):0.0• FXAM Examine real

FXAM

C1 sign bit of ST; (* 0 for positive, 1 for negative *)

BASIC ARITHMETICFloatng point Addition/subtractionFSUBR, FSUBRP, FISUBR Reverse SubtractionFMUL Multiply realFMULP Multiply real and popFIMUL Multiply integerFDIV Divide realFDIVP Divide real and popFIDIV Divide integerFDIVR, FDIVRP, FIDIVR Reverse DivisionFPREM Partial remainder FPREMI IEEE Partial remainder st(0)%=st(1)FABS Absolute valueFCHS Change signFRNDINT Round to integerFSCALE Scale by power of two st(0)=st(0)*2^st(1)FSQRT Square rootFXTRACT st(0)=exponent(st(0)) significandregister stack

Floating Point Addition/Subtraction

DATA TRANSFERFLD m32real/m64real/m80real/st(I) push onto FPU register stackFST m32real/m64real/st(I) store st(0) on m32…. FSTP m32real/m64real/m80real/st(I) FST & pop stackFILD m16/m32/m64 Load integer. push onto FPU register

stackFIST Store integerFISTP Store integer and popFBLD Load BCDFBSTP Store BCD and popFXCH st(I)/none Exchange registers st(0) and st(I)/st(1)FCMOVE Floating-point conditional move if equalFCMOVNE Floating-point conditional move if not equalFCMOVB Floating-point conditional move if belowFCMOVBE Floating-point conditional move if below or equalFCMOVNB Floating-point conditional move if not belowFCMOVNBE Floating-point conditional move if not below or equalFCMOVU Floating-point conditional move if unorderedFCMOVNU Floating-point

Binary Floating Point Format

J-Bit is implied

Normalized Representation: 1<= Significand < 2

Exponent is Biased, So always it is positive

Convert 9.75 to single-precision floating point

Convert 0.078125 to short real FP

Convert -96.27 to short real FP

Convert 152.1875 to double-precision

Encoding Special Values• Signed zeros : 0+ or 0-

• Denormalized finite numbers.

• Normalized finite numbers.

• Signed infinities.

• NaNs : Not a Number

Quiet NaNs

No exception

Signaling Nans

• Indefinite numbers.

FPU Registers

Error Pointers: Instruction & Operand

16bit Selector + 32 bit address

Opcode of the last non-control FPU instruction.

Example

FPU Control Word

FPU Status & TAG Register

Save Reg: FSTSW/FNSTSW, FSTENV/FNSTENV, FSAVE/FNSAVE

Condition Codes

Correspondence Between FPU and CPU Flag Bits

Opcode Field

FCOM, FCOMP, FCOMPP

C1 Set to 1 if stack underflow occurred; otherwise, cleared to 0.

Floating-Point Exceptions

#IS Stack underflow occurred.

#IA One or both operands are NaN values or have unsupported formats. Register is marked empty.

#D One or both operands are denormal values.