flip flop mealy and moore model

8/9/2019 Flip Flop Mealy and Moore Model

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ASeminar Report

OnFLIP FLOP CIRCUITS, MEALY AND

MOORE MODEL

In partial fulfillment of requirements for the degree ofBachelor of Engineering

InElectronics & Communication Engineering

Submitted By

SURAJ. P. B

Department of Electronics Engg:

Govt Engineering College! "hrissur

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I#DE$

% Introduction 'age (

) S* +atch 'age ,

( D -lip-lop . 'age /

, 01 -lip -lop . 'age 2

3 " -lip flop . 'age %4

5 6ealy and 6oore 6odel 7ith e8amples . 'age %%

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http://www.circuitstoday.com/flip-flop-conversion#SRtoJKhttp://www.circuitstoday.com/flip-flop-conversion#SRtoJK


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Introduction

The circuits stored information about the previous history of inputs are called storage or memory elements. A primitive storageelement can be constructed from a small number of gatesconnecting the outputs back as inputs. These circuits are binarycells capable of storing one bit of information. They have twooutputs, one for the normal value and one for the complement valueof bit stored in it. Primitive memory elements actually fall into twoboard classes : latches and fip-fop.

If a latch has only data inputs, it is called an unlocked latch (oronly latch. !evel"sensitive latches have an additional enable input,sometimes called the clock . !evel"sensitive latches continuouslysample their inputs when they are enabled. Any change in the levelof the input is propagated through to the output. #hen the enablesignal is unasserted, the last value of the inputs is determines thestate held by the latch.

$lip"%ops di&er from latches in that their output change only withrepeat to the clock, whereas latches change output when theirinputs change. $lip"%ops are characteri'ed on the basis of the clocktransition that cause the output change : there are positive edge-triggered, negative edge-triggered, and master/slave %ip"%ops.

A positive edge"triggered %ip"%op samples its inputs on the low"to"high clock transition. A negative edge"triggered %ip"%op works ina similar fashion, with the input sampled on the high"to"low clocktransition.

A master"slave %ip"%op is constructed from two stage separate%ip"%ops. The rst stage ( rst %ip"%op samples the inputs on therising edge of a clock signal. The second stage transfer them to theoutput on the falling edge of the clock signal.

These circuits have two additional control inputs. These are

Preset and )lear, which force the output of the %ip"%op or latch tothe logic"* or logic"+ state, respectively, independent of the %ip"%opor latch inputs.

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S-R Lat!"

• A "- ( et"-eset latch is the simplest possible memory element.

• It is constructed by feeding the outputs of two /- gates back to

the other /- gates input.

• The inputs - and are referred to as the -eset and et inputs,respectively.

• To understand the operation of the "- latch consider the

following scenarios :

• S#$ an% R#&" The output of the bottom /- gate is e0ual to

'ero,

0Q =′

.

• 1ence both inputs to the top /- gate are e0ual to 'ero, thus,1Q =

.

• 1ence, the input combination 2* and -2+ leads to the latch

being set to

1Q =

.

• S#& an% R#$" imilar to the arguments above, the outputs

become

1Q =′

and

0Q =

.

• #e say that the latch is reset.

• S#& an% R#&" Assume the latch is set (

0Q =′

and

1Q =

,

then the output of the top /- gate remains at

1Q =

and the

bottom /- gate stays at

0Q =′

.

• imilary, when the latch is in a reset state (

1Q =′

and

0Q =

, it

will remain there with this input combination.

• Therefore, with inputs 2+ and -2+, the latch remains in its

state.

• S#$ an% R#$" This input combination must be avoided

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S

Q

Q '

R-

3

34

QS

Q 'R

-

3

34

• The logic diagram and graphic symbol are shown in

$igure.5.*.

• The following truth table can be summari'ed the operation of the "- latch.

(a !ogic 6iagram (b7raphic

ymbol

- 3 34 )omment

+ + 3 34 1oldtate

+ * + * -eset

* + * + et

* * " " $orbidden

(c Truth table

$igure.5.* "- latch with /- gates.

• A "- latch can also be constructed from A6 gates.

The graphic symbol, logic diagram, and truth table of the latch are shown in $igure.5.8.

(a !ogic 6iagram (b7raphicymbol

- 3 34 )omment

* * 3 34 1oldtate

+ * * + et

* + + * -eset

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-

3

34

R

SQ

Q '

C)

+ + " " $orbidden

(c Truth table

$igure.5.8 "- latch with A6 gates.

Level Sensitive (Clock) S-R Latch:

The operation of the "- latch can be modied by providing anadditional control input that determines when the state of the circuit isto be changed. The logic diagram, graphic symbol, and thruth table of level sensitive "- latch are shown in $igure.5.9 *;.


- ) 3 34 )omment

+ + * 3 34 1oldtate

+ * * + * -eset

* + * * + et

* * * " " $orbidden

< < + 3 34 1oldtate

(c Truth table

$igure.5.9 !evel ensitive "- latch with A6 gates.

Level Sensitive (Clock) D (Delay) Latch :

/ne way to eliminate the undesirable condition of theindeterminate state in the "- latch is to ensure that inputs and - arePage


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6

)

3

34

Q

D

Q '

C

=

>

3

34

)

Q '

Q

C

K

J

never e0ual to * at the state time. This is done level sensitive 6 latchshown in $igure.5.5. The latch has only two inputs: 6 and ). The 6input connect directly to the input and its complement is applied tothe - input. The 6 input is sampled when ) is e0ual to *. If 6 ise0ual to *, the 3 output goes to *. If 6 is e0ual to +, the 3 output goesto +. If ) is e0ual to +, the 3 output remains in its previous state *;.


) 6 3 34

* + + *

* * * +

+ < 3 34

(c Truth table

$igure.5.5 !evel ensitive 6 latch with A6 gates.

Level Sensitive (Clock) J-K Latch:

A level sensitive ="> latch shown in $igure.5.? is a renement of the "- latch in that the indeterminate state of the "- type is denedin the ="> type. Inputs = and > behave like inputs and - to set andclear the latch, respectively. The input marked = is for set and the

input marked > is for reset. #hen the both inputs = and > are e0ual to*, the latch switches to its complement state, that is , if 32*, itswitches to 32+, and vice versa. If the ) is e0ual to +, The output of the latch remains in its previous state *;.

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) = > 3 34 )omment

* + + 3 34 1old

* + * + * -eset

* * + * +4 et

* * * 34 3 Toggle

+ < < 3 34 1old

(c Truth table

$igure.5.? !evel ensitive ="> latch.

6 $lip"$lop:

Positive"@dge Triggered:

)!> 6 3 34

+ + *

* * +

+ < 3 34

* < 3 34

(a Truth table (b 7raphic ymbol

$igure.5.. Positive edge"triggered 6 %ip"%op.

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6

)!>

3

34

Negative-Edge Triggered:

)!> 6 3 34

+ + *

* * +

+ < 3 34

* < 3 34


$igure.5.B. Positive edge"triggered 6 %ip"%op.

J-' F(ip-F(op"

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=

>

3

34

)!>

ositive-Edge Triggered:

)!> = > 3 34

+ + 3 34

+ * + *

* + * +

* * 34 3

+ < < 3 34

* < < 3 34


$igure.5.C. Positive edge"triggered ="> %ip"%op.Negative-Edge Triggered:

)!> = > 3 34

+ + 3 34

+ * + *

* + * +

* * 34 3

+ < < 3 34* < < 3 34


$igure.5.D. egative edge"triggered ="> %ip"%op.

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=

>

3

34

)!>

T!>

T F(ip-F(op"

The T %ip"%op is a single"input version of the ="> %ip"%op. Asshown in $igure.5.*+, the T %ip"%op is obtained from the ="k %ip"%opwhen both inputs are tied together. The designation T comes from theability of the %ip"%op to toggle, or complement, its state. #hile input T is *, The %ip"%op complements its output when the clock pulse

occurs. #hile T is +, The output of the %ip"%op remains in its previousstate *;.

)!> T 3 34

+ 3 34

* 34 3

+ < 3 34

* < 3 34


$igure.5.*+. egative @dge"Triggered T %ip"%op.

Moore & Mealy Machines

Sequential Design Review:

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- A binary number can represent 2n states, where n is the number o bits!

- "he number o bits re#uire$ is $etermine$ by the number o states! %&! ' states re#uires 2 bits (2

2 ) ' possib*e states+

%&! 1 states re#uires bits (25 ) .2 possib*e states+

- /ne *ip-*op is re#uire$ per state bit!

Steps to Desin Se#uentia* Circuits

1+ Draw a State Diaram

2+ a3e a 4e&t State "ruth "ab*e (4S""+.+ 5ic3 6*ip-6*op type

'+ A$$ 6*ip-6*op inputs to 4S"" usin 6*ip-6*op e&citation

e#uation ("his creates an %&citation "ab*e!++ So*7e e#uations or 6*ip-6*op inputs (K-maps+

8+ So*7e e#uations or 6*ip-6*op outputs (K-maps+

9+ :mp*ement the circuit

Moore State Machines:

- /utputs $etermine$ solely by the current state- /utputs are unconditional (not $irect*y $epen$ent on input sina*s+

INPUT

INPUT INPUT

STATE STATE

OUTPUT OUTPUT

INPUT

GENERIC MOORE STATE MACHINE

4ote "his shou*$ *oo3 at *ot *i3e the counter $esins $one pre7ious*y!

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%&amp*e Desin a simp*e se#uence $etector or the se#uence 011! :nc*u$e three outputs

that in$icate how many bits ha7e been recei7e$ in the correct se#uence! (6or e&amp*e,

each output cou*$ be connecte$ to an ;%D!+

1+ Draw a State Diaram (oore+ an$ then assin binary State :$entiiers!

X=1X=0

X=0

A B

000 001

X=0

X=1 X=0 X=1

D C

111 011

X=1

MOORE SEQUENCE DETECTOR FOR 011

4ote State


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STATES

A=00

B=01

C=11

D=10

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.+ 5ic3 6*ip-6*op type

- 5ic3 D 6*ip-6*op

'+ A$$ 6*ip-6*op inputs to 4S"" to ma3e an e&citation tab*e

Q1 Q0 X O2 O1 O0 Q1+

Q0+

D1 D0

0 0 0 0 0 0 0 1 0 1

0 0 1 0 0 0 0 0 0 0

0 1 0 0 0 1 0 1 0 1

0 1 1 0 0 1 1 1 1 1

1 0 0 1 1 1 0 1 0 1

1 0 1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 1 0 1

1 1 1 0 1 1 1 0 1 0

+ So*7e e#uations or 6*ip-6*op inputs (K-maps+

X\Q1Q0 00 01 11 10

0 0 0 0 0

1 0 1 1 0

D1 = XQ0

X\Q1Q0 00 01 11 100 1 1 1 1

1 0 1 0 0

D0 = X +Q1Q0


Q1\Q0 0 1 Q1\Q0 0 1 Q1\Q0 0 1

0 0 0 0 0 0 0 0 1

1 1 0 1 1 1 1 1 1

O2 = Q1 O1 = Q1 O0 = Q1 +Q0Q0

4ote oore $esins $o not $epen$ on the inputs, so > can be ne*ecte$!

?+ :mp*ement the circuit


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%&amp*e Desin a se#uence $etector that searches or a series o binary inputs to satisy

the pattern 01@0B1, where @0B is any number o consecuti7e eroes! "he output (+

shou*$ become true e7ery time the se#uence is oun$!

* Draw a State Diaram (oore+ an$ then assin binary State :$entiiers!


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Reca** 5ic3in state i$entiiers so that on*y one bit chanes rom state to state wi**

enera**y he*p re$uce the amount o har$ware re#uire$ or imp*ementation! /n*y

the transition rom Success to 6irst re#uires two bits to chane!

2+ a3e a 4e&t State "ruth "ab*e (4S""+

State Q2 Q1 Q0 X

Start 0 0 0 0Start 0 0 0 1Firt 0 0 1 0Firt 0 0 1 1

S!""e 0 1 0 0S!""e 0 1 0 1

Se"#$% 0 1 1 0Se"#$% 0 1 1 1

U$!e% 1 0 & &

S!""eD 1 1 0 0S!""eD 1 1 0 1

De'a( 1 1 1 0

De'a( 1 1 1 1


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4ote "he ea*y achine re#uires one *ess state than the oore achineE "his is

possib*e because ea*y achines ma3e use o more inormation (i!e! inputs+ than

oore achines when computin the output! Fa7in *ess states ma3es or an easier

$esin because our truth tab*es, K-maps, an$ *oic e#uations are enera**y *ess

comp*e&! :n some cases, the re$uction o states is siniicant because it re$uces the

number o *ip-*ops re#uire$ or $esin imp*ementation! :n spite o the a$7antaes ousin a $esin with *ess states,

We will still use the 6-state

Mealy Machine for the remainder of these notes to facilitate a direct

comarison with the 6-state Moore Machine!

2+ a3e a 4e&t State "ruth "ab*e (4S""+


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State Q2 Q1 Q0 X


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Start 0 0 0 0Start 0 0 0 1Firt 0 0 1 0

Firt 0 0 1 1S!""e 0 1 0 0

S!""e 0 1 0 1Se"#$% 0 1 1 0

Se"#$% 0 1 1 1!$!e% 1 0 & &

S!""eD 1 1 0 0S!""eD 1 1 0 1

De'a( 1 1 1 0

De'a( 1 1 1 1

) State+

Q2+

Q1+

Q0+

0 Firt 0 0 10 Start 0 0 00 Firt 0 0 1

0 Se"#$% 0 1 10 Firt 0 0 10 Start 0 0 00 De'a( 1 1 11 S!""e 0 1 0

X X X X X

0 De'a( 1 1 11 S!""e 0 1 0

0 De'a( 1 1 1

1 S!""eD 1 1 0

4ote "his is i$entica* to the oore achine, e&cept or output !

.+ 5ic3 6*ip-6*op

type Se*ect D

6*ip-6*ops!!

'+ A$$ 6*ip-6*op inputs to 4S"" usin 6*ip-6*op e&citation e#uation

State Q2 Q1 Q0 X ) State

+Q2

+Q1

+Q0

+D2 D1 D0

Start 0 0 0 0 0 Firt 0 0 1 0 0 1Start 0 0 0 1 0 Start 0 0 0 0 0 0Firt 0 0 1 0 0 Firt 0 0 1 0 0 1

Firt 0 0 1 1 0 Se"#$% 0 1 1 0 1 1S!""e 0 1 0 0 0 Firt 0 0 1 0 0 1


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S!""e 0 1 0 1 0 Start 0 0 0 0 0 0Se"#$% 0 1 1 0 0 De'a( 1 1 1 1 1 1

Se"#$% 0 1 1 1 1 S!""e 0 1 0 0 1 0

!$!e% 1 0 & & X X X X X X X X

S!""eD 1 1 0 0 0 De'a( 1 1 1 1 1 1S!""eD 1 1 0 1 1 S!""e 0 1 0 0 1 0

De'a( 1 1 1 0 0 De'a( 1 1 1 1 1 1

De'a( 1 1 1 1 1 S!""eD 1 1 0 1 1 0

+ So*7e e#uations or 6*ip-6*op inputs (K-maps+

Q2Q1\Q0X 00 01 11 10 Q2Q1\Q0X 00 01 11 10 Q2Q1\Q0X 00 01 11 10

00 0 0 0 0 00 0 0 1 0 00 1 0 1 101 0 0 0 1 01 0 0 1 1 01 1 0 0 111 1 0 1 1 11 1 1 1 1 11 1 0 0 110 X X X X 10 X X X X 10 X X X X

D2 = Q2Q0 +Q2 +Q1Q0 D1 = Q2 +Q1Q0 +Q0 X D0 = X X Q0 X +Q0 X +Q1Q0

4ote "his is i$entica* to the oore achine!


oore ea*yQ2Q1\Q0 0 1 Q2Q1\Q0X 00 01 11 10

00 0 0 00 0 0 0 001 1 0 01 0 0 1 0

11 1 0 11 0 1 1 010 X X 10 X X X X

Z Moore

=

Q1

Z Mealy

=

Q2

X

+Q1

Q0

X Q0

Reca** oore outputs $o not $epen$ on the input!

- oore can on*y chane when the state chanes (synchronous+!

- ea*y can chane asynchronous*y because it can chane with >!

4ote "he oore an$ ea*y achines so*7e the same prob*em!

9+ :mp*ement the circuit

D)D 9

9)

$! 9)! 9%! 94 Combo

+ogic D--

C 9

D% 9%:D 9

$! 9)! 9%! 94 Combo

Combo


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+ogic D-- +ogic

C 9

D4 D 9 94

$! 9)! 9%! 94 Combo

+ogic D--

C 9

Cl;

4otes "he . bo&es o combinationa* *oic on the *et are the same or both o the oore

an$ ea*y $esins because the state transitions are the same! "his wou*$ not ha7e been

the case ha$ we imp*emente$ the -state ea*y achine!

"he *arer bo& o combinationa* *oic on the riht is $ierent or the oore an$ ea*y

$esins because the output, , is compute$ $ierent*y


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flip flop mealy and moore model

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