flextrate™ characterization - semi.org tak fukushima.pdf · embedded in pdms. the flexible...
TRANSCRIPT
-
FlexTrate Characterization
Tak Fukushima1, 2, Arsalan Alam1, Amir Hanna1, Ze Wan1, Siva Chandra Jangam1, Adeel. Bajwa1, and Subramanian S. Iyer1
1 Center for Heterogeneous Integration and Performance Scaling (CHIPS), Electrical Engineering Dept., UCLA, USA,
2 Dept. of Mechanical Systems Engineering, Tohoku Univ., Japan
-
1. Background on Flexible Hybrid Electronics2. Introduction of FlexTrateTM using
Fan-Out Wafer-Level Packaging (FOWLP)3. Fabrication Challenges4. Characterization5. Summary
Content
2
-
Similar to a bicycle chain:rigid segments with flexible links
New Concept of Flexible Hybrid Electronics (FHE)FlexTrateTM: Flexible Device Integration using FOWLP
Wire bonding and ball bumping
Ultra-thin dieFlexible substrate
Cross-section
Bird-eyeview
Conventional FHE
3
Sheet-level processing using printingHigh stress Source: Uniqarta
Wire bonding and ball bumping processes are not required for FlexTrateTM by using advanced FOWLP technologies. In addition, we dont have to use organic semiconductors and printing technologies such as screen- and inkjet-printing to make high-performance devices and high-density interconnect.
Source: K. Lee, T. Fukushima, M. Koyanagi et al.,IEEE ELECTRON DEVICE LETTERS, Vol. 34, 1038 (2013)
Flexible substrate
Small/thin Si dielets
This workHigh-density wirings
Low stress
Cross-section
Bird-eyeview
Wafer-level processing using photolithography
-
1. Chip assembly
2. Resin molding
3. Metallization(wiring formation)
1. Metallization(wiring formation)
2. Chip assembly
3. Resin molding
Quick Tutorial of FOWLP and Categories of FOWLP Flowhttps://semimd.com/insights-from-leading-edge/page/2/
4
FOWLPEpoxy Mold Compound (EMC)
Conventional flip-chip packages
Logic Memory
Logic Memory
Redistribution wiring layer (RDL)
C4 bump
Solder ball
Underfill EMC
Laminate (substrate)
Temporary adhesive/handlerTemporary adhesive/handler Temporary adhesive/handler
A10 Application Processor in Apple iPhone 7 Plus:/ Node: TSMC 16nm FinFET/ Die size: 125mm2/ RDL pitch: 10um (L/S 5/5m)
InFO (Integrated Fan-Out) /TSMC
FOWLP can eliminate laminate packages and dramatically increase the performance using the current technology node.
-
A Fabrication Flow of FlexTrateTM using Flexible FOWLP Process with a Biocompatible PDMS
This transfer process allows wafer-level processing based on FOWLP to make flexible inorganic semiconductor dielets with fine-pitch interconnects.
FlexTrateTM
5
-
6
Properties of a Biocompatible PDMS (SILASTIC MDX4-4210 / Dow)
PropertiesHardnessTensile strengthElongation at breakDielectric constant @ 100kHzDissipation factor @ 100KHzCTEYoung modulusTgThermal decomposition temp.Curing temp.
PDMS (MDX4-4210 / Dow)30 (Shore A)5 MPa~500%3.0 (3.01@100Hz) 0.001 (0.0009@100Hz) ~300 ppm/K0.5 MPa-120C200C or more25C - 80C Passed up to 29 days for implantationin the human body.
Epoxy Mold Compound (EMC)
< 1%
7.5 ppm/K22 GPa165C~ 200C125C - 150C NoneBiocompatibility
(screening test)
-
7
Metallization Challengesusing Stress Buffer Layer for Fin-Pitch Interconnetcs on PDMS
Metallization process on PDMSSi Si Si Si
Si wafer (2nd handler)
Pitch:10m
Line:3mTi/Au wire
Bufferlayer onPDMS
Si Si Si Si
Si wafer (2nd handler)
Si Si Si Si
Si wafer (2nd handler)
Si Si Si Si
Si wafer (2nd handler)
Si Si Si Si
Si wafer (2nd handler)
2. Metal deposition
1. Stress buffer layer formation (and contact hole formation)
4. Litho & metal etchingSi Si Si Si
Si wafer (2nd handler)
3. Photoresist coating (prebaking and cooling)
Stress buffer layer
Fine-pitch wiresStress buffer layer
500 m
Photoresist Crackgeneration !
Good adhesion
-
8
1-mm-square Si dielet(pitch: 1.8mm)
50mm
Si Si Si SiSi wafer (2nd handler)
Cross-section of measured structure
500-m-thickPDMS
1-mm-square Si dielets100m
3D Surface Profile of Multi-Dielets Transferred to the 2nd Handler
Height gaps
Total number of dielets: 625 (25 25)
By white light interferometer (cyberTECHNOLOGIES, CT100)
Die tiltCoplanarity
-
9
The lowest die tilt is given by the lowest temperature and thinner adhesion layer.The coplanarity is getting smaller (
-
10
Challenges in Typical FOWLP Technologies
1. Coplanarity and die tilt(height gap between mold and dies) Si Si Si Si
Epoxy mold
Dies Stand off height
3. Die shift(chip drift)
Sharma et al, IEEE CPMT vol. 1, p.502, 2011Average die shift: 45m
2. Wafer bow (warpage)
1 mm or more
Resin thickness (m)
010002000300040005000
0 200 400 600 8001000Calc
ulat
ed w
afer
war
page
(
m)
3.7m
PDMS
Epoxy
Calculated by Stoneys equation
300mm Si waferResin
4.7mm
-
11
Die Shift Evaluation
GlassAdhesive
GlassAdhesive
Dielets
5N/chipChipplacement
Methods
Before PDMS curing After PDMS curing (80C/ 30min)
10m10m
Vernier
Alignment mark Alignment mark
Die shift is nearly zero.
Dielets
PDMScuring
GlassAdhesive
Dielets
Si
80C/30min
Vernier patternon chips
Vernier patternon adhesive
Vernier patternafter assembly
PDMS
Vernier
-
12
Photos of 625 pcs of Dielets Placed on the 1st Si Handler (a)-(b) and the Dielets Transferred to the 2nd Si Handler (c)-(d)
1mm
4inch wafer
On the 2nd Si handler(c)
(b)(b)
625 pcs of 1-mm-square dielets
On the 1st Si handler
(a)
(d)
2) Multichip flip-chip assembly on the 1st handler
Si SiSi Si
5) Debonding from the 1st handler
Si wafer (2nd handler)
SiSi SiSi
Si wafer (1st handler)
1mm 1.8mm 1mm 1.8mm
-
13
Fine-pitch (pitch: 8m) wirings are successfully formed on PDMS.
mSiSi Si
Stress buffer layeron PDMS
Measured width: 18m Design: 20m
100m
500m
Line/space: 3.6m/4.4m
Pitch: 8m
Au wiringPDMS
Au wiringStress buffer layer on PDMS
High-Density Interconnects Connecting Neighboring Si Dielets Embedded in PDMS
-
14
Electrical Property of Fine Wirings on FlexTrateTM
Line width: 18m
Line width: 7m
Line width: 5m
Line width: 3m
0200400600800
100012001400160018002000
0 5 10 15Wire length (mm)
Resis
tanc
e (
)Si Si Si Si
Si wafer (2nd handler)
Cross-section of measured structure
Theoretical resistance:122
@18m(w),10mm(l),100nm(t)
(Au: 2.21x10-8 m)
-
15
Thick Metal Deposition for Reduced Resistances Thick metallization process on PDMS
Si Si Si Si
Si wafer (2nd handler)
3. Au electroplating (EEJA) & seed etching
1. Stress buffer layer formation& seed metal deposition
Si Si Si Si
Si wafer (2nd handler)2. Thick photoresist patterning
Si Si Si Si
Si wafer (2nd handler)
PDMS 5-m-thick Au wire
Si Si Si Si
Si wafer (2nd handler)
61.90
2.27 2.23 0
10
20
30
40
50
60
70
1 2 30.2-m-thickAu without
electroplating
5-m-thickAu with
electroplating
5-m-thickAu after
final release
Resis
tanc
e (
)
Au electroplatingby Electroplating Engineers of JapanLtd. (EEJA)
-
16
Electrical Property before/after 1,000 Cycle Repeated Bending
Fig. 2 Resistances before and after bending test
0
50
100
Beforebending
After1,000 cycle
bending
61.90 61.97
Resis
tanc
e (
)
40 mm
Wire width:95m
Au wirings (n=3) formed
on PDMSFig. 1 Picture of the sample specimens
Au thickness: 200nm
Top view
Tape
40mm
Test conditions:Curvature radius: 10 mmBending speed: 50 cycle/minCycle: 1,000 (< 20 min)
20mm
Line width: 95mLength: 40 mmAu thickness: 200 nm
#1
#2#3
Tape
Side view
#2 #3
#1
By a repeated bend tester (DLDMLH-FS / Yuasa System Co., Ltd., Japan)
-
Pictures of a Wearable Demonstrator of FlexTrateTM
625 Si dies embedded in PDMS
The flexible substrate FlexTrateTM embedding large numbers of small Si dies in the biocompatible PDMS is bendable, wearable & implantable, and can be attached on the curved surfaces such as the human arm or even inserted into the cranium.
625 Si dieletsembedded in PDMSPDMS
-
18
Summary We developed a technology platform called FlexTrateTM for new flexible device
integration with high-performance inorganic crystalline semiconductor dielets. Fine-pitch interconnects were successfully formed on a large number of small Si
dielets embedded in the PDMS by advanced FOWLP technologies usingpick&place assembly, low-temperature compression mold, and multichip transfer.
By using the low-modulus PDMS, there were little wafer warpages and die shift.Coplanarity between Si dielets and PDMS was well controlled by PDMS curingtemperatures and adhesive thicknesses
FlexTrateTM can be used for many leading edge wearable and biomedicalapplications requiring high-performance heterogeneous dielets (low-power logicand sensors) and fine-pitch interconnects that are not possible using conventionalprinted flexible electronics.
-
19
The Defense Advanced Research Projects Agency (DARPA) through ONR grantN00014-16-1-263 and the UCLA CHIPS Consortium supported this work. Partof the experimental work was performed in the Integrated SystemsNanofabrication Cleanroom (ISNC) of California NanoSystem Institute (CNSI) inUCLA and the Nanoelectronics Research Facility (NRF). The authors gratefullyacknowledge the support of K&S and staff at ISNC and NRF. The views,opinions and/or findings expressed are those of the authors and should not beinterpreted as representing the official views or policies of the Department ofDefense or the U.S. Government. The authors gratefully acknowledge thesupport of Global INTegration Initiative (GINTI) in Tohoku University, Japan.We also would like to acknowledge Dow Corning and NITTO for materialsupport, cyberTECHNOLOGIES for analytic services and Yuasa System forbending test support, and Electroplating Engineers of Japan Ltd. (EEJA) for Auelectroplating services.
Acknowledgements
-
Poster Presentation of FlexTrateTM:FlexTrateTM: For the next generation high performance flexible systems
Presentation schedules:6/20 (Tue)
Morning break: 10:00-10:50amLunch: 12:40-2:15pmExhibitor reception: 4pm-
6/21 (Wed)Morning break: 9:25-10:25amLunch: 11:50am-1:30pmAfternoon break: 2:55-3:55pm
Arsalan Alam, T. Fukushima, A. Hanna, Z. Wan, S. C. Jangam, A. Bajwa, and S. S. Iyer (UCLA)
Ph.D. candidate(EE Dept. UCLA)
Poster presentationEntrance
20
FlexTrate CharacterizationSlide Number 2Slide Number 3Slide Number 4Slide Number 5Slide Number 6Slide Number 7Slide Number 8Slide Number 9Slide Number 10Slide Number 11Slide Number 12Slide Number 13Slide Number 14Slide Number 15Slide Number 16Slide Number 17Slide Number 18Slide Number 19Slide Number 20