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  • 1YORK UNIVERSITY

    Verilog Review and Fixed Point Arithmetics

    Mokhtar Aboelazebased on slides by Dr. Shoab A. Khan

    CSE4210 Winter 2012

    YORK UNIVERSITY

    Overview Floating and Fixed Point Arithmetic System Design Flow

    Requirements and Specifications (R&S) Algorithmic Development in Matlab and Coding Guidelines

    2s Complement Arithmetic Floating Point Format Qn.m format for Fixed Point Arithmetic Addition, Multiplication and Scaling in Qn.m LTI systems and implementation in Qn.m format

  • 2YORK UNIVERSITY

    Floating & Fixed Point Arithmetic

    Two Types of arithmetic Floating Point Arithmetic

    After each arithmetic operation numbers are normalized Used where precision and dynamic range are important Most algorithms are developed in FP

    Ease of coding More Cost (Area, Speed, Power)

    Fixed Point Arithmetic Place of decimal is fixed Simpler HW, low power, less silicon Converting FP simulation to Fixed-point simulation is time consuming Multiplication doubles the number of bits

    NxN multiplier produces 2N bits The code is less readable, need to worry about overflow and scaling

    issues

    YORK UNIVERSITY

    System Design Flow and Fixed Point Arithmetic

  • 3YORK UNIVERSITY

    System Design Flow The requirements and specifications of the application are captured The algorithms are then developed in double precision floating point

    format Matlab or C/C++

    A signal processing system general consists of hybrid target technologies DSPs, FPGAs, ASICs

    For mapping application developed in double precision is partitioned into hardware & software

    Most of signal processing applications are mapped on Fixed-point Digital Signal Processors or HW in ASICs or FPGAs

    The HW and SW components of the application are converted into Fixed Point format for this mapping

    YORK UNIVERSITY

    Requirements & Specifications

    12V DC nickel metal hybrid, nickel cadmium or lithium-ion battery pack

    Handheld

    >10,000 hours MTBF55 dBHarmonic Suppression

  • 4YORK UNIVERSITY

    R&S of a UHF Radio (cont)

    Radio works as SDR and should be capable ofaccepting additional waveforms

    Waveforms

    > 600 hops/s, frequency hopping on full hopping band

    Frequency hopping

    Turbo codes, convolution, ReedSolomonFEC

    OFDM supporting BPSK, QPSK and QAMModulation

    Multi-path with 15 s delay spread and 220 km/hrelative speed between transmitter and receiver

    Channel

    Up to 512 kbps multi-channel non-line of sightData rate

    420 MHz to 512 MHzFrequency Range

    SpecificationsCharacteristics

    YORK UNIVERSITY

    Algorithm Development and Mapping

    The R&S related to digital design are forwarded to algorithm developers and system designers

    Algorithms are coded in behavioral modeling tools like Matlab

    The Matlab code is then translated into a high level language, for example, C/C++

    System is designed based on R&S System usually consists of hybrid technologies consisting of ASICs,

    DSPs, GPP, and FPGAs Partitioning of the application into HW/SW parts is

    performed The SW is then developed for the SW part and

    architectures are designed and implemented for the HW parts

    Integration and testing is performed throughout the design cycle

  • 5YORK UNIVERSITY

    Guidelines for Matlab Coding Signal processing applications are mostly developed in

    Matlab As the Matlab code is to be mapped in HW and SW so

    adhering to coding guidelines is critical The code must be designed to work for processing of data in

    chunks The code should be structured in distinct components

    Well defined interfaces in terms of input and output arguments and internal data storages

    All variables and constants should be defined in data structures User defined configurations in one structure System design constants in another structure Internal states for each block in another structure

    Initialization in the start of simulation

    YORK UNIVERSITY

    Processing in Chunks% BPSK = 1, QPSK = 2, 8PSK = 3, 16QAM = 4% All-user defined parameters are set in structure USER_PARAMSUSER_PARAMS.MOD_SCH = 2; %select QPSK for current simulationUSER_PARAMS.CHUNK_SZ = 256; %set buffer sizeUSER_PARAMS.NO_CHUNKS = 100;% set no of chunks for simulation% generate raw data for simulationraw_data = randint(1, USER_PARAMS.NO_CHUNKS*USER_PARAMS.CHUNK_SZ)% Initialize user defined, system defined parameters and statesPARAMS = MOD_Params_Init(USER_PARAMS);STATES = MOD_States_Init(PARAMS);mod_out = [];% Code should be structured to process data on chunk-by-chunk

    basisfor iter = 0:USER_PARAMS.NO_CHUNKS-1

    in_data = raw_data(iter*USER_PARAMS.CHUNK_SZ+1:USER_PARAMS.CHUNK_SZ*(iter+1));[out_sig,STATES]= Modulator(in_data,PARAMS,STATES);mod_out = [mod_out out_sig];

    end

  • 6YORK UNIVERSITY

    Fixed Point vs. Floating Point HW

    Algorithms are developed in floating point format using tools like Matlab

    Floating point processors and HW are expensive Fixed-point processors and HW are used in

    embedded systems After algorithms are designed and tested then

    they are converted into fixed-point implementation

    The algorithms are ported on Fixed-point processor or application specific hardware

    YORK UNIVERSITY

    Digital Signal Processors

  • 7YORK UNIVERSITY

    Number Representation In a digital design fixed or floating point numbers

    are represented in binary format Types of Representation

    ones complement sign magnitude canonic sign digit (CSD) twos complement

    In digital system design for fixed point implementation the canonic sign digit (CSD), and twos complement are normally used

    YORK UNIVERSITY

    2s Complement

    MSB is the sign bit (has a negative weight)

    23 22 21 20

    1 0 1 1

    -8 +0 +2 +1= -5

    23 22 21 20

    0 1 1 0

    0 +4 +2 +0 = 6

  • 8YORK UNIVERSITY

    Floating Point Format Floating point arithmetic is appropriate for high precision

    applications Applications that deals with number with wider dynamic range A floating point number is represented as

    s represents sign of the number m is a fraction number >1 and < 2 e is a biased exponent, always positive The bias b is subtracted to get the actual exponent

    bes mx = 21)1(

    YORK UNIVERSITY

    IEEE 754 FP Format (single precision)

    mes

    Sign

    0= +

    1= -

    8 bit

    True exponent=e-b

    Bias is 127

    23 bit

    Mantissa is normalized (MSB=1). There is an implied 1 to make it >1 and

  • 9YORK UNIVERSITY

    IEEE 754 FP Format SEEEEEEEEMMMMMMMMMMMMMMMMMMMMMMM If E=255 and M is nonzero, then V=NaN ("Not a number") If E=255 and M is zero and S is 1, then V=- If E=255 and M is zero and S is 0, then V= If 0

  • 10

    YORK UNIVERSITY

    IEEE 754 Double Precision

    64 bit number 1 bit for sign 11 bits for exponent 52 bits for mantissa Bias is 1023

    YORK UNIVERSITY

    FP Addition S0: Append the implied 1 of the mantissa S1: Shift the mantissa from S0 with smaller exponent es

    to the right by el es, where el is the larger of the two exponents

    S2: For negative operand take twos complement and then add the two mantissas. If the result is negative, again takes twos complement of the

    result for storing in IEEE format S3: Normalize the sum back to IEEE format by adjusting

    the mantissa and appropriately changing the value of the exponent el

    S4: Round or truncate the resultant mantissa to fit in IEEE format

  • 11

    YORK UNIVERSITY

    FP Addition -- Example

    Add these 2 numbers (e=4, m=5, bias=7)0_1010_00101 =2107 1.00101=1001.01=9.250_1001_00101 =297 1.00101=1.00101=4.625Align1.0010123=>1.0010123

    1.0010122 =>0.100101231.10111123 =1.734375 8=13.875

    InFPformat0_1010_10111 =2107 1.7185=13.75

    YORK UNIVERSITY

    FP Multiplication

    S0: Add the two exponents e1 and e2 and subtract the bias once

    S1: Multiply the mantissas as unsigned numbers to get the product, and XOR the two sign bits to get the sign of the product

    S2: Normalize the product if required S3: Round or truncate the mantissa

  • 12

    YORK UNIVERSITY

    Qn.m Format for Fixed-Point Arithmetic

    Qn.m format is a fixed positional number system for representing floating point numbers

    A Qn.m format binary number assumes n bits to the left and m bits to the right of the binary point

    . 2-82-72-62-52-42-32-22-120-21

    Fraction BitsFraction BitsSign Bit

    Q2.8 Format

    YORK UNIVERSITY

    Example. 2-82-72-62-52-42-32-22-120-21

    01 1101 0000

    1 + 1/21 + 1/22 + 1/24 = 1.8125

    The range of a Q2.8 is -2 (10_000_000) to

    +1.99609375 (01_1111_1111)

    In Qn.m n determines the range of the integer, while m determines the precision of the fractional part

  • 13

    YORK UNIVERSITY

    Fixed Point DSPs Commercially available off the shelf processors usually

    have16 bits to represent a number In C, a programmer can define 8, 16 or 32 bit numbers

    as char, short and int/long respectively In case a variable requires different precision than what

    can be defined in C, the number is defined in higher precision

    For example an 18-bit number should be defined as a 32-bits integer

    High precision arithmetic is performed using low precision arithmetic operations 32-bit addition requires two 16-bit addition 32-bit multiplication requires four 16-bit multiplications

    YORK UNIVERSITY

    FP to Fixed Point Comversion

    Start wit the algorithm (FP) Estimate the range Determine n The fractional part m requires detailed

    analysis of signal to quantization noise

  • 14

    YORK UNIVERSITY

    R&S

    Floating Point algorithm

    Range estimation

    SQNR analysis for optimal fractional part

    determination

    Fixed point algorithm

    HW-SW implementation

    Target system

    YORK UNIVERSITY

    Addition in Q Format

    Adding two numbers Qn1.m1 and Qn2.m2results in Qn.m where

    N=max(n1,n2)+1, m=max(m1,m2) Note that the decimal point does not exist

    in H/W, the designer must align the two number properly

  • 15

    YORK UNIVERSITY

    Multiplication in Q Format

    Unsigned by unsigned Straightforward shift and add, no sign

    extension in general Q(n1+n2).(m1+m2)1101=11.01inQ2.2=3.251011=10.11inQ2.2=2.75

    1 1 0 11 1 0 1

    0 0 0 01 1 0 1

    1 0 0 0 1 1 1 1 = 1000.1111 in Q4.4 format = 8.9375

    YORK UNIVERSITY

    Multiplication in Q Format

    Signed by Unsigned1101=11.01inQ2.2=0.75(signed)

    0101=01.01inQ2.2=1.25(unsigned1111 1101

    0000 000

    11 11010 0000

    111110001=1111.0001inQ4.4format=0.9375

    Sign extended number

  • 16

    YORK UNIVERSITY

    Multiplication in Q Format

    Signed by Unsigned1101=11.01inQ2.2=0.75(signed)

    1101=01.01inQ2.2=3.25(unsigned1111 1101

    0000 000

    11 11011 1101

    1011011001=1101.1001inQ4.4format=

    Take2scomplement0010.0111=2.4375

    YORK UNIVERSITY

    Multiplication in Q Format

    Unsigned by Signed1001=11.01inQ2.2=2.25(unsigned)

    1101=01.01inQ2.2=0.75(signed)0000 1001

    0000 000

    00 10011 0111

    11100101=1110.0101inQ4.4formattake2scomplementitbecome0001.1011=1.6875

    The 2s complement of the multiplicand 01001=10111

  • 17

    YORK UNIVERSITY

    Multiplication in Q Format

    Signed by Signed1101=11.01inQ2.2=0.75(signed)

    1101=1.101inQ1.3=0.375(signed)1111 1101

    0000 000

    11 11010 0011

    1000001001=00.01001inQ2.5format=0.28125

    Notethatthereisanextrasignbitsoweneed2.5not3.5format

    The 2s complement of 11.01 since we are multiplying it by the sign bit

    YORK UNIVERSITY


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