finite state machines - web02web02.gonzaga.edu/faculty/talarico/cp430/lec/fsm.pdf · ·...
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FiniteStateMachines
FSM
nextstatestate
GenericStateMachineModel
GuidelinesforcodingFSMsinVHDL:
*Useseparateprocessesforsequentiallogicandcombinationallogic
*Useenumerateddatatypetolistallpossiblestates
(optional)(state registers)
StateMachine:keyidea
• StatemachinesareaneffectivemathematicalMoC thatallowtocharacterizeinanun-ambiguousandformalwaythebehaviorofasystem
• Goal:givenasetofexternalstimuliwewanttodesignasystemthatexhibitadesiredbehavior,i.e.thesystemmustbeabletoprocessthestimuli providedatitsinputstoproducecertainactions atitsoutputs
SYSTEMinputs outputs
StateMachine:keyidea
STATE,ACTIONS
checkstimuli
IfnecessarychangeSTATEandACTIONS
SystemBehavior:
stimuli inputs
actions outputs
actionsdependsonstimuli&state
Insummary:1. atanygiventimeyouare
inacertainstate,andperformcertainactions
2. monitorexternalstimuliand“decide”whatnextstateandactionsshouldbe
MoorestyleFSM
NextstateC.L.
OutputC.L.
StateRegistersS.L.
clock reset(optional)
nextstate state outputsinputs
Theremaybeglitchesontheoutputs
MealystyleFSM
NextstateC.L.
OutputC.L.StateRegisters
S.L.
clock reset(optional)
nextstatestate outputs
inputs
Theremaybeglitchesontheoutputsandtheoutputsmaylastlessthanonecycle
RegisteredOutputsFSMs
PipelinedMealy
Noglitchesandtheoutputslastone cycle
NextstateC.L.
OutputC.L.StateRegisters
S.L.
clock reset(optional)
nextstatestateinputs
OutputRegistersS.L.
storedoutputs
RegisteredOutputsFSMs
NextstateC.L.
OutputC.L.
StateRegistersS.L.
clock reset(optional)
nextstate statestoredoutputsinputs
OutputRegistersS.L.
Noglitchesandtheoutputslastoneclockcycle
Ifwewant,wecandefinitelypipeline“Moore”…
Registered(a.k.a stored)outputsFSMs
NextstateC.L.
OutputCodedStateRegisters
clock reset(optional)
nextstatestate/outputs
inputs
Noglitches+outputsarefaster
Solution1:outputcodedMoore
Solution2:output“forecasting”
Usuallysolution2requireslessthinking
NOTE:withMooreFSMsispossibletogetregisteredoutputswithouthavingtoaddapipelinestageà outputsgetspeedupbyoneclockcycle!!!
DesignExample:EdgeDetector
EdgeDetector• Designastatemachinetoimplementanedgedetector
Intuitivesolution:
SYSTEMDIN
CLKPULSE
K.MapsforMoore’sFSM
K.MapsforMealy’s FSM
Moorewithregisteredoutput
Mux0~0
InthissimpleexampletheMoore’soutputregisteredFSMandthe“pipelined”MealyFSMhappentocoincides!
DesignExample:EdgeDetectorVHDLcoding
Mealy’s FSM
Moore’sFSM
Moore’sstoredoutputFSM
EdgeDetector:FunctionalSimulation
EdgeDetector:Testbench VHDLcode
Testbench
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