final report metro

7/31/2019 Final Report Metro

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Chapter-1

INTRODUCTION

1.1 Architecture

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of

Flash programmable and erasable read only memory (PEROM). The device is manufactured

using Atmels high-density nonvolatile memory technology and is Compatible with the industry-

standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to

be reprogrammed in-system or by a conventional Non - volatile memory programmer.

1.2 Pin Configuration

Fig. 1.1 8051 Pin Configuration

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM,

32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt architecture, a full duplex

serial port, on-chip oscillator and clock circuitry.


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PIN DESCRIPTION

VCC

Supply voltage.

GND

Ground

Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight

TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.

Port 0 may also be configured to be the multiplexed low order.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. Port 1 also receives the low-order address bytes during Flash

programming and verification.

Port 2


sink/source four TTL inputs. Port 2 emits the high-order address byte during fetches from

external program memory and during accesses to external data memories that use 16-bit

addresses (MOVX @ DPTR).

Port 3


sink/source four TTL inputs. Port 3 also receives some control signals for Flash programming

and verification.


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ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to

external memory. This pin is also the program pulse input (PROG) during Flash programming.

Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

RESET

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the

device.

PSEN

Program Store Enable is the read strobe to external program memory. When the AT89C51 is

executing code from external program memory, PSEN is activated twice.

EA/VPP

External Access Enable (EA) must be strapped to GND in order to enable the device to fetch

code from external program memory locations starting at 0000H up to FFFFH. It also receives

the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require

12-volt VPP.

XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating

circuit.

XTAL2: Output from the inverting oscillator amplifier.


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Chapter-2

AT89S51

2.1 Architecture Features

8-Bit CPU Optimized for Control Applications Extensive Boolean Processing Capabilities (Single-Bit Logic) On-Chip Flash Program Memory On-Chip Data RAM Bidirectional and Individually Addressable I/O Lines Multiple 16-Bit Timer/Counters Full Duplex UART Multiple Source/Vector/Priority Interrupt Structure On-Chip Clock Oscillator On-chip EEPROM (AT89S series) SPI Serial Bus Interface (AT89S Series)Block Diagram

Fig. 2.1 Block Diagram of AT89S51


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2.2 Memory Organization

Logical Separation of Program Data Memory

All Atmel Flash microcontrollers have separate address spaces for program and data memory.

The logical separation of program and data memory allows the data memory to be accessed by 8-

bit addresses, which can be more quickly stored and manipulated by 8- bit CPU. Nevertheless,

16-bit data memory addresses can also be generated through the DPTR register. There can be up

to 64K bytes of directly addressable program memory. Data memory occupies a separate address

space from program memory upto 64K bytes of external memory. The CPU generates read and

write signals, RD and WR, during external data memory accesses.

Program Memory

Fig. 2.2 Program memory

Program memory addresses are always 16 bits wide, even though the actual amount of program

memory used may be less than 64K bytes. External program execution sacrifices two of the 8-bit

ports, P0 and P2, to the function of addressing the program memory.


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Data Memory

The right half of the internal and external data memory spaces available on Atmels Flash

microcontrollers hardware configuration for accessing up to 2K bytes of external RAM. In this

case, the CPU executes from internal Flash. Port 0 serves as a multiplexed address/data bus tothe RAM, and 3 lines of Port 2 are used to page the RAM. The CPU generates RD and WR

signals as needed during external RAM accesses. You can assign up to 64K bytes of external

data memory.

Fig. 2.3 RAM Allocation in 8051

Internal data memory addresses are always 1 byte wide, which implies an address space of only

256 bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes.

Direct addresses higher than 7FH access one memory space and indirect addresses higher than

7FH access a different memory space. Thus, the Upper 128 and SFR space occupying the same

block of addresses, 80H through FFH, although they are physically separate entities. The lowest

32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as

R0 through R7. Two bits in the Program Status Word (PSW) select which register bank is in use.

This architecture allows more efficient use of code space, since register instructions are shorter

than instructions that use direct addressing.


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Fig. 2.4 Data Memory

Programming Status Word:

Fig. 2.5 Programming Status word


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The Instruction Set

All members of the Atmel microcontroller family execute the same instruction set. This

instruction set is optimized for 8- bit control applications and it provides a variety of fast

addressing modes for accessing the internal RAM to facilitate byte operations on small datastructures.

Fig. 2.6 8051 Instruction Set

Program Status Word

The Program Status Word (PSW) contains status bits that reflect the current state of the CPU.

The PSW, shown in Figure 11, resides in SFR space. The PSW contains the Carry bit, the

Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow flag, a

Parity bit, and two user-definable status flags. The Carry bit, in addition to serving as a Carry bit

in arithmetic operations, also serves as the Accumulator for a number of Boolean operations.

Fig 2.7 Program Status Word


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The bits RS0 and RS1 select one of the four register banks shown in Figure 8. A number

of instructions refer to these RAM locations as R0 through R7. The status of the RS0 and RS1

bits at execution time determines which of the four banks is selected. The Parity bit reflects the

number of 1s in the Accumulator: P=1 if the Accumulator contains an odd number of 1s, and

P=0 if the Accumulator contains an even number of 1s. Thus, the number of 1s in the

Accumulator plus P is always even. Two bits in the PSW are uncommitted and can be used as

general purpose status flags.


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Chapter-3

LCD (LIQUID CRYSTAL DISPLAY)

3.1 Liquid Crystal Display Fundamentals

Liquid Crystal Displays (LCDs) are categorized as none missive display devices, in that respect,

they do not produce any form of light like a Cathode Ray Tube (CRT). LCDs either pass or

block light that is reflected from an external light source or provided by a back/side lighting

system. There are two modes of operation for LCDs during the absence of an electric field

(applied Power); a mode describes the transmittance state of the liquid crystal elements. Normal

White mode: the display is white or clear and allows light to pass through and Normal Black

Mode: the display is dark and all light is diffused. Virtually all displays in production forPC/Workstation use are normal white mode to optimize contrast and speed.

Fig. 3.1 LCD Display

A simplified description of how a dot matrix LCD display works is as follows: A twisted nematic

(TN) LC display consists of two polarizer, two pieces of glass, some form of switching element

or electrode to define pixels, and driver Integrated Circuits (ICs) to address the rows and

columns of pixels. To define a pixel (or sub pixel element for a color display), a rectangle is

constructed out of Indium Tin Oxide -- a semi-transparent metal oxide (ITO) and charge is

applied to this area in order to change the orientation of the LC material ( change from a white

pixel to a dark pixel). The method utilized to form a pixel in passive and active matrix displays

differs and will be described in later sections. Figure 1 illustrates a cross sectional view of a


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simple TN LC display. Figure 2 depicts a dot matrix display as viewed without its metal

module/case exposing the IC drivers.

Viewer///////////////////////////////////// Polarizer

___________ __________________________ glass~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Liquid Crystal

_____________________________________ glass\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ Polarizer

Backlight

Fig. 3.2 Cross Section of a Simple LC Display

________________________________________| |

| IC IC | Source/Column ICs| | |

| | ||IC---------------------Pixel |

| ||IC


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will not twist and the display will not form an image. If the display is too warm, the resistance of

the liquid crystal material changes and this alters the properties of the display and performance

suffers. Liquid crystal material for display use is normally referred to as TN (STN, DSTN,

MSTN, and etc.) or Twisted Nematic--sometimes known as TNFE or Twisted Nematic Field

Effect. It is called TWISTED since the crystals are twisted 90 degrees (or more for STN) from

the top piece of glass to the bottom piece of glass. (TN usually refers only to a 90 degree twist.)

Field Effect (a direct correlation is the semiconductor MOSFET), refers to the LC material's

ability to align parallel or perpendicular to an applied electric field.

3.3 Liquid Crystal Alignment

Liquid crystals must be aligned to the top and bottom pieces of glass in order to obtain the

desired twist. In other words, the 90 degree twist is formed by anchoring the liquid crystal on one

glass plate and forcing it to twist across the cell gap (the distance between the two glass plates)

when contacting the second plate. Furthermore, The actual image quality of the display will be

dependent on the surface alignment of the LC material. The method currently used for aligning

liquid crystals was developed by the Dai-Nippon Screening (English= Big Japan Screening)

Company. The process consists of coating the top and bottom sheets of glass with a Polyimide

based film. The top piece of glass is coated and rubbed in a particular orientation; the bottom

panel/polyimide is rubbed perpendicular (90 degrees for TN displays) with respect to the top

panel. It was discovered that by rubbing the polyimide with a cloth, nanometer (1 X 10 - 9

meters) size grooves are formed and the liquid crystals align with the direction of the grooves. It

is common that when assembling a TN LC cell, it will be necessary to eliminate patches of non

uniform areas. The two parameters required to eliminate the non uniformities and complete the

TN LC display are pre tilt angle and cholesteric impurities. TN LC cells commonly have two

problems that affect uniformity following assembly: reverse tilt and reverse twist. Reverse tilt is

a function of the applied electrical field and reverse twist is common when no electrical field isapplied. Reverse twist is eliminated by the introduction of cholesteric additives and reverse tilt is

eliminated by introducing a pre-tilt angle to the LC material.


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3.4 LCD Codes

Fig. 3.4 LCD Command Codes


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Chapter-4

STEPPER MOTOR FUNDAMENTALS

4.1 Introduction

Stepper motors are commonly used in accurate motion control. They allow controlling any

motion with high precision by counting the number of steps applied to the motor. Most of

systems controlling stepper motors are embedded systems such as printer, scanner or floppy disk

drive. This application note describes how to drive a uni-polar stepper motor with the

Programmable Counter Array of an Atmel C51/C251 microcontroller. There are two major types

of stepper motors: Permanent magnet stepper motors (un-polar stepper motors and bipolar

stepper motors) and variable reluctance stepper motors (hybrid stepper motors).

4.2 Identification of Stepper Motor

There are several types of stepper motors; these cannot be driven in the same way. In this

application note, we have chosen to drive a uni-polar stepper motor For more information you

will find schemes to identify the other types of stepper motors. Uni-polar Stepper Motor Uni-

polar stepper motors are characterized by their center-tapped windings.

Fig. 4.1 Uni-polar Stepper Motor

Bipolar Stepper Motor Bipolar stepper motors are designed with separate coils.

Fig. 4.2 Bipolar Stepper Motor


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Variable Reluctance Variable reluctance stepper motor (also called hybrid motors) are

characterized by one common lead.

Fig. 4.2Variable Reluctance Stepper Motor

Driving Uni-polar Stepper Motors

There are three ways to drive uni-polar stepper motors (one phase on, two phases on or half

step); each one has some advantages and disadvantages.

Table 4.1 One Phase Sequence

There are two stages to sorting out which wire is which in a 5- or 6-wire uni-polar stepper motor:

1. Isolate the Common Power wire(s) by using an ohmmeter to check the resistancesbetween pairs of wires. The Common Power wire will be the one with only half as much

resistance between it and all the others. This is because the Common Power wire only has

one coil between it and each other wire, whereas each of the other wires have two coils

between them. Hence half the resistance.


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2. Identify the wires to the coils by supplying a voltage on the Common Power wire(s) andkeeping one of the other wires grounded while grounding each of the remaining three

wires in turn and observing the results. Select one wire and ground it Assume it's

connected to coil 4. Keeping it grounded, ground each of the other three wires one by one

Grounding one wire should make the rotor turn a little clockwise. That'll be the wire

connected to Coil 3. Grounding one wire should make the rotor turn a little anticlockwise.

That'll be the wire connected to Coil 1. Grounding one wire should do nothing That'll be

the wire connected to Coil 2.

Fig. 4.3 Stepper Motor Driver IC ULN2003

Features

Output current (single output) 500ma MAX. High sustaining voltage output

50V MIN. (ULN2003AP/AFW Series)

Output clamp diodes Input compatible with various types of logic Package Type-AP : DIP-16pin Package Type-AFW : SOL-16pin

The ULN2003AP / AFW Series are high-voltage, high-current darlington drivers comprised ofseven NPN darlington pairs.

All unit feature integral clamp diodes for switching inductive loads.

Applications include relay, hammer, lamp and display (LED) drivers.


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Pin Connection:

Fig. 4.4 Pin Connections

Table 4.2 Rating of IC


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Test Circuit

Fig. 4.5 Tasting the IC Circuit

Precautions for Using

Utmost care us necessary in the design of the output line, COMMON and GND line since IC

may be destroyed due to short-circuit between outputs, air contamination fault, or fault by

improper grounding.


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4.3 Voltage Regulator IC (Electrical Characteristics of MC7805)

The MC78XX/LM78XX/MC78XXA series of three terminal positive regulators are available in

the TO-220/D-PAK package and with several fixed output voltages, making them useful in a

wide range of applications. Each type employs internal current limiting, thermal shut down and

safe operating area protection, making it essentially indestructible. If adequate heat sinking is

provided, they can deliver over 1A output current. Although designed primarily as fixed voltage

regulators, these devices can be used with external components to obtain adjustable voltages and

currents.

Features

Output Current up to 1A

Output Voltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V

Thermal Overload Protection

Short Circuit Protection

Output TransistorSafe Operating Area Protection

Fig. 4.6 Pin Diagram of the Power IC


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Internal Block Diagram

Fig. 4.7 Internal block diagram of MC7805

Table 4.3 Absolute Maximum Rating


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Typical Applications

Fig. 4.8 Constant Current Regulator

Notes:

(1) To specify an output voltage. Substitute voltage value for "XX." A common ground is

required between the input and the Output voltage. The input voltage must remain typically 2.0V

above the output voltage even during the low point on the input ripple voltage.

(2) CI is required if regulator is located an appreciable distance from power Supply filter.

(3) CO improves stability and transient response.


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Chapter-5

SHCEMATIC DIAGRAM

Fig. 5.1 8051 MC


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PCB Diagram

Fig. 5.2 PCB Layout


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Chapter-6

PROGRAM in Assembly

Program for a stepper having connected at p2 (form p2.0; to p2.3) & to show message on

the LCD$mod51

dat equ p1

busy equ p1.7

rs equ p3.5

rw equ p3.4

en equ p3.3

bzr equ p0.2

ledf equ p0.0

ledb equ p0.1

org 0000h

ajmp main

org 0003h

test: mov c,p3.2

jnc halt

setb bzr

reti

halt:


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clr bzr ;till zero blow on the bzr

ajmp test

main:

mov ie,#00h

setb ea

;setb ex0

here:

mov p2,#00h

acall ini

mov dptr,#show0

acall read

clr ledf ;p1.0

acall delay

mov a,#01h

acall command; Now make memory clear cursor home

mov dptr,#show1

acall read

setb ex0 ;#############

mov a,#0c0h

acall command

mov dptr,#show3


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acall read

acall delay ;Stopage1 time 3 sec rookee

acall delay

clr bzr

acall delay

mov a,#01h

acall command

mov dptr,#show2

acall read

mov a,#0c0h

acall command

mov dptr,#show4

acall read

setb bzr

acall delay10

acall stepperf

mov a,#01h

acall command

mov dptr,#show1

acall read

mov a,#0c0h


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acall command

mov dptr,#show4

acall read

acall delay ;Stopage2 time 3 sec shsar

acall delay

clr bzr

acall delay

mov a,#01h

acall command

mov dptr,#show2 ;display ne

acall read

mov a,#0c0h

acall command

mov dptr,#show5

acall read

setb bzr

acall delay10

acall stepperf

mov a,#01h

acall command

mov dptr,#show1


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acall read

mov a,#0c0h

acall command

mov dptr,#show5

acall read

acall delay ;Stopage2 time 3 sec Meerut

acall delay

clr bzr

acall delay

setb ledf ; p1.0 ;off led at p1.0 for forward journey

clr ledb ; p1.1 ; 0n Led for back ward journey

mov a,#01h

acall command

mov dptr,#show2 ;display ne shar

acall read

mov a,#0c0h

acall command

mov dptr,#show4

acall read

setb bzr

acall delay10


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acall stepperb

mov a,#01h

acall command

mov dptr,#show1

acall read

mov a,#0c0h

acall command

mov dptr,#show4

acall read

acall delay ;Stopage2 time 3 sec shsar

acall delay

clr bzr

acall delay

mov a,#01h

acall command

mov dptr,#show2 ;display ne roor

acall read

mov a,#0c0h

acall command

mov dptr,#show3

acall read


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setb bzr

acall delay10

acall stepperb

mov a,#01h

acall command

mov dptr,#show1

acall read

mov a,#0c0h

acall command

mov dptr,#show3

acall read

setb ledb ;p1.1

ljmp here

;routine for stepper motor

; Delay Routine

;one sec delay

delay:

push acc

push 00h


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push 01h

push p0

push p1

mov r0,#0eh

loopr:

mov a,#0ffh

loopb:

mov b,#0ffh

loopa: djnz b,loopa

djnz 0e0h,loopb

djnz r0,loopr

pop p1

pop p0

pop 01h

pop 00h

pop acc

ret

;dlay stepper

delays:

push acc

push 00h

push 01h


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push p0

push p1

mov a,#0ffh

loopa1:

mov b,#0fh

loopb1:

djnz b,loopb1

djnz 0e0h,loopa1

pop p1

pop p0

pop 01h

pop 00h

pop acc

ret

delay10:

mov tmod,#01h

mov tcon,#00h

mov tl0,#0f0h

mov th0,#0f8h


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setb tr0

no: jnb tf0,no

clr tr0

clr tf0

ret

;=============== Routine to read data from prog mem

read:

nex: clr a

movc a,@a+dptr

cjne a,#'0',aga

sjmp down

aga: acall display

inc dptr

sjmp nex

down:

ret

;================ stepper routine

stepperf:

push acc

push p1

mov a,#88h


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mov r1,#04h

loop1:

mov r0,#0e0h

loop: mov p2,a

acall delays

rr a

djnz r0,loop

djnz r1,loop1

pop p1

pop acc

ret

stepperb:

push acc

push p1

mov a,#88h

mov r1,#04h

loop12:

mov r0,#0e0h

loop0: mov p2,a

acall delays

rl a

djnz r0,loop0


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djnz r1,loop12

pop p1

pop acc

ret

;*******************************************************

;LCD strobe subroutines

ini:

mov a,#38h

acall command

mov a,#38h

acall command

mov a,#38h

acall command

mov a,#38h

acall command

mov a,#0eh

acall command

mov a,#06h

acall command

mov a,#01h

acall command


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mov a,#80h

acall command

ret

command:

acall ready

mov dat,a

clr rs

clr rw

setb en

clr en

ret

display:

acall ready

mov dat,a

setb rs

clr rw

setb en

clr en

ret

ready:


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clr en

mov dat,#0ffh

clr rs

setb rw

wait: clr en

setb en

jb busy,wait

clr en

ret

show0: db 'Welcome To All','0'

show1: db 'CURRENT STATION','0'

show2: db 'NEXT STATION','0'

show3: db 'ROORKEE','0'

show4: db 'MEERUT','0'

Show5: db 'DELHI','0'

end


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Chapter-7

Components List for Project

AT89c51 1

ULN2003 1

Stepper Motor 1

2 Line LCD 1

Buzzer 1

LED 3

Resistances (10K) 5

4.7K 5

470 ohm 5

33picofarad Ceramic Disk Capacitor 2

Crystal Osci. (12 MHz) 1

Mini Switch 2

10K Pot (Preset) 1

Diode 1n4007 4

IC Base (16Pin, 40Pin, 8Pin) 1 each

Relimate (5 pin and 2 pin) 1 each

Relimate (16pin) 2

Power chord 1

Capacitor 100Microfarad/ 25v 1

Capacitor 470 Microfarad / 25v 1

Power IC 7805 1

Transformer (9-0-9) 1


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CONCLUSION

The project gives prototype for driver less type of metro trains using microcontroller 89C51 as

CPU. The motion of the train is controlled by the Stepper Motor, for displaying message in the

train we are using Intelligent LCD Display of two lines. The Stoppage time is of 3 sec and time

between two consecutive stations is 6 sec. There is a LCD display for showing various messages

in the train for passengers. There are indicators, which are used to show the train direction.

Before stopping at station the train blows the buzzer. It also includes an emergency brake system

due to which the train stops as soon as the brakes are applied and resumes journey when theemergency situation is over.


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REFERENCE

1. The 8051 Microcontroller and Embedded Systems Using Assembly and C-2nd-ed BYMazidi

2. The 8085 microprocessor by Goankar3. http://www.atmel.com4. http://www.wikipedia.com5. http://www.google.com6. http://www.ibibo.com7. http://www.iste.com
http://www.wikipedia.com/http://www.wikipedia.com/http://www.wikipedia.com/http://www.google.com/http://www.google.com/http://www.google.com/http://www.ibibo.com/http://www.ibibo.com/http://www.ibibo.com/http://www.iste.com/http://www.iste.com/http://www.iste.com/http://www.iste.com/http://www.ibibo.com/http://www.google.com/http://www.wikipedia.com/


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APPENDIX

INSTRUCTION SETS


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final report metro

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