figure 9.1. a block diagram of a microwave oven
DESCRIPTION
Figure 9.1. A block diagram of a microwave oven. Figure 9.2. A simplified block diagram of a digital camera. Please see “ portrait orientation ” PowerPoint file for Chapter 7. Figure 9.6. Parallel interface registers. Figure 9.7. Receive and transmit structure of the serial interface. - PowerPoint PPT PresentationTRANSCRIPT
ROMProcessor
Inputinterface
Input keys Door open
Bus
Outputinterface
Magnetron Fan
Displays Light
Speaker
RAM
Figure 9.1. A block diagram of a microwave oven.
EMBEDDED PR OCESSOR CHIP
Figure 9.1. A block diagram of a microwave oven
Userswitches
Computerinterface
Imagestorage
LCDscreen
Flashunit
A/Dconversion
Opticalsensors
Systemcontroller
Motor
Lens
Figure 9.2. A simplified block diagram of a digital camera.
Cable to PC
Figure 9.2. A simplified block diagram of a digital camera.
Parallel
I/O ports
Serial
I/O ports
Counter/Timer
Processor
core
Internal
memory
To external
memory
Figure 9.3. A block diagram of an embedded processor.
A-to-D conversion D-to-A conversion
Parallel I/O
Serial I/O
Counter/Timer
Processorcore
Internalmemory
Figure 9.4. An example microcontroller.
Address
Data
Control
Port A
Port B
Receive data
Transmit data
Counter_in
Timer_out
D Q
QWrite_Port
D Q
Q
Output data
Di PAi
Data direction
Write_DIR
Read_Port
Figure 9.5. Access to one bit in Port A in Figure 9.4.
Please see “portrait orientation” PowerPoint file for Chapter 7
Figure 9.6. Parallel interface registers.
Figure 9.7. Receive and transmit structure of the serial interface.
D7
D0
Serial outputTransmit shift register
Transmit buffer
Receive shift register Serial input
Receive buffer
Figure 9.7. Receive and transmit structure of the serial interface.
Figure 9.8. Serial interface registers.
Address
FFFFFFE2
FFFFFFE0
FFFFFFE1
Status register (SSTAT)
Receive buffer
Transmit buffer
12 034567
FFFFFFE3 Control register (SCONT)
RBUF
TBUF
1 : Receiver full
1 : Transmitter empty
1 : Error detected
1 : Transmitter interrupt
1 : Receiver interrupt
0 : System clock
1 : Error interrupt
1 : Enable transmitter interrupt
1 : Enable receiver interrupt
1 : Enable error interrupt
1 : Divide clock
031
DIV (Divisor register)FFFFFFE4
Figure 9.9. Counter/Timer registers.
Address
FFFFFFD8 Control register (CTCON)
12 034567
FFFFFFD9 Status register (CTSTAT)
1 : Start
1 : Stop1 : Timer
1 : Enable interrupt
0 : Counter
1 : Counter reached 0
031
CNTM (Initial value)FFFFFFD0
COUNT (Counter contents)FFFFFFD4
RBUF EQU $FFFFFFE0 Receivebuffer.SSTAT EQU $FFFFFFE2 Statusregisterforserial interface.PAOUT EQU $FFFFFFF1 Port Aoutputdata.PADIR EQU $FFFFFFF2 Port Adirectionregister.
*InitializationORIGIN $1000MoveByte #$FF,PADIR ConfigurePort A asoutput.
* TransferthecharactersLOOP Testbit #0,SSTAT Check ifnewcharacterisready.
Branch=0 LOOPMoveByte RBUF,PAOUT Transfera characterto Port A.Branch LOOP
Figure 9.10. A generic assembly language program for character transfer using polling.
/* Defineregisteraddresses*/#defineRBUF (volatilechar*)0xFFFFFFE0#defineSSTAT (volatilechar*)0xFFFFFFE2#definePAOUT (char*) 0xFFFFFFF1#definePADIR (char*)0xFFFFFFF2
void main(){
/* Initializetheparallelport */*PADIR = 0xFF; /* ConfigurePort A asoutput */
/* Transferthecharacters */while(1){ /* Infinite loop*/
while((*SSTAT &0x1)= =0); /* Wait for anewcharacter */*PAOUT = *RBUF; /* Move thecharacterto Port A */
}}
Figure 9.11. C program for character transfer using polling.
/* Defineregisteraddresses*/volatilechar *RBUF = (char*)0xFFFFFFE0;volatilechar *SSTAT = (char*)0xFFFFFFE2;char *PAOUT = (char*)0xFFFFFFF1;char *PADIR = (char*)0xFFFFFFF2;
void main(){
/* Initializetheparallelport */*PADIR =0xFF; /* ConfigurePort A asoutput */
/* Transferthecharacters*/while(1){ /* Infinite loop */
while((*SSTAT &0x1)= =0); /* Wait fora newcharacter */*PAOUT = *RBUF; /* Move thecharacterto Port A */
}}
Figure 9.12. An alternative C program for character transfer using polling.
Move PADIR,R0MoveByte #$FF,(R0)
LOOP Move SSTAT,R0Testbit #0,(R0)
Branch=0 LOOPMove RBUF,R0Move PAOUT,R1Move (R0),(R1)
Branch LOOP
Figure 9.13. Possible compiled code for the program segment in Figure 9.12.
RBUF EQU $FFFFFFE0 Receivebuffer.SCONT EQU $FFFFFFE3 Control registerforserialinterface.PAOUT EQU $FFFFFFF1 Port Aoutputdata.PADIR EQU $FFFFFFF2 Port Adirectionregister.
* InitializationORIGIN $1000MoveByte #$FF,PADIR ConfigurePort A asoutput.Move #INTSERV,$24 Settheinterruptvector.Move #$40,PSR Processorresponds to IRQ interrupts.MoveByte #$10,SCONT Enablereceiver interrupts.
* TransferloopLOOP Branch LOOP Infinitewait loop.
* Interrupt serviceroutineINTSERV MoveByte RBUF,PAOUT Transferacharacterto Port A.
ReturnI Returnfrom interrupt.
Figure 9.14. A generic assembly language program for character transfer using interrupts.
#defineRBU (volatilechar *)0xFFFFFFE0#definePAOUT (char *) 0xFFFFFFF1
.
.
.
void main(){
.
.
.}
void intserv(){
*PAOUT = *RBUF; /* Move a characterto Port A */}
Figure 9.15. A function call in a C program.
Please see “portrait orientation” PowerPoint file for Chapter 7
Figure 9.16. C program for character transfer using interrupts.
Please see “portrait orientation” PowerPoint file for Chapter 7
Figure 9.17. C program for transfer through a circular buffer.
Please see “portrait orientation” PowerPoint file for Chapter 7
Figure 9.18. A generic assembly language program for transfer through a circular buffer.
BCD-to-7-segmentdecoder
BCD-to-7-segmentdecoder
BCD-to-7-segmentdecoder
PB1PB7-4 PB2 PB0PA3-0PA7-4
VDD VDDVDD
LED
Go
Stop
Processor core
Memory
Counter / Timer
Microcontroller
Figure 9.19. The reaction-timer circuit.
Please see “portrait orientation” PowerPoint file for Chapter 7
Page 1 of Figure 9.20. C program for the reaction timer.
Please see “portrait orientation” PowerPoint file for Chapter 7
Page 2 of Figure 9.20. C program for the reaction timer.
Please see “portrait orientation” PowerPoint file for Chapter 7
Page 1 of Figure 9.21. Assembly language program for the reaction timer using polling.
Please see “portrait orientation” PowerPoint file for Chapter 7
Page 2 of Figure 9.21. Assembly language program for the reaction timer using polling.
a
b
c
d
e
f
g
BCD
to
7-segment
decoder
BCDdigit
Figure P9.1. A 7-segment display with a BCD decoder.
a
b
c
d
e
f g
a
b
c
d
e
f
g
Figure P9.2. A 7-segment display with a register.
Sa
Sb
Sc
Sd
Se
Sf
Sg
a
b
c
d
e
f g
Load
Register