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Fig. 5.3 Transistor circuit under examination in this introductory discussion. Robert L. Boylestad Electronic Devices and Circuit Theory, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

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Page 1: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.3 Transistor circuit under examination in this introductory discussion.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 2: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.4 The network of Fig. 5.3 following removal of the dc supply and insertion of the short-circuit equivalent for the capacitors.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 3: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.5 Circuit of Fig. 5.4 redrawn for small-signal ac analysis.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 4: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.6 (a) Common-base BJT transistor; (b) re model for the configuration of (a).

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 5: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.7 Common-base re equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 6: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.8 Defining Zo.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 7: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.9 Defining Av = Vo/Vi for the common-base configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 8: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.10 Approximate model for a common-base npn transistor configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 9: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.11 (a) Common-emitter BJT transistor; (b) approximate model for the configuration of (a).

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 10: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.12 Determining Zi using the approximate model.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 11: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.13 Effect of re on input impedance.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 12: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.14 Defining ro for the common-emitter configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 13: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.15 Including ro in the transistor equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 14: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.16 Determining the voltage and current gain for the common-emitter transistor amplifier.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 15: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.17 re model for the common-emitter transistor configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 16: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.19 Two-port system.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 17: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.20 Hybrid input equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 18: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.21 Hybrid output equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 19: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.22 Complete hybrid equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 20: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.23 Common-emitter configuration: (a) graphical symbol; (b) hybrid equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 21: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.24 Common-base configuration: (a) graphical symbol; (b) hybrid equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 22: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.25 Effect of removing hre and hoe from the hybird equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 23: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.26 Approximate hybrid equivalent model.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 24: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.27 Hybrid versus re model: (a) common-emitter configuration; (b) common-base configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 25: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.28 Common-emitter hybrid equivalent circuit for the parameters of Example 5.3.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 26: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.29 Common-base re model for the parameters of Example 5.3.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 27: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.30 Giacoletto (or hybrid ) high-frequency transistor small-signal ac equivalent circuit.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 28: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.34 Common-emitter fixed-bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 29: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.35 Network of Fig. 5.34 following the removal of the effects of VCC, C1 and C2.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 30: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.36 Substituting the re model into the network of Fig. 5.35.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 31: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.37 Determining Zo for the network of Fig. 5.36.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 32: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.38 Demonstrating the 180° phase shift between input and output waveforms.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Page 33: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.39 Example 5.4.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

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Fig. 5.40 Voltage-divider bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 35: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.41 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.40.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

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Fig. 5.42 Example 5.5.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.43 CE emitter-bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 38: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.44 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.43.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Page 39: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.45 Defining the input impedance of a transistor with an un-bypassed emitter resistor.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Page 40: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.46 Example 5.6.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Page 41: Fig. 5.3 Transistor circuit under examination in this ...site.iugaza.edu.ps/jroumy/files/chapter-5-small-signla-analysis-of-BJT.pdfTitle: Fig. 5.1 Steady current established by a dc

Fig. 5.48 Example 5.3.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.49 The ac equivalent circuit of Fig. 5.48.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.50 An emitter-bias configuration with a portion of the emitter-bias resistance bypassed in the ac domain.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.51 Emitter-follower configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.52 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.51.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.53 Defining the output impedance for the emitter-follower configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.54 Example 5.10.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.55 Emitter-follower configuration with a voltage-divider biasing arrangement.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.56 Emitter-follower configuration with a collector resistor RC.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.57 Common-base configuration.

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Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

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Fig. 5.58 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.57.

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Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

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Fig. 5.59 Example 5.11.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.60 Collector feedback configuration.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.61 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.60.

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Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

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Fig. 5.62 Defining Zo for the collector feedback configuration.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.63 Example 5.12.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.64 Collector feedback configuration with an emitter resistor RE.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.65 Collector dc feedback configuration.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.66 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.65.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.67 Example 5.13.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.68 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.67.

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Electronic Devices and Circuit Theory, 9e

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Fig. 5.69 Determining the current gain using the voltage gain.

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Fig. 5.70 Amplifier configurations: (a) unloaded; (b) loaded; (c) loaded with a source resistance.

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Fig. 5.71 The ac equivalent network for the network of Fig. 5.70c.

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Fig. 5.72 Voltage-divider bias configuration with Rs and RL.

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Fig. 5.73 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.72.

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Fig. 5.74 Emitter-follower configuration with Rs and RL.

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Fig. 5.75 Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.74

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Fig. 5.76 Two-port system.

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Fig. 5.77 Substituting the internal elements for the two-port system of Fig. 5.76.

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Fig. 5.79 Applying a load to the two-port system of Fig. 5.77.

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Fig. 5.80 Including the effects of the source resistance Rs.

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Fig. 5.81 Considering the effects of Rs and RL on the gain of an amplifier.

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Fig. 5.82 Amplifier for Example 5.16.

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Fig. 5.110 Approximate common-emitter hybrid equivalent circuit.

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Fig. 5.111 Approximate common-base hybrid equivalent circuit.

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Fig. 5.112 Fixed-bias configuration.

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Fig. 5.113 Substituting the approximate hybrid equivalent circuit into the ac equivalent network of Fig. 5.112.

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Fig. 5.114 Example 5.31.

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Fig. 5.115 Voltage-divider bias configuration.

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Fig. 5.116 CE unbypassed emitter-bias configuration.

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Fig. 5.117 Emitter-follower configuration.

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Fig. 5.118 Defining Zo for the emitter-follower configuration.

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Fig. 5.119 Common-base configuration.

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Fig. 5.120 Substituting the approximate hybrid equivalent circuit into the ac equivalent network of Fig. 5.119.

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Fig. 5.121 Example 5.32.

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Fig. 5.122 Two-port system.

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Fig. 5.123 Substituting the complete hybrid equivalent circuit into the two-port system of Fig. 5.122.

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Fig. 5.124 Example 5.33.

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Fig. 5.125 Substituting the complete hybrid equivalent circuit into the ac equivalent network of Fig. 5.124.

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Fig. 5.126 Replacing the input section of Fig. 5.125 with a Thévenin equivalent circuit.

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Fig. 5.127 Example 5.34.

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Fig. 5.128 Small-signal equivalent for the network of Fig. 5.127.

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