field-plate assisted resurf power gradient based optimization, · field-plate assistedresurfpower...
TRANSCRIPT
Field-plate assisted RESURF powerdevices:
Gradient based optimization,degradation and analysis
Boni K. Boksteen
Members of the dissertation committee:
prof. dr. P.M.G. Apers University of Twente (chairman and secretary)prof. dr. J. Schmitz University of Twente (promotor)
dr. ir. R.J.E. Hueting University of Twente (co-promotor)prof. dr. ir. A.J. Mouthaan University of Twenteprof. dr. ir. W.G. van der Wiel University of Twente
prof. dr. P.G. Steeneken Delft University of Technology / NXP Semiconductorsprof. dr. B. Bakeroot Ghent University / IMEC
dr. ir. J.J. Koning Eindhoven University of Technologydr. G.E.J. Koops ON Semiconductor
This work is part of the Dutch Point-One program andis supported financially by Agentschap NL, an agency ofthe Dutch Ministry of Economic Affairs.
MESA+ Institute for Nanotechnology,University of TwenteP.O.Box 217, 7500 AE Enschede, the Netherlands
Copyright c© 2015 by Boni K. Boksteen, Enschede, The Netherlands.
This work is licensed under the Creative Commons Attribution-Non-Commercial 3.0 Netherlands License. To view a copy of this license, visithttp://creativecommons.org/licenses/by-nc/3.0/nl/ or send a letter toCreative Commons, 171 Second Street, Suite 300, San Francisco, California94105, USA.
Typeset with LATEX.Printed by Gildeprint Drukkerijen, Enschede, The Netherlands.
ISBN 978-90-365-3931-9DOI 10.3990/1.9789036539319
http://dx.doi.org/10.3990/1.9789036539319
FIELD-PLATE ASSISTED RESURF POWER
DEVICES:
GRADIENT BASED OPTIMIZATION,DEGRADATION AND ANALYSIS
PROEFSCHRIFT
ter verkrijging vande graad van doctor aan de Universiteit Twente,
op gezag van de rector magnificus,prof. dr. H. Brinksma,
volgens besluit van het College voor Promotiesin het openbaar te verdedigen
op woensdag 26 augustus 2015 om 12.45 uur
door
Boni Kofi Boksteen
geboren op 15 augustus 1986te Paramaribo, Suriname
Dit proefschrift is goedgekeurd door:
prof. dr. J. Schmitz (promotor)dr. ir. R.J.E. Hueting (co-promotor)
To my Parentsand in memory of my Grandfather
ABSTRACT
Compact fluorescent and solid-state lights rapidly gain ground in the light-ing market. Developments in the size, efficiency and reliability of theselight sources are accompanied by advancements in the embedded elec-tronics driving them. The long lifetime of these light sources requires thatthe electronics parts last at least equally long. The power transistor, atransistor specially designed to withstand high voltages or currents, is akey component in these and many other (e.g. automotive) electronics.
This PhD-work focuses on the development of optimization method-ologies for these power transistors and studies how long-term electricalstress affects their performance. The developed (gradient based) optimizeddevice designs result in smaller and therefore less expensive transistorswith an almost constant internal electric field (Reduced SURface Field -RESURF) having many unique features useful for modeling and the pre-diction of electrical behavior. During electrical stress however, parasiticcharge can build up in certain locations, thus distorting the electric fielddistribution which in turn leads to changing (potentially destructive) tran-sistor performance.
The main mechanisms responsible for degradation in these transistorsunder different stress conditions are identified, as well as the location inthe transistor where the stress induced physical and chemical changes takeplace. Diagnostic techniques and analytical models were subsequentlydeveloped to allow the prediction of the transistor’s performance afterstress. As such, this work provides the necessary insights and tools for thedesign and in depth electrical characterization of gradient based field-plateassisted RESURF optimized power transistors before and after electricalstress.
Overview
Each chapter in this work is based on, and expands upon, published workperformed throughout my PhD track.
vii
viii
AB
STR
AC
T
Chapter 1: General introduction based on: ’An initial study on the relia-bility of power semiconductor devices’ a literature study performed in 2010 atthe start of this research path [1]. This chapter provides the basic under-standing of the figures of merit used to qualify power devices, the differentissues facing their design, the basis of RESURF optimization and overallreliability concerns.
Chapter 2: Gradient based field-plate (FP) assisted REduced SURfaceField (RESURF) device design based on: ’Design optimization of field-plateassisted RESURF devices’ published in 2013 as part of the 25th ISPSD pro-ceedings, Kanazawa Japan [2]. This chapter provides design rules on howto optimize the electric field distribution for different types of dielectricbased RESURF while also focusing on reducing the specific on resistance.
Chapter 3: Field changes and degradation due to interface charge inFP assisted RESURF devices based on: ’Impact of interface charge on the elec-trostatics of field-plate assisted RESURF Devices’ published in 2014 in IEEETransactions on Electron Devices (TED) [3]. This chapter treats the theoryand provides application guidelines required to model the electrostatic in-fluence of interface charge degradation caused by arbitrary charge profiles.
Chapter 4: Extraction of the electric field and interface charge pro-files based on: ’Extraction of the electric field in field plate assisted RESURFdevices’ published in 2012 as part of the 24th ISPSD proceedings, Bruges,Belgium [4], and ’Electric field and interface charge extraction in field-plateassisted RESURF devices’ published in 2015 in TED [5]. This chapter focuseson subthreshold impact ionization in gradient based FP assisted RESURFdevices, how it can be used to extract lateral fields, their changes and theinterface charge distributions causing them.
Chapter 5: Off-state leakage behavior in gradient based FP assistedRESURF power devices based on: ’On the degradation of field-plate assistedRESURF power devices’ published in 2012 as part of the IEDM proceedings,San Francisco, CA, USA [6]. This chapter focuses on extracting and model-ing the leakage generation components, how they degrade and how theyare affected by the temperature.
Chapter 6: Measurement results and their analysis based partly on:’On the degradation of field-plate assisted RESURF power devices’ published in2012 as part of the IEDM proceedings, San Francisco, CA, USA [6]. Thischapter focuses on the obtained measurement results and their analysisusing the developed methods described in previous chapters.
Chapter 7: This chapter provides a summary of the most importantconclusions, recommendations and an outlook on future work.
ix
AB
STR
AC
T
Ordering the above chapters chronologically ([1],[4],[6],[2],[3],[5]) showsa path typical in research of any kind, namely the quest to explain obtained(measurement) results and all the different tangential paths those can leadto. This work, by arranging the myriad of obtained insights in a coherentstory line, provides a guide for those who are interested in:
Field-plate assisted RESURF power devices, their gradient basedoptimization, degradation and analysis.
SAMENVATTING
Compacte fluorescente en licht-emitterende diode (LED) lampen hebbeneen steeds groter marktaandeel in de lichtindustrie. De snelle ontwik-kelingen met betrekking tot grootte, efficiëntie en betrouwbaarheid vandeze lichtbronnen gaan hand in hand met de ontwikkelingen van de in-gebouwde sturingselektronica. Voor de lange levensduur van deze licht-bronnen is het daarom essentieel dat hun sturingselektronica minstenszo robuust is. Transistors specifiek ontworpen om hoge spanningen ofstromen te kunnen weerstaan (zogenaamde vermogenstransistors) vormeneen belangrijk deel van de verlichtingselektronica.
Dit doctoraalonderzoek focusseert zich op het ontwikkelen van op-timalisatiemethodes voor deze vermogenstransistors en bestudeert hoelangdurige elektrische stress de werking daarvan beïnvloedt. De (op gra-diënten gebaseerde) geoptimaliseerde transistorontwerpen resulteren inkleinere en daardoor goedkopere transistors met een bijna constant internelektrisch veld (Reduced SURface Field, RESURF) en vele unieke eigen-schappen, nuttig voor het modelleren en voorspellen van het elektrischgedrag. Echter, door elektrische stress kan er parasitaire lading op bepaaldelocaties in de transistor opgebouwd worden die het interne elektrische veldbeïnvloedt, wat vervolgens leidt tot een ander (en mogelijk destructief)transistorgedrag.
De belangrijkste mechanismen die degradatie onder verschillende stress-condities in de transistors teweegbrengen zijn geïdentificeerd, evenals delocatie waar de door stress veroorzaakte fysieke en chemische verande-ringen plaatsvinden. Met deze kennis zijn diagnostische technieken enanalytische methoden ontwikkeld om voorspellingen van de transistor-werking na elektrische stress mogelijk te maken. Als zodanig levert ditonderzoekswerk de benodigde inzichten en gereedschappen voor het ont-werp en diepgaande elektrische karakterisatie van op gradiënten geba-seerde veld-plaat ondersteunde RESURF vermogenstransistors voor en naelektrische stress.
Overzicht
Elk hoofdstuk in dit werk is gebaseerd, en weidt uit, op gepubliceerd werkuitgevoerd tijdens mijn doctoraal onderzoek.
xi
xii
SAM
EN
VA
TT
ING
Hoofdstuk 1: Algemene introductie gebaseerd op: ’An initial study onthe reliability of power semiconductor devices’ een literatuurstudie uitgevoerdin 2010 aan het begin van dit onderzoekspad [1]. Dit hoofdstuk presenteertde benodigde basis voor het kunnen kwalificeren van vermogenstransis-tors, de mogelijke problemen bij het ontwerp daarvan, de basis voor deRESURF optimalisatie en de algemene betrouwbaarheidsoverwegingen.
Hoofdstuk 2: Het ontwerp van de op gradiënten gebaseerde veld-plaatondersteunde RESURF vermogenstransistors gebaseerd op: ’Design optimi-zation of field-plate assisted RESURF devices’ gepubliceerd in 2013 als deel vande 25ste ISPSD conferentie te Kanazawa, Japan [2]. Dit hoofdstuk presen-teert de benodigde ontwerpregels voor de optimalisatie van de elektrischevelddistributie en het reduceren van de aanweerstand in verschillendetypen op diëlektrica gebaseerde RESURF transistors.
Hoofdstuk 3: Veldveranderingen en degradatie veroorzaakt door op-pervlaktelading in veld-plaat ondersteunde RESURF transistors gebaseerdop: ’Impact of interface charge on the electrostatics of field-plate assisted RESURFDevices’ gepubliceerd in 2014 in het wetenschappelijk tijdschrift TED [3].Dit hoofdstuk gaat in op de benodigde richtlijnen voor het modelleren vanoppervlakteladingsdegradatie veroorzaakt door arbitraire ladingsprofie-len.
Hoofdstuk 4: De extractie van het elektrisch veld en oppervlaktela-dingsdistributie gebaseerd op: ’Extraction of the electric field in field plateassisted RESURF devices’ gepubliceerd in 2012 als deel van de 24ste ISPSD teBrugge, België [4]. En ’Electric field and interface charge extraction in field-plateassisted RESURF devices’ gepubliceerd in 2015 in het wetenschappelijk tijd-schrift TED [5]. Dit hoofdstuk bestudeert de botsingsionisatie beneden dedrempelspanning in de op gradiënten gebaseerde veld-plaat ondersteundeRESURF transistors, hoe dit te gebruiken bij het extraheren van het lateraalelektrisch veld en hoe dit verandert aan de hand van oppervlaktelading.
Hoofdstuk 5: Het gedrag van de lekstroom in uitstand voor de opgradiënten gebaseerde veld-plaat ondersteunde RESURF transistors ge-baseerd op: ’On the degradation of field-plate assisted RESURF power devices’gepubliceerd in 2012 als deel van de IEDM conferentie te San Francisco,CA, Verenigde Staten [6]. Dit hoofdstuk presenteert de extractie en demodellering van verschillende contributies in de lekstroomgeneratie, hoedie degraderen en hoe zij worden beïnvloed door de temperatuur.
Hoofdstuk 6: Meetresultaten en de analyse daarvan gebaseerd op: ’Onthe degradation of field-plate assisted RESURF power devices’ gepubliceerd in2012 als deel van de IEDM conferentie te San Francisco, CA, VerenigdeStaten [6]. Dit hoofdstuk presenteert de verkregen meetresultaten en de
xiii
SAM
EN
VA
TT
ING
daarbij behorende analyse aan de hand van de ontwikkelde methoden.
Hoofdstuk 7: Dit hoofdstuk presenteert de belangrijkste conclusies,aanbevelingen en mogelijke vooruitzichten.
Als de hoofstukken chronologisch zouden worden geordend ([1],[4],[6],[2],[3],[5]) zien wij een typisch onderzoekspad, namelijk de zoektocht naarde oorzaak van verkregen (meet) resultaten en de vele tangentiële wegenwaar dit toe leidt. In dit doctoraalonderzoek is door het organiseren vande vele verkregen inzichten in een coherent verhaal een algemeen leidraadontwikkeld voor diegene die geïntresseerd zijn in:
Veld-plaat ondersteunde RESURF vermogenstransistors, de daarvoor opgradiënten gebaseerde optimalisatie, degradatie en analyse.
CONTENTS
ABSTRACT · vii
SAMENVATTING · xi
1 POWER SEMICONDUCTOR DEVICES · 11.1 Introduction · 2
1.2 Size and breakdown voltage · 21.3 Specific on-resistance · 5
1.4 The RESURF principle · 71.5 Degradation and reliability · 11
1.6 Methodology · 131.7 Conclusion · 14
2 DEVICE DESIGN OPTIMIZATION · 152.1 Introduction · 16
2.2 Gradient based FP assisted RESURF model · 162.3 Breakdown · 21
2.4 Field-plate potential · 292.5 Application guidelines and results · 32
2.6 Conclusion · 33
3 INTERFACE CHARGE AND ELECTROSTATICS · 353.1 Introduction · 36
3.2 Interface charge - 1-D electrostatics · 383.3 Lateral decay characteristic · 38
3.4 Modeling the interface charge · 433.5 Conclusions · 50
4 SUBTHRESHOLD CURRENT AND EXTRACTION · 514.1 Introduction · 52
4.2 Subthreshold multiplication and field extraction · 544.3 Field extraction in RESURF devices · 57
4.4 Voltage range of validity · 644.5 Interface charge extraction · 65
4.6 Conclusions · 68
5 OFF-STATE CURRENT AND TEMPERATURE DEPENDENCE · 69
xiv
xv
CO
NT
EN
TS
5.1 Introduction · 705.2 Off-state leakage current model · 70
5.3 Depletion expansion and carrier generation · 725.4 Off-state multiplication · 75
5.5 Virgin leakage current · 775.6 Band to band tunneling generation · 785.7 Interface charge carrier generation · 79
5.8 Degraded leakage current · 805.9 Conclusions · 83
6 MEASUREMENTS AND STRESS ANALYSIS · 856.1 Introduction · 86
6.2 Stress procedure · 876.3 Specific on-resistance and threshold voltage · 88
6.4 Off-state leakage degradation · 896.5 Off-state stress acceleration · 90
6.6 Stress evolution · 966.7 Modeling · 98
6.8 Conclusion · 99
7 SUMMARY & RECOMMENDATIONS ·1017.1 Summary ·102
7.2 General Conclusion ·1037.3 Original contributions ·104
7.4 Recommendations and Future work ·104
A THE PARABOLIC POTENTIAL APPROXIMATION ·113A.1 Derivation - Single Sided device ·113
A.2 Dielectric asymmetry ·116A.3 Solving Merchant’s equation - non-reachtrough case ·117
A.4 2-D distribution ·119
B IMPACT IONIZATION INTEGRAL AND MULTIPLICATION ·121
C GRADED MOSCAP DEPLETION ·123
D PARAMETERS ·125
BIBLIOGRAPHY ·129
LIST OF PUBLICATIONS ·135Peer-reviewed ·135
Other ·135
ACKNOWLEDGMENTS ·137
CHAPTER 1POWER SEMICONDUCTOR
DEVICES
Abstract
An initial literature study combined with some basic comparisonshas been performed on electric-field modulation (or electrostatic) tech-niques and the subsequent reliability issues of power semiconductordevices. An explanation of the most important power device met-rics such as the off-state breakdown voltage (BV) and the specificon-resistance RONA will be given, followed by a short overview ofsome of the electrostatic techniques used to suppress peak electricfields. Furthermore it will be argued that depending on the operatingconditions of these devices changes in electric field peaks and thereforeavalanche behavior can occur. This results in (oxide) reliability issuesunlike those of conventional field-effect transistors.
This Chapter was published as part of the SAFE at STW.ICT ’10 proceedings [1]. For clarityit has been expanded with additional figures and explanations.
1
2
1.1.IN
TR
OD
UC
TIO
N
1.1 Introduction
Low power consumption and miniaturization form by far the largest re-search interest in today’s semiconductor industry. Integration of inherently2D/3D device structures (e.g. Double Gate FETs, FinFETs), metal semi-conductor contacts (e.g. Schottky FETs ), band gap engineering and highmobility materials have gradually become a necessity in keeping up withthe goal originally set by Moore [7] in 1965. Yet the world of power semi-conductors required some of these creative design trends ([8],[9]) longbefore their low power counterparts.
Power devices have to withstand high voltages imperative for manyapplications such as motor drives and power distribution systems. There-fore high breakdown voltage is a primary requirement for power devices(paragraph 1.2). The field of power semiconductor devices encapsulateseverything from the extremely high power (>10 MW) low switching speedthyristors (e.g. in high-voltage DC power transmission [10]), the mid-range (1 kW-1 MW) MOS- Bipolar devices (IGBTs [11]), to the ’low’ power(<1 kW) high switching speed double-diffused MOS (DMOS, [12]) transis-tors. In this work the focus will be on, silicon based, devices falling in thelower end of this spectrum.
An other figure of merit is the so-called on-resistance (RON) [13]. Thisparameter is defined as the total resistance to current flow between theconducting terminals (i.e. source, drain) when the device is turned on (i.e.by the gate). The RON limits the maximum current-handling capability ofthe power device:
P = ID · VDS = I2D · RON, (1.1)
with ID the drain current, VDS the drain-source voltage and P the devicepower dissipation. Hence to reduce power loss RON should be minimized.Since power dissipation per unit area has a limit (temperature) Eq. (1.1) isalso expressed using:
P
Aw
= J2D · RONA, (1.2)
with Aw the active device area, JD the on-state drain current density, andRONA the so-called specific on-resistance, a key parameter used in the fieldof power semiconductor devices (paragraph 1.3).
1.2 Size and breakdown voltage
In the field of power semiconductors size reduction is also of great im-portance, although fundamental material properties combined with thehigh voltage, high current needs make this an inherently complicated task.When switching/blocking a given voltage (V) a device size reduction willlead to higher fields ( V/μm). At a certain critical field electrical breakdownwill occur. This type of breakdown does not have to be physically destruc-tive but indicates the point at which the device will start to electrically
3
CH
AP
TE
R1.
PO
WE
RSE
MIC
ON
DU
CT
OR
DE
VIC
ES
Figure 1.1: Device cross section of a P+N (a) and PIN (b) diode with equalBV characteristics (750 V, dashed Fig. 1.2) at a reverse bias of 500 V showingthe simulated potential line and electric field distributions.
conduct, making it unable to switch/block the given voltage. Size reduc-tion is therefore inherently limited by the device’s electric field having tobe lower than the material (semiconductor) critical field.
Figure 1.1 visualizes the size vs. breakdown voltage relation [14–16]of a silicon P+N and a PIN diode, the basic components used in mostpower devices. For the PIN diode the breakdown scales stronger with thedrift length (Fig. 1.2) since there is no space charge in the (intrinsic) driftregion. In this intrinsic layer the potential can spread evenly across anincreased length resulting in lower electric fields than at comparable P+Ndrift lengths. Therefore for the same device length the breakdown voltage(BV) of a PIN diode is higher than that of a P+N diode. This differencecan be observed in their electric field distributions (E(x)) as illustrated inFig. 1.1a and b. The difference in field distribution can be obtained bysolving the 1-D Poisson equation with (left, P+N ) and without (right, PIN)space charge density (ρ), as described below:
∂2ψ(x)
∂x2 = −∂E(x)
∂x= −
ρ
εsi
E(x) =ρ
εsix+ c
∂2ψ(x)
∂x2 = −∂E(x)
∂x= 0
E(x) = c,(1.3)
where ψ is the potential and εsi is the permittivity of silicon.The higher PIN breakdown is due to the constant electric field distri-
4
1.2.SIZ
EA
ND
BR
EA
KD
OW
NV
OLTA
GE
Figure 1.2: The device or drift length vs breakdown voltage relation of a sil-icon PIN diode (using [14]) and that of the P+N diode (Fig. 1.3, L =Wmax).The dashed line indicates the intrinsic resp. N− region lengths of thedevices depicted in Fig. 1.1.
Figure 1.3: Analytically determined [13] breakdown voltage (left-axis) vsdoping concentration (ND, N− Fig. 1.1a) of an abrupt one-sided (Si) P+Ndiode with the corresponding maximum depletion width (Wmax, right-axis).
bution across the whole intrinsic layer (Fig. 1.1b) while that of the P+Ndiode is triangular in shape with a peak critical field (≈ 2 · 105 V/cm) at theP+N junction (Fig. 1.1a). The slope of this field (Eq. (1.3)) is determined
5
CH
AP
TE
R1.
PO
WE
RSE
MIC
ON
DU
CT
OR
DE
VIC
ES
Figure 1.4: Schematic representation of device geometry as related to thespecific on-resistance. The active device area Aw is projected on the wafer,while Ac is the current cross-sectional area.
by the doping [13]. Figure 1.3 shows that the maximum depletion layerwidth increases for lower (n-type) doping concentrations yielding higherbreakdown voltages.
Therefore, for a given maximum voltage, a PIN diode can be mademore compact than a P+N diode and an N+P diode, for that matter. Thishowever comes with a crucial disadvantage. The lower, ultimately intrinsic(PIN), layer doping with its higher breakdown will cause the specific on-resistance to increase compared to the higher doped counterparts.
1.3 Specific on-resistance
As explained before, for determining the power consumption of electriccircuits the on- resistance (RON) is a key figure of merit. A higher RON
results in increased power loss, resulting in systems that consume moreenergy (produce more heat, have shorter battery life etc.). The specificon- resistance (RONA) additionally takes into account device dimensionsand orientation (Fig. 1.4), a physical characteristic. The latter is the worldstandard as it indirectly includes the cost of (on wafer) implementation.The specific on-resistance is defined as:
RONA =ρ · LAc
·Aw, (1.4)
with Ac is the current flow cross section, Aw is the active device area orwafer footprint, L is the drift length and ρ the resistivity, see Fig. 1.4:
ρ =1
qμN, (1.5)
6
1.3.SP
EC
IFICO
N-R
ESISTA
NC
E
Figure 1.5: Example of different contributing resistances in a typical HVLDMOS biased in on-state (VGS=Vth, VDS=VDD). The contact resistances(RCS and RCD), n+ resistance (Rn+ ), the channel resistance (RCh), the JFETresistance (RJFET ) and drift resistance (Rdrain) are indicated.
with q the elementary charge, μ mobility and N the doping (ND or NA)concentration. Examining Fig. 1.4, and then employing Eq. (1.4) and (1.5),RONA for both the lateral (left) and vertical (right) case can be obtained:
Ac =W × t, Aw =W × L
RONA =L2
qμNt
Ac = Aw =W × tRONA =
L
qμN
(1.6)
As shown in Fig. 1.4 for a given design a vertical device orientationmakes better use of the available semiconductor (volume) for the samewafer area [9] and therefore provides the lowest RONA. The small waferfootprint combined with large drift length required in power MOSFETs hascaused a large part of power device components, in particular discrete, tobe vertically designed. However vertical power devices, such as the verticaldouble-diffused MOSFET (VDMOS), are inherently difficult to integratewith CMOS and generally suffer from worse quasi-saturation behavior [17]than their lateral (LDMOS) counterparts. As such planar RESURF deviceshave found widespread commercial success in a variety of fields such asintegrated high-side circuitry [18, 19] and as driver transistors in high endanalog applications [20].
A universally accepted set of specified bias conditions, what devicesto use and how exactly to measure the on-resistance is lacking. Howeverwhen measuring the resistance of a device that is turned on (RON), e.g.by the gate, the doped drain (drift) extension of a device is usually onlya part of the total resistance. Figure 1.5 gives an illustration of typicalcontributing resistances, such as contact resistance (RC), channel resistance(RCh), junction FET resistance (RJFET ) and drift resistance (Rdrain), in an(on-state) LDMOS [13]. The percentage of contribution to the total deviceresistance is strongly dependent on the breakdown voltage (∝ drift length)and on how the device has been optimized. The focus of this work willonly be on the understanding and optimization of the drift length or doped
7
CH
AP
TE
R1.
PO
WE
RSE
MIC
ON
DU
CT
OR
DE
VIC
ES
Figure 1.6: Two-dimensional simulations and analytical results of the I-Vcurves (or on-resistance) for the three different drift region types. Note thatthe results depicted are for unipolar devices which use drift region dopingdistributions identical to the diode types treated.
drain extension (Rdrain) contribution. This is because it is by far the largestcontribution in the device breakdown voltage range (250-1 kV) this workfocuses on.
Figure 1.6 shows the drift region current density vs. voltage characteris-tic of various unipolar devices with the same drift region. The slope givesthe on-resistance obtained from 2-D numerical simulations and analyticalmodels in which the active area has not been taken into account. For ahigher doping (N) concentration the RON reduces (Eq. (1.6)) at the priceof a lower breakdown voltage BV (Fig. 1.3). This RONA-BV trade-off isoften referred to as the 1-D silicon limit. In Fig. 1.7 the RONA is plottedagainst BV for various power device technologies, close to this limit. Thisrelation is not linear as for instance increased doping reduces the carriermean free path resulting in a mobility (μ) decrease [13, 21] affecting RON
and breakdown (impact ionization rate) in different ways. A more detailedtheoretical limit analysis (of novel high-voltage topologies) can be foundin [22].
1.4 The RESURF principle
To break the 1-D silicon limit Appels and Vaes proposed the RESURFprinciple of a lateral power diode in 1979 [26–28], although originally theso-called superjunction structure comes from a different field: the varactorwith a highly dense capacitance, introduced by S. Shirota and S. Kaneda
8
1.4.T
HE
RE
SUR
FP
RIN
CIP
LE
Figure 1.7: The 1D silicon limit plotted with experimental RON-BV resultsfor various power device technologies [23–25].
in 1978 [29]. Ten years later in 1988 the superjunction power device wasinvented by D. Coe [30], with the first experimental superjunction devicesbeing reported in 1998 by G. Deboy et al. [25]. The device created was aVDMOS containing vertical superjunctions and was named "CoolMOS".The theory of these superjunctions is well described in [31]. The idea behindthis RESURF or superjunction concept is to have a relatively highly dopeddrift region (Low RON) while maintaining the high BV ′s [32] associatedwith a constant electric field distribution along the current flow direction.
The RESURF principle which stands for REduced SURface Field isbased on reducing the peak electric field through a 2-D or 3-D depletioneffect (Fig. 1.8a) using additional charge. The diode formed consists oftwo parts: a lateral diode with a vertical P+/N− (and N+/P−) junctionwith a possible lateral breakdown and a vertical diode with a horizontalN−/P− junction and possible vertical breakdown. The optimal (epitaxial)doping vs. layer thickness (Nepi · tepi) was shown to be ≈ 1 · 1012 cm−2
[27],[31]. This results in the lateral depletion layer being influenced by thevertical N−/P− junction in such a way that the (lateral) surface electricfield is spread along the drift extension and the peak (horizontal) fields aresuppressed. This then leads to a higher breakdown condition, occurringnot at the surface, but vertically in the semiconductor body.
Merchant et al. [33] expanded the RESURF principle for implementa-tion in SOI devices (Fig. 1.8b). The authors solved the 2D-Poisson equation:
∂2ψ(x,y)∂x2 +
∂2ψ(x,y)∂y2 = −
ρ(x,y)εsi
, (1.7)
9
CH
AP
TE
R1.
PO
WE
RSE
MIC
ON
DU
CT
OR
DE
VIC
ES
Figure 1.8: Schematic cross section of a junction RESURF (a) and gradeddoped FP assisted SOI based RESURF (b) diode. Handler wafer (HW) actsas field-plate (FP). Shown fields at a reverse bias of 500 V with BV 750 V.
by forcing the 1-D contradictory requirements of having low RON (ρ �= 0),and also a constant lateral field (∂
2ψ(x,y)∂x2 = −∂E(x,y)
∂x= 0) as a central
boundary condition (Appendix A). This resulted in the necessity of a laterallinear grading in doping [33] according to:
N(x) =(εsi/q)(BV/L)
tsi(tsi
2 + εsi
εoxtox)
x, (1.8)
with BV/L the desired uniform electric field at breakdown, tsi the siliconthickness and tox the oxide thickness. The required doping gradientsare achieved through ion implantation and diffusion through specificallyspaced mask openings as explained in [34] and [35]. It should be mentionedthat the superior field distribution and low RON made possible by this typeof RESURF is by no means exclusive to planar devices and has also beenproposed in vertical (trench) MOSFETs [36, 37]. Using the methodologiespresented by S. Merchant et al. this work will generalize and expandgradient based FP assisted RESURF device optimization (chapter 2).
10
1.4.T
HE
RE
SUR
FP
RIN
CIP
LE
Figure 1.9: Electric field evolution for (a) P+/N− and (b) Junction RESURFnormalized to that of a (c) Gradient based FP assisted RESURF extension.Dashed lines clarify size and field difference compared to the optimaldistribution of (c).
11
CH
AP
TE
R1.
PO
WE
RSE
MIC
ON
DU
CT
OR
DE
VIC
ES
A normalized overview of the field distribution and expansion duringreverse bias operation for different diodes with equal BV (750 V) drain ex-tensions is shown in Fig. 1.9. The differences in drift extension length, dueto the non-optimal field distributions, are highlighted by the dashed lines.It is clear that the field in gradient based FP assisted RESURF extensionsexpands in a unique way: the field peak does not change for a bias change,rather only the depletion width (Fig. 1.9c). This distinct field ’clamping’ [4]and expansion behavior provides unique advantages and is the basis ofmany of the models and analysis techniques developed in this work.
1.5 Degradation and reliability
After (prolonged) use device behavior can slowly start to change or evenundergo abrupt catastrophic failure. Understanding, predicting and antici-pating this type of unwanted behavior is therefore of great importance forthe design of reliable electrical (power) systems. Robust design is especiallyimportant for critical applications operating in harsh environments such asthose for automotive applications, in which the (power) transistor plays anincreasingly important role.
In analog applications, where these devices are used as driver transis-tors [20], [38], the presence of high voltages on the drain terminal serves asa source of degradation. When using DMOS devices for switching appli-cations, the devices generally operate in either the on (high VGS, low VDS)or the off (low VGS, high VDS) state. Extended periods in any of these twostatic DC states can induce some degradation. During the transient stateshowever, when both higher than off-state currents and high VDS (<BV) canoccur (i.e. the DC semi on-state), the device is typically most vulnerable.As it was still lacking, understanding the root cause of DC off-state andsemi on-state degradation in gradient based FP assisted RESURF devices isthe main focus of this study. This according to the general philosophy that,without first understanding DC device behavior, understanding transientbehavior and its many changing parameters is impossible.
The study of device degradation shows that three effects can be relevant:
1) injection, trapping/release of hot electrons in the oxide [39],
2) injection, trapping/release of hot holes in the oxide [40],
3) interface state creation [41].
In CMOS these Hot-Carrier Injection (HCI) effects can be distinguishedby capacitance-voltage (C-V) measurements or a combination of current-voltage (I-V) measurements and charge pumping. In high voltage (LD)MOSdevices, the more complex potential distributions due to the advanceddrain extensions (e.g. using field plates, thick field oxides, doping gra-dients etc) complicate the separation and distinction of these individualmechanisms. However, one can separate the general spots of electric field
12
1.5.D
EG
RA
DA
TIO
NA
ND
RE
LIA
BIL
ITY
Figure 1.10: Schematic cross section of a typical planar (SOI) RESURFdevice with a field oxide (LOCOS) and top field plate. This provides fieldsuppression through double-sided symmetric RESURF [18, 23] allowinghigher drift region doping thus lowering RON further. Possible high (lateral)electric field spots are indicated (circles, arrows).
peaks as highlighted in Fig. 1.10. In combination with large current flowsthese areas form locations of impact ionization in which the generated hotcarriers can more easily interact with the silicon - silicon dioxide interface.Analyzing [4], expanding [5] and developing [3] methods to locate fieldpeaks and consequently the responsible HCI charge, is an integral part ofthis work.
It should be clear by now that the electric field distribution in high-voltage (HV)-devices is different from that of their low power CMOScounterparts. Moreover, the high current densities associated with therelatively lowly doped (ND) drift regions in these HV devices result inlarge amounts of additional charge (related to mobile carriers n and p)in on-state operation. This charge alters the space charge distributionaccording to:
ρ(x,y) = q(N+D(x,y) − n(x,y) + p(x,y)), (1.9)
which in turn causes shifts in the electric field distribution. Commonlyreferred to as the base push out or Kirk effect [42],[43] this effect causes adestructive snapback phenomenon [44], limits the voltage handling capa-bilities (or Safe-Operating-Area, SOA) of RESURF devices [45] and makesfinding both the physical and electrical HCI points of interests yet morecomplicated [46]. Furthermore accelerated lifetime tests of HV-devices of-ten result in self-heating effects which are otherwise not present in normaldevice operation [47]. This should therefore also be taken into accountwhen studying HCI and complicates the extraction of good device life timepredictions [48]. A failure analysis of thermal behavior in these types ofdevices can be found in [49].
Throughout the years a multitude of device design strategies (e.g. mov-ing current paths away from high electric field regions) have been proposedto mitigate the degradation effects in HV-devices [28]. But the lack of pure
13
CH
AP
TE
R1.
PO
WE
RSE
MIC
ON
DU
CT
OR
DE
VIC
ES
reliability research based on understanding HV degradation phenomena,specifically for charge gradient optimized devices, has made this mostly apractice of trial and error with room for improvement. Through a combinedcharacterization, modeling and simulation strategy this work presents afirst step towards this deeper understanding.
1.6 Methodology
Electrical measurements, Technology Computer-Aided Design (TCAD)simulations and (analytical) modeling are the main pillars of semiconductordevice research. Each has its own strengths and weaknesses that usuallyrequire combined use to provide a complete understanding of devicebehavior. The extent to which these tools are used is usually dependenton the task to be performed. Obtaining a better understanding of a singleexisting device for instance requires a different approach (measurementand TCAD) than that of predicting behavior across large design ranges ormultiple interconnected devices (compact modeling). General constraintssuch as, available (computing) time, simulation tools and equipment canalso play an important role.
A large time (and monetary) investment is required to create (on waferor packaged) test structures and measurement setups. Measurementsgenerally provide I-V characteristics alone while the device itself remainsa ’black box’ without (easy or non-destructive) ways to look into it. Whenfor instance measurements show a type of behavior not understood onemight choose to study the physics behind it by employing TCAD devicesimulations. These simulation tools [50] are based on node by node (finiteelement) calculations of interacting physical models. As such they providea computer based numerical framework/environment to develop devicesand study their operation while also providing the ability to look ’into’ thedevice. Depending on the complexity of the models and the density ofnodes (the mesh) TCAD simulation can be highly time consuming.
A key feature of these tools is the ability to enable and disable differentphysical models. This is an often used method to determine what phe-nomena affect certain observed device behavior. Using this approach thekey physical models can be identified, which can then be used to creategeneral (physics based) analytical models. The initial time investment forthe development of these types of models is generally very high but onceimplemented, are usually (computationally) fast and provide capabilitiesto optimize device design and predict their behavior across wide designand operating ranges.
The methodology of observation through electrical measurements,TCAD modeling to identify key phenomena and subsequent analyticalmodeling as described above, is the general research methodology followedthroughout this work.
14
1.7.C
ON
CL
USIO
N
1.7 Conclusion
In this chapter a brief literature and simulation study was performed in thefield of power semiconductor devices. The inherent problem faced withthe desire towards smaller devices having higher breakdown voltages andyet lower on-resistances was visualized. Some of the design trends used tocircumvent these problems were discussed. The reliability problems facedwith these complex designs and their high current, high voltage operationwere briefly addressed. And finally the general (measurement, TCAD,modeling) research methodology adopted in this work was discussed.
CHAPTER 2DEVICE DESIGN OPTIMIZATION
Abstract
A mathematical model for optimizing the 2-D potential distribu-tion in the drift region of field-plate (FP) assisted REduced SURfaceField (RESURF) devices (Fig. 2.1) at reverse breakdown condition ispresented. The proposed model generalizes earlier work [33, 37] by in-cluding top-bottom dielectric asymmetry (typical in SOI devices [51]),non-zero field plate potentials (VFP) and grading of design parametersother than drift region doping. This generally-applicable, TCAD veri-fied [50], model provides a guideline for gradient based optimizationof the drain extension in a wide range of FP assisted RESURF devices.
The core of this chapter was published as part of the Kanazawa Japan ISPSD’13 proceedings[2]. It has been expanded with respect to its original publication by including a variety ofadditional figures and clarifications.
15
16
2.1.IN
TR
OD
UC
TIO
N
2.1 Introduction
As discussed in chapter 1 the RESURF [26] effect is commonly used toimprove the specific on-resistance vs. breakdown voltage (RONA-BV) trade-off in high-voltage (HV) transistors [28]. RESURF optimization primarilyaims to achieve a constant horizontal field at reverse (electrical) breakdownusing various methods like pn-junctions [26], super-junctions [31], field-plates (FP) [52] or a combination thereof [53].
This chapter focuses on FP assisted RESURF only. This type of RESURFcan be realized in both SOI [52] and trench-MOS [54] technology by tailor-ing one or a combination of the design parameters shown in Fig. 2.1:
(a) drift region doping, ND [34, 37]
(b) dielectric layer permittivity, εd [55]
(c) dielectric layer thickness, td [56, 57]
(d) semiconductor layer thickness, ts
(e) FP-potential, VFP [58, 59]
A mathematical model will be presented that allows RONA-BV optimizationfor all above mentioned FP assisted RESURF devices. Based on this, ageneralized expansion that includes super junction based RESURF and theimportance of curved contact electrodes is presented in [60].
The chapter is outlined as follows: paragraph 2.2 presents the gradientbased FP assisted RESURF optimization model, paragraph 2.3 treats devicebreakdown and how to determine it, paragraph 2.4 presents the use ofconstant field-plate potentials to optimize device design, paragraph 2.5focuses on application guidelines and the attainable RONA-BV trade-off,while in paragraph 2.6 conclusions are drawn.
2.2 Gradient based FP assisted RESURF model
The model proposed in this chapter generalizes the work by S. Merchant[37], while achieving deeper physical insight into the RONA-BV trade-offoptimization of gradient based FP assisted RESURF devices. For this pur-pose, a more general model is presented describing the optimal RESURFelectric fields and potential distributions, at reverse breakdown condition,in drain extensions using any substrate/dielectric combination (Fig. 2.1) or2-D symmetry (Fig. 2.2).
2.2.1 Constant lateral field condition
The general description of the field distribution inside the depleted drainextension is given by the 2-D Poisson equation (assuming only a lateral vari-ation in drift doping ND(x) and constant semiconductor permittivity εs):
17
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
Figure 2.1: Breakdown voltage (BV) optimization methods for FP assistedRESURF devices. Optimal structures shown for: a) graded ND; b) gradedεd; c) graded td; d) graded ts; e) graded VFP. Methods shown are alsoapplicable to vertical trench-MOS type devices.
∂Ex(x,y)∂x
+∂Ey(x,y)∂y
=qND(x)
εs(2.1)
Since optimal RESURF design requires a constant horizontal field (Ex = −BVL
,with L the drift length) it holds that at breakdown:
∂Ex(x,y)∂x
= 0. (2.2)
The constant lateral field Ex necessarily requires the lateral potential tobe a linear function of x (ψx = u(x) = BV
Lx). Using this, Eq. (2.1) can be
solved for the 2-D potential distribution (ψ) giving:
ψ(x,y) =BV
Lx+ψy(x,y), (2.3)
with
ψy(x,y) = −qND(x)
2εsy2 + c, (2.4)
obtained by accounting for Eq. (2.2) and integrating Eq. (2.1) twice. Usingboundary condition Ey(x, 0) = 0 the integration constant c is zero. Thusthe general expression for an optimal (2-D) potential distribution (at break-down) in the depleted drift extension is:
ψ(x,y) =BV
Lx−
qND(x)
2εsy2. (2.5)
18
2.2.G
RA
DIE
NT
BA
SED
FPA
SSISTE
DR
ESU
RF
MO
DE
L
Figure 2.2: Cut along the y-direction of cross sections shown in Fig. 2.1for SS, ASYM and SYM devices and their equivalent structure. Top andbottom FP potentials are equal, dark gray regions represent the dielectricand white/light gray region represent the semiconductor.
Using this parabolic potential approximation different drain exten-sion vertical designs (single-sided SS, double-sided ASYM, and SYM) canbe modeled as a single symmetrical field-plate/semiconductor structure(’EQV’, Fig. 2.2), with teq the equivalent thickness and VFP the verticalpotential boundary (dashed line, Fig. 2.3). Imposing the equivalent (verti-cal) boundary condition to the (laterally) optimal semiconductor potentialequation (Eq. (2.5), ψ(x, teq(x)) = VFP(x)) yields the design equation forcreating devices under the constant lateral field (Ex = −BV
L) condition:
VFP(x) =BV
Lx−
qND(x)
2εst2
eq(x) ⇔
εs[BVLx− VFP(x)
]qND(x)
t2eq(x)
2
= 1.
(2.6)
2.2.2 Vertical design, equivalent thickness teq and λ
Figure 2.3 shows that for any vertical design teq is the equivalent semicon-ductor depletion thickness necessary for a parabolic drop from the peakpotential (u) to the vertical potential boundary (VFP). A relation for thisequivalent thickness to the semiconductor and oxide thicknesses is essen-tial for a generalized set of optimal RESURF design rules (Section 2.2.3).From the known vertical potential drop (ψy) and the (parabolic) semicon-ductor potential equation (Eq. (2.4)) teq is derived. For a SS device the
19
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
Figure 2.3: Vertical parabolic potential distribution ψ(y) for SS, ASYM andSYM devices (solid). Also shown the distribution for the equivalent (’EQV’,Fig. 2.2) structure (dashed).
semiconductor (ψs) and dielectric (ψd) potential drop are (Fig. 2.3a):
ψs = −qND
2εst2s,
ψd =Qs
cd= −qNDts
td
εd,
(2.7)
with Qs is the silicon (depletion) charge per unit area and cd the arealdielectric capacitance. The total vertical potential drop is therefore:
ψy = u− VFP = ψs +ψd
= −qNDts
(ts
2εs+td
εd
).
(2.8)
Using the parabolic description of Eq. (2.4) the equivalent thickness ( teq)for this potential drop in a SS device is:
qND
2εst2eq = qNDts
(ts
2εs+td
εd
),
teq =
√2 · ts
(ts
2+εs
εdtd
).
(2.9)
This is related to the parabolic approximation based λ-parameter ([37],Eq. (A.15)) using:
λ =
√ts
(ts
2+εs
εdtd
),
teq =√
2λ,
(2.10)
whereby the separate parameters can be dependent on lateral location x(Fig. 2.1). Using Eq. (2.8) and (2.10) we obtain (see also appendix A):
u− VFP
λ2 =qND
εs. (2.11)
20
2.2.G
RA
DIE
NT
BA
SED
FPA
SSISTE
DR
ESU
RF
MO
DE
L
As will be discussed in the following chapters λ is a key device parameternecessary to understand many RESURF device I-V characteristics. Assuch from each of the boundary conditions corresponding to the differentvertical device configurations (Fig. 2.3), a relation for λ has been derived:
λ =
⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩
√ts
(ts2 + εs
εdtd
)⇒ SS (a)√
ts1,2
(ts1,2
2 + εs
εd1,2td1,2
)⇒ ASYM (b)√
ts2
(ts4 + εs
εdtd
)⇒ SYM (c)
(2.12)
Laterally along the device extension the vertical point of potential sym-metry (u, Fig. 2.3) forms the potential line of symmetry (path 1, Fig. 2.4).For an SS and SYM device this is y = ts resp. ts
2 from the dielectric inter-face (Fig. 2.3, Fig. 2.4a,c). For the fully depleted ASYM case this locationdepends on the asymmetry in dielectric properties and thicknesses. Sincethe potential drop (Eq. (2.8)) is equal from this location to the respectivevertical potential boundaries (Fig. 2.3b) and it holds that ts1 + ts2 = ts, theASYM vertical point of potential symmetry can be obtained using:
ts1,2 =
ts2 (ts + 2 εs
εd2,1td2,1)
ts +εs
εd1td1 +
εs
εd2td2
. (2.13)
The derivation for the above equation is given in appendix A.2
2.2.3 Lateral design rule equations
Rewriting Eq. (2.6) in terms of λ (Eq. (2.10)) leads to Eq. (2.14). This de-scribes how the different design parameters should be tailored as a functionof x (Fig. 2.1) in order to achieve optimal RESURF, i.e. a constant lateralfield at breakdown, by means of graded (Eq. (2.14)):
(a) doping RESURF, ND(x)
(b) ’ λ-RESURF’, λ2(x)
(c) FP-potential RESURF, VFP(x)
Whereby the grading of λ can be achieved through grading of the dielectricconstant (Eq. (2.14)i), dielectric layer thickness (Eq. (2.14)ii) or semiconduc-tor layer thickness (Eq. (2.14)iii).
21
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
εs(BVLx− VFP
)qNDλ2 = 1 ⇒
⎧⎪⎪⎨⎪⎪⎩ND(x) =
εsqλ2
(BVLx− VFP
)(a)
λ2(x) = εsqND
(BVLx− VFP
)(b)
VFP(x) =BVLx− qND
εsλ2 (c)
⇒
⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩
εd(x) =2qεsNDtdts
2εs(BVL
x−VFP)−qNDt2s
(i)
td(x) = − tsεd2εs
+εd(BV
Lx−VFP)
qNDts(ii)
ts(x) =εstdεd
+
√(εstdεd
)2+ 2εs
qND
(BVLx− VFP
)(iii)
(2.14)
Optimal RESURF can also be obtained using a block type combinationof graded profiles as long as Eq. (2.14) is fulfilled. Although the gradedprofiles from Eq. (2.14) are not exact solutions of the Poisson equation,good agreement between the model and TCAD simulations is achieved.Though the general approach does not change it should be noted thatfor the semiconductor thickness ( ts) and the dielectric permittivity ( εd)equations the initial assumptions made in Eq. (2.1) have to be changed toinclude non-constant boundary conditions. To fully optimize the potentialdistribution uniquely shaped terminal connections, as discussed in [60],might also be necessary.
Equations (2.12) - (2.14) provide a guideline for RESURF optimizationacross a wide range of drain extensions types. However, they will onlylead to optimal RESURF if the device breakdown voltage is limited by aconstant lateral field Ex (Fig. 2.5), as discussed in following section.
2.3 Breakdown
Breakdown in 2-D structures can occur in three possible ways: lateral(Ex) breakdown, vertical (Ey) breakdown and P-body/N–drain junctionbreakdown. The breakdown voltage BV of the device is determined bythe lowest of each of the three contributions. Each of these breakdownpossibilities will be treated separately in the subsequent sections.Breakdown is analyzed as follows, first Eq. (2.15) is solved for u(x) (=ψ(x, 0)), to obtain the potential distribution along the symmetry line y = 0(Path 1, Fig. 2.4) using Eq. (2.11).
∂2u(x)
∂x2 −u(x) − VFP(x)
λ2(x)= −
qND(x)
εs(2.15)
22
2.3.B
RE
AK
DO
WN
Figure 2.4: a) Highest electron impact ionization (highest e− − II) paths [6]for BV modeling in the three vertical configurations SS, ASYM and SYM.
Subsequently the field distributions important for impact ionization (II) [6]are obtained using (appendix A.4):
Ex(x, 0) = −u ′(x)
Ey(x,y) =u(x) − VFP(x)
λ2(x)y.
(2.16)
And finally the impact ionization (II) integrals (IIint) along these mainhorizontal and vertical ionization paths [6] (Fig. 2.4) are calculated using:
IIxint =
∫Path1
An · exp(
−Bn
Ex(x, 0)
)dx (2.17)
and
IIyint =
∫Path2
An · exp(
−Bn
Ey(W(VDS),y)
)dy. (2.18)
For a more in depth treatment of the IIint and its relation to carrier multi-plication and breakdown (runaway multiplication) see chapter 4.
2.3.1 Lateral (Ex) breakdown
Lateral breakdown occurs when IIxint (Eq. (2.17)) along the symmetryline of the depleted drift region (path 1, Fig. 2.4) reaches unity. This iswhen impact ionization results in runaway carrier multiplication (M =
11−IIint
, appendix B) causing electrical failure. For optimal (VDS = BVmax)breakdown it means having a constant (critical) lateral field of Excrit = −BV
L
23
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
at y = 0 (Fig. 2.5a). Solving IIxint = 1 for any drift region length (L) underthis constant lateral field condition gives:
1 =
∫L0An · exp
(−Bn
Excrit
)dx
1 = AnL · exp(
−BnL
BVmax
)
ln
(1AnL
)=
−BnL
BVmax
BVmax(L) =BnL
ln(AnL)
Excrit(L) =Bn
ln(AnL).
(2.19)
This is the maximum BV vs. RESURF drift length (L) equation ([33]) andequal to that of the breakdown condition of the PIN diode (chapter 1.2,[21]). When using the correct (silicon) coefficients (An = 7.03 · 105cm−1,Bn = 1.47 · 105Vcm−1 [52]) Eq. (2.19) can be used to calculate the materialgradients necessary (Eq. (2.14)) for constant critical lateral field distribu-tions at breakdown. Figure 2.5 shows modeled (Eq. 2.16, solved in ap-pendix. A.3) and TCAD simulated lateral fields. This is done at y = 0 usingoptimal (with slope a) and two non-optimal (with reduced slope 0.8a andincreased slope 1.2a) graded doping profiles as described by Eq. (2.14)a.
In Fig. 2.5a it is seen that the device has a drift length (L) of 25μmwith an optimal breakdown of 490 V as obtained by Eq. (2.19). For thenon-optimal reduced grading case of Fig. 2.5b the lateral field is below thecritical value. This results in a field that expands faster with increasingpotential causing a reachthrough, i.e. the lateral field reaches the draincontact, peak field that limits breakdown. For the non-optimal increasedgrading case depicted in Fig. 2.5c the above critical field value obtainedcauses premature breakdown (IIxint=1 for path1 < L).Using Eq. (2.17) each of the field distributions shown in Fig. 2.5 can be rep-
resented as a single IIxint value. Figure 2.6 compares the model and TCADobtained field distributions using IIxint for: (a) Doping (ND(x), Eq. (2.14)a),FP-potential (VFP(x), Eq. (2.14)c) and (b) dielectric ( td(x), Eq. (2.14)ii) gradeddevices. Good agreement between model and TCAD (chapter 1.6) has beenobtained across the full VDS range and across multiple (optimal and non-optimal) gradient values. For an even better fit see the discussion on theuse of the parabolic assumption based λ as the decay characteristic inChapter 3. Finally, non-optimal design of the lateral electrode boundaries(Anode/Source, Cathode/Drain) introduces Ex non-idealities that limitoptimal lateral breakdown. Although not a big issue for the breakdownvoltage ranges discussed here (>150 V), an in-depth discussion on electrodedesign is given in [60].
24
2.3.B
RE
AK
DO
WN
Figure 2.5: TCAD and modeled Ex at y = 0 for different VDS. Shown isgraded-ND RESURF in three different cases: a) optimal slope, b) reducedgrading (0.8opt) and c) increased grading (1.2opt).
25
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
Figure 2.6: a) TCAD and modeled Ex -ionization integrals (IIxint ) for SYMgraded-ND and graded-VFP RESURF in three different grading cases b) Asin (a) but for graded- td. For all simulations a Si/SiO2 structure is assumedwith a fixed εs/ εd ratio of 3.
2.3.2 Vertical (Ey) breakdown
Vertical breakdown occurs when IIyint (Eq. (2.18)) along a vertical ioniza-tion path reaches unity. The largest vertical ionization path is found alongthe longest path at the edge of the depletion region (path 2, Fig. 2.4), whereEy is maximum (Fig. A.2). Figure 2.7 shows the calculated IIyint at the edgeof the depletion region (x = W(VDS)) of an L = 40μm and ts = 1μm de-vice with three different vertical configurations of the dielectrics (Fig. 2.4).A clear reduction in breakdown is seen for increasing ionization paths.As such the SS configuration with its longest vertical ionization path ( ts,
26
2.3.B
RE
AK
DO
WN
Figure 2.7: Ey -II integrals calculated for SYM ( td=3μm), ASYM ( td1=6μm,td2=3μm) and SS ( td=3μm) devices showing vertical breakdown decreaseas the y-path length (Path 2, Fig. 2.4) increases. Inset: correspondingsimulated off-state I-V in the three cases.
Fig. 2.4) has the lowest breakdown voltage followed by the ASYM and sub-sequently the SYM configuration. For an ASYM device the longest amongstts1 and ts2 (Eq. (2.13)) is the breakdown limiting path of importance.
The vertical designs used in Fig. 2.7 don’t reach the optimal lateralbreakdown (BVmax(40μm) = 740 V, Eq. (2.19)), even for the shortest verticalionization path (SS = 1
2 ts = 0.5μm). This, because a critical Ey field isreached before lateral breakdown could occur. Solving IIyint = 1 the criticalvertical peak field can be obtained for any given path length as shown inFig. 2.8a. Contrary to Eq. (2.19) this is performed numerically as Ey is afunction of y (Eq. (2.16)) and
∫exp( 1
y)dy (Eq. (2.18)) does not have a closed
form solution. Figure 2.8a shows that for a 0.5μm vertical path length, likefor the (SYM) devices shown in Fig. 2.8b, Eycrit is 65 V/μm.
Figure 2.8b shows the increase of the peak Ey field, located along thesemiconductor/dielectric interface (Ey(x, 1
2 ts), Eq. (2.16), Fig. A.2). For 3different oxide thicknesses these peak values are shown along the lateraldirection x of the extension. When reducing the oxide thickness a largerpart of the vertical voltage is dropped in the semiconductor resulting in asharper increase in Ey at the interface. As such a critical Ey field is reachedearlier (lower BV) for the thinner oxide devices, i.e. those having a smallerλ (Eq. (2.16)). For an optimized design, Eycrit should not be reached beforeExcrit. An overview of the Excrit vs. Eycrit limited breakdown interaction, forthe SYM ts = 1μm device is shown in Fig. 2.8c. The theoretical minimumsize (lateral and vertical design) is therefore at the intersection when both
27
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
Figure 2.8: a) Numerically obtained Eycrit for different vertical ionizationpath lengths. b) Simulated ts = 1μm SYM device (y-path = 0.5μm) show-ing lateral increase of Ey-fields at Ey(x, 1
2 ts) for different dielectric thick-nesses. Vertical breakdown locations are indicated in the same figure. c) BVvs. drift length L for graded-ND RESURF, showing the limitations on thechoice of td imposed by Ey-breakdown. The inset shows a comparisonbetween simulated and modeled BV .
28
2.3.B
RE
AK
DO
WN
lateral (blue, Fig. 2.8c) and vertical (gray, Fig. 2.8c) breakdown happensimultaneously. As shown in the inset of Fig. 2.8 this occurs at td = 3.5μmfor the L = 40μm, ts = 1μm SYM device. To postpone vertical breakdownit is only needed to increase the dielectric thickness (reducing Ey ) or reducethe ionization path (reducing ts) for those lateral positions (x) beyondwhich Eycrit would be exceeded. For instance to optimize breakdown, thevertical breakdown limited L = 40μm, td = 3μm device of Fig. 2.8b onlyneeds to increase oxide thickness or reduce the vertical ionization path forextension location x > 34μm.
Finally, when the vertical path is sufficiently short (e.g. 0.25μm inFig. A.2) the critical field values (Eycrit = 85 V/μm, Fig. 2.8a) can exceedfields at which Band to Band (B2B) tunneling starts playing a significantrole (EB2B > 70 V/μm in silicon) [61, 62]. Tunneling is not an impact ioniza-tion current, rather a generation current that rises steeply with increasingfields (beyond EB2B). Devices that have (vertical) fields that exceed EB2B
while still being below Eycrit can therefore have ’runaway’ tunneling gen-eration, that limit breakdown (Fig. 5.7). As is clear from Fig. 2.8a thisscenario (Eycrit>Ey>EB2B) is primarily an issue for ultrathin SOI (or ultra-scaled trench) high-voltage devices. Chapter 5 [6] will further discuss thisgeneration component and its unique (minimal) temperature dependencerelated to off-state leakage generation.
2.3.3 Junction breakdown
Having a high initial doping N0 (ND(x=0)) at the source/anode junctionmight lead to junction field peaks not suppressed by the vertical depletionside of the 2-D RESURF effect (Fig. 2.9a). In 1979 when Appels and Vaesfirst described the occurrence of REduced SURface Fields by means of a2-D depletion effect [26] the maximum junction dose rule was postulated:
tmax ·ND(0) = 1 · 1012. (2.20)
This describes the relation between the initial doping (ND(0)) and max-imum silicon layer thickness (tmax) that can be (2-D) depleted (in a SSdevice) without premature breakdown from the (1-D) junction fields. Thevertical semiconductor thickness to be depleted for SYM and ASYM de-vices are as described previously in Fig. 2.3. Figure 2.9a shows TCADobtained lateral field distribution of a SYM L = 40μm and ts = 0.5μmdielectric graded RESURF device (Eq. (2.14)ii). The results show junctionbreakdown limiting the ideal device breakdown (BVmax = 740 V) whenND(0) exceeds the 4 · 1016cm−3 maximum obtained for tmax = 0.25μm inEq. (2.20). Figure 2.9b gives an overview of TCAD obtained breakdown val-ues for two SYM device semiconductor layer thicknesses (0.5μm, 0.2μm).Breakdown is clearly shown to be junction limited at those doping lev-els exceeding 4 · 1016cm−3 resp. 1 · 1017cm−3 (dashed) as stated by themaximum junction dose rule of Eq. (2.20).
29
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
Figure 2.9: a) Junction breakdown in a SYM td-graded RESURF device.Doping concentrationND increase leads to higher junction Ex -fields limit-ing breakdown. b) BV vs. ND for different thicknesses ts showing onset ofjunction breakdown shifted towards higher ND when reducing ts (see alsoinset).
2.4 Field-plate potential
Obtaining a constant Ex is not always possible with grounded field-plates(VFP=0 V), because Eq. (2.14) predicts unrealistic (i.e. negative) valuesfor device parameters at x=0. Equation (2.21) shows how to get rid offthese unrealistic terms by tailoring the VFP-value [63] for the different(ND(x), td(x), εd(x), ts(x)) types of gradient based FP assisted RESURF.
30
2.4.FIE
LD
-PL
AT
EP
OT
EN
TIA
L
Figure 2.10: a) Simulated Ex -fields at breakdown for graded-ND RESURFwith and without VFP compensation. b) Simulated and modeled BV vs.VFP for different values of the initial doping ND(0).
VcompFP =
⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩
−qND(0)tsεs
(ts2 + εs
εdtd
)ND(x)
−qNDtsεs
(td(0) + tsεd
2εs
)td(x)
−qNDtsεs
(ts2 + εs
εd(0)td
)εd(x)
−qNDts(0)2εs
(ts(0) − 2 εs
εdtd
)ts(x)
(2.21)
31
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
Figure 2.11: Simulated and modeled BV vs. ND(0) with and without VFP-compensation for different values of ts. Breakdown for VFP compensationis limited to junction breakdown similar to Fig. 2.9b. The VFP values usedare obtained from Eq. (2.21) - ND(x).
From a design perspective field-plate compensation can be of particularinterest in the case of graded ND and td as it allows for compensationof technological design limitations. For instance, if an (increased) initialdoping ND(0) is needed or a minimum td(0) this can be accounted for inthe ND(x) resp. td(x) cases (Fig. 2.1a,c) using an appropriate VFP.Figure 2.10a shows TCAD obtained lateral fields of a graded-ND(x) devicewith high and low initial doping, with and without VFP compensation. Fora sufficiently low initial doping (high RON, chap. 1.3) no field-plate compen-sation is needed for optimal lateral breakdown. When the initial doping isincreased (lower RON) however, this has to be compensated according toEq. (2.21).Figure 2.10b visualizes the gradual increase in breakdown across a rangeof negative field plate potentials and different initial doping values. Theoptimal breakdown plateau is at the voltages described by Eq. (2.21). Whencompensating the initial doping in doping graded devices it is important tonote that the junction breakdown limit, as described by Eq.(2.20)), will stillhold. In Fig. 2.11 the same vertical device symmetries (tmax) as Fig. 2.9bare used and show similar junction limited breakdown for the VFP compen-sated curves. Finally, smart usage of field-plate potentials can be beneficialnot only for off-state breakdown optimization as discussed here, but alsofor active RON reduction as discussed in [64]. Understandably, non-optimalfield-plate potentials can reduce both on and off-state breakdown, thisparasitic effect is discussed in [65].
32
2.5.A
PP
LIC
AT
ION
GU
IDE
LIN
ES
AN
DR
ESU
LTS
Figure 2.12: Comparison of theoretical RONA-BV trade-off for graded-NDRESURF with and without VFP-compensation for both lateral and verticaldevices. For ts=1μm (SYM device) and optimalND(x) profile, other designparameters ( td andND(0)) are selected to achieve minimum RONA for idealBV .
2.5 Application guidelines and results
Using the proposed model, the following guideline for optimizing FPassisted RESURF can be derived:
1. first determine the drift-region length (L) for the desired ideal BVfrom Eq. (2.19) ;
2. then optimize the lateral BV by grading one of the design parametersaccording to Eq. (2.14);
3. finally tailor the other device parameters such that: a) the deviceis not subjected to vertical breakdown (Chapter 2.3.2) or junctionbreakdown (Chapter 2.3.3); and b) the specific on-resistance RONA isminimized.
2.5.1 Specific on-resistance (RONA) optimization
Because of the complex interaction between the different breakdown limit-ing criteria an optimization routine has been developed that incorporatesgiven design parameters (e.g. ND(0), ts, td) for optimizing the RONA-BVtrade-off. Figure 2.12 shows this for a ts=1μm device for which the maxi-mum value of the drift dopingND(x) to achieve a minimum RONA has been
33
CH
AP
TE
R2.
DE
VIC
ED
ESIG
NO
PT
IMIZ
AT
ION
determined. Performing such optimization on a graded-ND device showsRONA-BV improvements when using negatively-biased VFP compared tothe grounded counterpart (Chapter 2.4). An improvement of a factor 5 forlateral and 2 for vertical devices is obtained.
2.5.2 Deviations from optimal design
The device designs treated here have been optimized at the edge of theirmaximum breakdown conditions. This is however ill advised for realapplications since any non-optimal characteristics such as drift dopingfluctuation or injected (interface) charge will affect the ideal fields andresult in premature breakdown or drastic reliability concerns. For reliabledevice operation the drain extension is therefore usually designed withlonger than required L or thicker td. To improve the understanding towhat extent this is necessary the influence of (charge) non-idealities onoptimal fields and general device I-V characteristics has to be analyzed.This is the main topic of interest for all subsequent chapters.
2.6 Conclusion
A mathematical model describing field and potential distributions in dif-ferent configurations of gradient based FP assisted RESURF devices hasbeen presented and verified by TCAD simulations. Using the proposedmodel, an optimal RONA-BV trade-off can be achieved for both lateral andvertical devices.
CHAPTER 3INTERFACE CHARGE AND
ELECTROSTATICS
Abstract
A systematic study on the effects of arbitrary parasitic chargeprofiles, such as trapped or fixed charge, on the 2-D potential dis-tribution in the drain extension of reverse-biased (gradient based)field-plate (FP) assisted RESURF devices is presented. Using TCADdevice simulations and analytical means the significance of the so-called characteristic or natural length λ is highlighted with respect tothe potential distribution and related phenomena in both ideal (virgin)and non-ideal (degraded) drain extensions. Subsequently a novel andeasy-to-use charge-response method is introduced that enables cal-culation of the potential distribution for an arbitrary parasitic chargeprofile once the peak potential and lateral fall-off (∝ λ) caused by a sin-gle unit charge has been determined. This can be used for optimizingand predicting the performance of RESURF power devices, after hotcarrier injection.
The core of this chapter was published in IEEE Transactions on Electron Devices, Vol.61,No.8, [3].
35
36
3.1.IN
TR
OD
UC
TIO
N
3.1 Introduction
Proper shaping of the electric field distribution in the drain extension ofpower devices plays a key role in improving the specific on-resistance vs.breakdown voltage trade-off. As treated in chapter 2, at reverse breakdowna delicate charge balance is required for constant lateral fields in the driftextension. Understandably a small non-ideality in this balance, such asinterface charge, can cause changes in device characteristics which can leadto failure.
This chapter focuses on devices where the RESURF effect is dominantlyinduced by field-plates, as found in many SOI or Trench-MOS based tech-nologies [2, 33, 54, 57, 66–69]. Figure 3.1 shows the lateral field distributionand resulting (subthreshold) device characteristics in reverse-bias operationfor:
i) a virgin device with ideal RESURF
ii) after degradation by a uniformly distributed interface charge profile
iii) after degradation by a Gaussian-shaped interface charge profile
with the degraded devices containing interface charge along the drainextension at the Si/SiO2 interface as indicated in Fig. 3.1a.
For the ideal device i) a uniform lateral field and a high breakdownvoltage (chapter 2) of around 760 V is observed. When interface charge isintroduced, in cases ii) and iii), a non-uniform field is obtained resulting innon-ideal I-V curves with reduced breakdown voltages (BV). Since inter-face charge can lead to an electric field increase, hot-carrier-induced chargeinjection is a reliability concern in RESURFdevices [6, 70–72]. Physical un-derstanding and models of the charge induced changes in the electric fieldare therefore essential for the design of drain extensions that can withstandworst case scenario HCI phenomena. The objectives of this chapter areto provide an intuitive method to study the effect of (non-ideal) interfacecharge on device characteristics (Fig. 3.1b-d), to model this and to clarifythe significance of the geometry-related modeling term λ. Except for thephysically larger dimensions, the electrostatics in field plate RESURF de-vices are quite similar to that observed in (multi-gate) FD-SOI, FinFETs,nanowires [73] and junctionless transistors [74, 75]. This makes many ofthe analysis techniques and methods described applicable to a variety ofdevice types.This chapter is outlined as follows. Paragraph 3.2 focuses on the effect ofinterface charge on the one-dimensional (1-D) electrostatics along a verticalcross-section of the device. Paragraph 3.3 introduces the geometry-relatedlength λ, and its impact on the electrostatic device behavior. Paragraph3.4 extends the quasi-two-dimensional (2-D) gradient based FP assistedRESURF model [2, 37] to include interface charge, focuses on how thischanges the 2-D electrostatics and how to model these changes for arbitraryNit distributions. In paragraph 3.5 conclusions are drawn.
37
CH
AP
TE
R3.
INT
ER
FAC
EC
HA
RG
EA
ND
EL
EC
TR
OSTA
TIC
S
Figure 3.1: The effect of interface charge on the reverse-bias operation ofgradient based FP assisted RESURF structures. a) Schematic half-widthcross-section of the device, in which the axis of device symmetry is aty = 0, with interface charge (Qit) indicated; b) Fixed and Gaussian shapedinterface charge profiles (Nit(x) = Qit(x)/q); c) Virgin and degradedlateral fields; d) Subthreshold I-V and breakdown behavior at the backgate(body) terminal.
38
3.2.IN
TE
RFA
CE
CH
AR
GE
-1-D
EL
EC
TR
OSTA
TIC
S
3.2 Interface charge - 1-D electrostatics
Treating the electrostatics in 1-D improves the understanding and modelingof RESURF devices. Figure 3.2 gives a schematic overview of the charge,the electric field and the potential along the vertical (y-) direction in fullydepleted silicon with and without interface charge Qit (= q ·Nit).
Since a (net) positive Qit is more common in electrically stressed N-drain extension devices [76] the focus is on positive type charge, withnegative charge having an inverse effect. Along a vertical cross-sectionthe interface charge Qit can be modeled as a Dirac delta charge at thesemiconductor/dielectric interface, here Si/SiO2, as illustrated in Fig. 3.2a.With fully depleted silicon a mirror charge Qmir is formed at the field-plateinterface. The combined effect of these charges (see step responses, arrowsin Fig. 3.2a) is an increased field in the oxide (Eoxy ) while the semiconductorfield (Esiy ) does not change (Fig. 3.2b). This results in an increased potentialdrop across the oxide (Eoxy ), and consequently an increase or offset (ψstep)in the parabolic semiconductor potential (Fig. 3.2c). This charge-inducedpotential offset is taken into account considering the areal capacitanceCox (= εox/ tox) with ψstep = Qit/Cox. This allows the Qit influence tobe included in the 2-D potential distribution using the RESURF model[2, 37] as shown in paragraph 3.4. The 1-D parabolic potential profile iny-direction as seen in Fig. 3.2c forms a key approximation (appendix A)in many quasi-2-D device models [37, 77–79] where teq is the equivalentlength at which the parabolic potential (dashed lines) drops to the field-plate potential VFP , see also paragraph 2.2.
3.3 Lateral decay characteristic
In the previous paragraph the effect of interface charge was describedusing 1-D electrostatics. However, for correct modeling of the impact of acharge perturbation in a dielectric interfaced semiconductor structure the2-D Poisson equation in the drift region (Fig. 3.1a) has to be solved:
∂2ψ(x,y)∂x2 +
∂2ψ(x,y)∂y2 = −
ρ(x,y)εsi
, (3.1)
with ρ the total charge density and εsi the silicon dielectric constant. FromEq. (3.1) it can be derived, see appendix A.3 [37, 80, 81], that the lateral(x-direction) potential distribution has an exponential decay according toe+
xλ or e−
xλ . This decay length λ is a key geometric scaling parameter com-
monly referred to as the natural length [73] or device characteristic length[80]. Since this parameter has a strong impact on optimizing device designand modeling of the device electrostatics in both low [73, 78, 80] and high[2, 37] voltage devices, this paragraph summarizes the different methodsused to determine it. After this summary, in Paragraph 3.4 the effect of acharge perturbation on the potential distribution will be discussed.
39
CH
AP
TE
R3.
INT
ER
FAC
EC
HA
RG
EA
ND
EL
EC
TR
OSTA
TIC
S
Figure 3.2: Schematic vertical cross-sections showing changes in charge(a), field (b) and potential (c) distributions in an ideal (left) and a degraded(right) drain extension. The arrows in (a) indicate the 1-D (field) stepresponses of the respective Dirac delta charges. Cross-sections of thecomplete structure are presented, with the axis of symmetry at y = 0.
3.3.1 Determining the characteristic length λ
Three equivalent 2-D structures (Fig. 3.3a) have been simulated withTCAD [50] using a dielectric stack electrostatically similar to fully depletedSi (ε = εsi) sandwiched between insulating dielectrics (SiO2, ε = εox). Frompotential perturbations within this system (Fig. 3.3b,c) the lateral exponen-tial decay is studied.
40
3.3.L
AT
ER
AL
DE
CA
YC
HA
RA
CT
ER
ISTIC
Figure 3.3: TCAD obtained characteristic lengths λ for different verticaldevice dimensions; a) Schematic cross-section of simulated structures usingan electrode biased at 1 V to study the potential decay; b, c) simulated lat-eral potential from: built-in pn-junction potential (left), electrode potential(center) and drain (biased at 1 V) potential (right).
Figure 3.3c confirms that this decay is equal to 1/ λ on a natural log-arithmic scale. From the slope of these curves we obtain λ1 = 2.5μm,λ2 = 1.5μm, and λ3 = 5.0μm. Hence for smaller vertical dimensions thedecay is steeper. In literature several methods have been proposed to esti-mate λ. These methods can generally be divided into two main categories:
(I) those based on relating the vertical potential distribution to the lateraldecay using a parabolic potential approximation [37, 78, 82, 83] , and
(II) those looking at the 2-D electrostatic problem of the system using theevanescent-mode analysis [80, 84, 85].
The proposed λ estimations ( λa, λb, λc, λd) are summarized in Table 3.1.Comparing λ values extracted from TCAD to those calculated using
the equations in Table 3.1 shows (Fig. 3.4) that the methods based on theparabolic approximations ( λa, λb) underestimate λ. The implicit evanes-cent mode equation for λ does correctly determine the lateral fall-off ( λc,λd), albeit at the cost of much increased numerical complexity. Although
41
CH
AP
TE
R3.
INT
ER
FAC
EC
HA
RG
EA
ND
EL
EC
TR
OSTA
TIC
S
Parabolic approx. Evanescent mode
λa =√
kη· tsitox k· tan
(tsiλc
)tan
(tox
λc
)= 1
[83] [85][80]
λb =
√kη· tsitox
(1 + tsi
4ktox
)λd = tsi+2ktox
πfor (tsi � tox)
[37] [78] [84]
Table 3.1: Determining λ (k = εsi
εox, η see references)
Figure 3.4: Comparison of TCAD extracted λ values with those calculatedusing Table 3.1. a) tsi � tox ; b) tsi tox
the two groups of λ are used interchangeably as the lateral decay charac-teristic, from a mathematical standpoint they are in fact different quantities.The λ’s determined by the evanescent mode analysis give the solutionfor the lateral fall-off [80, 84, 85], while the parabolic-approximation, asreported in [37, 78], is accurate for determining fully depleted optimaldevice design at breakdown (VDS = BV) conditions [2] , see also chapter2. Even though in many situations the parabolic approximated λ’s arein good agreement (Fig. 3.4a for tsi � tox), it is recommended to use aevanescent mode ( λc, λd) or TCAD determined λ to best model the lateraldecay effects studied in this work.
Asymmetry (chapter 2, ASYM) in field oxides, for instance using Shal-low Trench Isolation (STI) on top and a Buried Oxide Layer (BOX) at thebottom, as seen in many lateral RESURF devices [51, 72], is not treatedseparately in this chapter. This is because asymmetry simply results in asystem with a single λ, between that of a symmetric and single sided case(chapter 2).
42
3.3.L
AT
ER
AL
DE
CA
YC
HA
RA
CT
ER
ISTIC
Figure 3.5: TCAD results for a device with and without interface charge(Fig. 3.1). With a) left axis: lateral field for different drain potentials, rightaxis: depletion charge perturbation induced by a voltage step dV = 0.1V .The graded N-drift doping profile causes the increasing charge peak; b) Thedecay of the field (left) and potential perturbation (right) in the depletedpart of the extension caused by depletion charge (dQdep).
3.3.2 λ and interface charge
Using the parabolic potential approximation the (ideal) drain extensionof FP assisted RESURF structures can be modeled as a symmetric field-plate/semiconductor structure (chapter 2). The parabolic potential drop(towards VFP) follows the equivalent depletion thickness teq as indicatedby the dashed blue line in Fig. 3.2. For the latter, it holds that teq =
√2 λ. As
shown in paragraph 3.2, according to the 1-D equivalent model, interfacecharge does not affect teq (and hence λ) as the potential curvature isconstant while only introducing an increase in VFP equal to ψstep.
To confirm whether the lateral exponential decay is unaffected by inter-face charge (Qit) TCAD simulations have been performed. Figure 3.5 showsthe simulation results of both the lateral field and the potential induced bya depletion charge perturbation (dQdep), caused by a drain potential stepof 0.1 V. This has been done for the differentQit profiles shown in Fig. 3.1b,i.e. i) no Qit (ideal device), ii) a uniform and iii) a Gaussian Qit distribution.The constant decay (∝1/ λ) in Fig. 3.5b indeed indicates that λ is a functionof the device geometry and is not affected by the interface charge. Thissimplifies modeling of the effect of interface charge on the electrostatics, aswill be discussed in the next paragraph.
43
CH
AP
TE
R3.
INT
ER
FAC
EC
HA
RG
EA
ND
EL
EC
TR
OSTA
TIC
S
3.4 Modeling the interface charge
To assess degradation phenomena it should be known how interface chargeaffects the device electrostatics. In [2, 37] the 2-D Poisson equation (3.1)was solved for (ideal) RESURF devices assuming a constant lateral field,i.e. d2ψ(x,y)
dx2 = d2u(x)dx2 = 0 (appendix A). The term u(x) represents the
lateral potential distribution at the potential line of symmetry ( 12 tsi for
symmetric, tsi for single sided devices, chapter 2), the location of interestfor subthreshold multiplication (Chapter 4) and for many other modelingpurposes, such as the subthreshold current [81] and threshold voltage [79]in junctionless transistors. This work extends the solution of u(x) (Eq. A.19)[2, 37] by adding the potential offset caused by the interface charge (ψstep,Fig. 3.2c) to that of the field-plate (VFP) potential resulting in the followingequation:
d2u(x)
dx2 −u(x) − (VFP + qNit
Cox)
λ2 = −ρ
εs, (3.2)
assuming the potential distribution is described as ψ(x,y) = u(x) · g(y),with u(x) and g(y) dependent upon the lateral and vertical direction re-spectively. The interface charge component is Qit = qNit, Cox is the oxidecapacitance per unit area, VFP the field-plate potential and ρ = qND thedrift doping charge density. Since modeling the electrostatic perturbationscaused by interface charge is the focus of this work, the lateral potentialu(x) is split into
u(x) = uopt(x) + uit(x), (3.3)
with uopt the ideal lateral potential and uit the potential caused by interfacecharge only. Subsequently substituting this expression in (3.2) yields:
d2uopt(x)
dx2 −uopt(x) − VFP
λ2 = −ρ
εs, (3.4a)
d2uit(x)
dx2 −uit(x) −
qNitCox
λ2 = 0, (3.4b)
with Eq. (3.4a) giving the lateral potential distribution in the drift regionin the absence of interface charge (u(x) = uopt(x)). Equation (3.4b) can berewritten as the more conventional nonhomogeneous differential equation
d2uit(x)
dx2 −uit(x)
λ2 = −qNit
λ2Cox. (3.5)
The shape of perturbation uit(x) can be derived using Eq. (3.5) withboundary conditions uit(0) = 0 and uit(L) = 0, where L is the length of thefully depleted drain extension and x = 0 the position of the body-drain junc-tion, see also Fig. 3.1a. Solving Eq. (3.5) in the regions of the drift extensionwithout interface charge results in a homogeneous (Nit = 0 cm−2) differ-ential equation with general solution
uit(x) = A+e
xλ +A−e−
xλ . (3.6)
44
3.4.M
OD
EL
ING
TH
EIN
TE
RFA
CE
CH
AR
GE
For a single, delta-function-shaped interface charge Nit(x) = δ(x− x0)
at a position x = x0: the analytical solution can be written in two parts:
uδit,0(x) =
{uit,l(x) = A
+l,0e
x−x0λ +A−
l,0e−
x−x0λ , x < x0
uit,r(x) = A+r,0e
x−x0λ +A−
r,0e−
x−x0λ , x > x0
, (3.7)
with uit,l(x) on the left and uit,r(x) on the right side of the interface charge.The potential needs to be continuous and the condition for its derivativeis obtained by integrating Eq. (3.5) over an infinitesimal distance thatcontains x0. Thus we get:
uit,l(x0) = uit,r(x0), (3.8)duit,r
dx(x0) −
duit,l
dx(x0) = −
q
λ2Cox. (3.9)
From (3.9) it is clear that the analytical solution of uit indeed has to be writ-ten in two parts to accurately model the discontinuity in its first derivative(Eit at x0 both positive and negative). In combination with the boundaryconditions uit(0) = 0 and uit(L) = 0, the coefficients A are given by:
A−l,0 =
q(1 − e2(L−x0)/λ)
2λCox(e2L/λ − 1), (3.10)
A+l,0 = −A−
l,0e2x0/λ, (3.11)
A−r,0 = A−
l,0 +q
2λCox, (3.12)
A+r,0 = A+
l,0 −q
2λCox. (3.13)
From Eq. (3.7) using the corresponding coefficients Ai it can be seen thatthe resultant (left, right) lateral fall off for charges at different positionsx0 is related to the distance from the potential boundaries x = 0 andx = L (see e.g. Fig 3.8b,c). Having solved the equation for a singledelta charge at position x0, we can generalize the solution for any chargedistribution in a window Wit by a set of delta charges at N positions xiwith i = 0, 1, . . .N − 1, hence, Wit = N · (xi+1 − xi). Each of the chargesinduces a potential contribution uδit,i(x) which needs to satisfy Eq. (3.5),such that the discrete convolution:
uit(x) =
N−1∑i=0
uδit,i(x) (3.14)
=
N−1∑i=0
(A+
l|r,i ex−xi
λ +A−l|r,i e
−x−xi
λ
)(3.15)
holds. The values of the parameters Ai are different on the left and rightside of each of the charges, satisfying Eqs. (3.10)-(3.13). With these equa-tions the effect of an arbitrarily distributed charge on the potential distribu-tion of a device can be calculated in a straightforward manner. Equation
45
CH
AP
TE
R3.
INT
ER
FAC
EC
HA
RG
EA
ND
EL
EC
TR
OSTA
TIC
S
(3.14) can also be written as a more general convolution integral and itscorresponding Laplace transform according to:
Δuit(x) = L−1 {Nit(s)× uδit(s)} =[Nit∗uδit
](x) =
∫x0Nit(τ)·uδit(x−τ)dτ,
(3.16)which will prove particularly useful when applied inversely, to extractcharge distributions (chapter 4). Finally, it is interesting to note that theintroduced perturbation approach is generally applicable to devices witharbitrary, not necessarily RESURF optimized
(uopt(x)
), potential distribu-
tions.
3.4.1 Potential distribution change for windows of fixed Qit
Various device extensions (i.e. λ1, λ2 and λ3, Fig. 3.3a) have been TCADsimulated using an interface charge of q× 2 · 1011 = 32 nC.cm−2 for varyingwindow widths Wit. The ideal potential (and lateral field) distributions(Fig. 1c, situation i) have been subtracted from the non-ideal ones (seeEq. (3.3)) yielding the TCAD obtained changes in potential as shown inFig. 3.6a,b. These changes have also been modeled using Eq. (3.15) forcomparison showing good agreement (Fig. 3.6a).
For a fixed λ and increasing window of interface charge (Wit = 1, 5,20μm, Fig. 3.6a,b) an increase in peak potential (ψpeak
x , located at Wit2 )
is seen. For a fixed window of interface charge (Wit= 5μm, Fig. 3.6a,b),devices with smaller vertical (oxide) dimensions (smaller λ, Fig. 3.3a)and therefore larger oxide capacitances (Cox) show a lower peak potential(ψpeak
x ). The normalized ψpeakx response versus Wit
λis shown in Fig. 3.6c.
The mathematical description of this peak potential behavior as related toa fixed charge windowWit can be obtained using the convolution integralEq. (3.16) for the potential resulting in:
ψpeakx (Wit) =
qNit
Cox
(1 − e−
Wit2λ
)(3.17)
which saturates to the 1-D value (ψstep = q·NitCox
), described in paragraph 3.2,for Wit � λ. This emphasizes that the 1-D approach for calculating thepotential change caused by Nit does not hold laterally. On the other hand,for Wit,i λ (Wit,i ≈ dx) the peak potential response will approach thatof the delta function described in Eqs. (3.7)-(3.13) at x = xi where the peakpotential is given by
ψpeakx (Wit,i) = ψ
peaki = Δuδit(xi) = A
+r,i +A
−r,i = A
+l,i +A
−l,i. (3.18)
46
3.4.M
OD
EL
ING
TH
EIN
TE
RFA
CE
CH
AR
GE
Figure 3.6: Potential distribution caused by varying fixed Nit windows. a)
linear; b) logarithmic; c) normalized ψpeakx for increasingWit and different
λ’s. A linear region is observed left of the vertical dashed line; d) linearregion of ψpeak
x = ψpeaki . The green dot indicates a Wit
λvalue usable for
effective discretization using Eqs. (3.14) and (3.19). The red dot indicates aWitλ
value which is not.
For the sake of convenience we simplify Eqs. (3.7), (3.10)-(3.13) into amore compact form:
uit,i(x) =
⎧⎪⎪⎨⎪⎪⎩ψ
peaki · sinh(x/λ)
sinh(xi/λ)W > x � xi
ψpeaki · sinh((W−x)/λ)
sinh((W−xi)/λ)W > x > xi
0 x < 0 ∨ x > W,
(3.19)
withW the depletion edge (see 3.4.3). The potential boundary conditionsused to obtain the above are ψ(xi, tsi
2 ) = ψpeaki , ∂ψ
∂y(x, 0) = 0, ψ(0,y) = 0
and ψ(W,y) = 0. Figure 3.8a,b,c illustrates modeling the (potential) re-
47
CH
AP
TE
R3.
INT
ER
FAC
EC
HA
RG
EA
ND
EL
EC
TR
OSTA
TIC
S
Figure 3.7: a) 1μm wide interface charge windows Wit used in TCAD sim-ulations. Effect of the respective interface charge windows on (b) potentialuit(x)and (c) the lateral field Eit(x) for increasing Nit with a fixed interfacecharge window of 1μm; and d) I-V curves formed by impact ionizationfor various Nit values. The lateral field peak increases with Nit , eventuallycausing premature local avalanche breakdown.
sponse using Eqs. (3.17) and (3.19). The field can be obtained throughdifferentiation of the potential, Eit(x) = −duit(x)
dx. Equation (3.19) does not
include the lateral drop in potential within the charge window (Fig. 3.6a,and 3.7b). It simply models the response as a peak potential, located atthe center of the window, with a lateral exponential drop on each side ofe−
xλ resp. e
xλ . As such, Eq. (3.19) is only valid when the charge window is
sufficiently narrow such that the lateral potential drop within the windowis negligible.
The validity of the discretization method (Eq. (3.14)) has been verifiedwith TCAD simulations using relatively narrow windows of 1μm, in adevice where λ=2.5μm (Wit,i < λ), to construct the potential and fieldresponse of wider charge windows. Some results are shown in Fig. 3.7where a single (base) window response in the linear region of Fig. 3.6c,d(Nit = 1 · 1011 cm−2,Wit= 1μm) enables the reproduction of other responsesthrough a simple multiplication (green dot, Nit = 9 · 1011 cm−2) or summa-tion (red dot,Wit = 5μm). On the other hand, a 5μm window (Wit,i > λ)as a base window (red dot, 3.6c) is not sufficiently narrow for effectiveconstruction using Eqs. (3.14) and (3.19).
48
3.4.M
OD
EL
ING
TH
EIN
TE
RFA
CE
CH
AR
GE
3.4.2 The effect of interface charge on device characteristics
Changes in lateral field, e.g. caused by interface charge, affect the impactionization multiplication (see chapter 4 for details) resulting in a change ofthe subthreshold device I-V characteristics (Fig. 3.7c,d). When the absolutevalue of the lateral field change Eit(x) caused by a non-ideality is as highas the lateral field Ex , local breakdown (red line) at this critical peakfield location will occur. The lateral field for the device treated here is15 V/μm (Fig. 3.1c) and the 1μm wide base interface charge window causesa lateral field change of ∼ 1.3 V/μm. The avalanche breakdown seen fora 1μm wide Nit of 1.2 · 1011 cm−2 (Fig. 3.7d) can be explained, as this is12×1.3 V/μm > 15 V/μm, causing a local critical field peak in Eit(x).
3.4.3 Discretization of Nit and partially depleted modeling
To determine multiplication [2] at each drain bias value in off-state or sub-threshold, the field and potential response at different depletion widths arerequired. This necessitates the modeling of partially depleted drift exten-sions (W < L), which can be done by changing the boundary conditionψ(L,y) = 0 to ψ(W,y) = 0 and applying the discrete convolution of Eq.(3.14) together with Eq. (3.19). Figure 3.8b,c shows a selection of differentboundary conditions and positions (xi) for a single base window of charge,while Fig. 3.8d-g shows the response of the full Gaussian Nit distributionof Fig. 3.1b using Eqs. (3.14), (3.17), and (3.19) at two different depletionwidths (W = 25μm andW = 50μm = L). For any form of discretizationthe narrower the discretization window the better the modeled response.The base discretization window used in Fig. 3.8b-e was 1μm wide for easeof illustration, for better response modeling however, the results shown inFig. 3.8f-g and Fig. 3.9 are obtained using a much narrower base windowwidthWit of 1 nm.
3.4.4 Field distribution of an arbitrary Nit profile
The proposed method is applied to an arbitrary interface charge distri-bution (with both positive and negative Nit) and compared with TCADsimulations. Using the appropriate λ (paragraph 3.3), excellent agreementis achieved (Fig. 3.9a). By adding the field distributions for a virgin case(Evirx , e.g. obtained with the analytical model presented in appendix A) tothe Eit(x) caused by the interface charge, the total field distributions Excan be obtained as shown in Fig. 3.9b. With this resultant field distribu-tion the drain potential can be obtained through integration of the field(VDS = −
∫W0 Ex(x)dx). The subthreshold I-V (Fig. 3.9c) obtained using
the Ex dominated impact ionization multiplication as explained further inchapter 4 [2] shows that interface charge will in fact affect the I-V behavior.In addition changes in I-V characteristics caused by arbitrarily biased sepa-rate field-plates along the drain extension can be obtained by changing the
49
CH
AP
TE
R3.
INT
ER
FAC
EC
HA
RG
EA
ND
EL
EC
TR
OSTA
TIC
S
Figure 3.8: a) Device cross-section illustrating a unit (δ, red arrows) inter-face charge window for laterally partially (W < L) and fully (W = L)depleted drain extensions; b,c) TCAD obtained and modeled uit(x) forpartially and fully depleted drain extensions; d,e) Discretization of theGaussian shaped Nit(x) distribution (see Fig. 3.1) in unit windows (δ’s)of charge (red arrows) with their respective potential (green lines); f) to-tal potential and (g) field (uit(x), Eit(x)) obtained through summation (Eq.(3.14)) of the separate responses (Wit = 1μm) for both the partially (grey,W = 25μm, L = 50μm) and fully (black, W = L = 50μm) depleted case.
field plate potential according to VFP(x) = ψstep(x) =qNit(x)
Cox(paragraph
3.2). Because of this analogy in influence, device structures with separatelybiased field-plates can be used to investigate and or suppress (Eq. (3.2))the influence of interface charge.
50
3.5.C
ON
CL
USIO
NS
Figure 3.9: TCAD simulation and perturbation modeling results for anarbitrary interface charge profile using the device (Fig. 3.3a) with λ =2.5μma) left axis: interface charge profile, right axis: potential response uit(x);b) total (Ex , left axis) and change (Eit(x), right axis) in field response; c)subthreshold I-V behavior. The results obtained for the ideal device areindicated by dashed lines, while the degraded device is indicated by thesolid lines.
3.5 Conclusions
In this chapter a systematic study on the effects of arbitrary parasitic chargeprofiles on the 2-D potential distribution in the drain extension of (gra-dient based) FP assisted RESURF devices is presented. The importanceof the device characteristic length λ in dielectric-interfaced (depleted)semiconductor systems is shown. A powerful charge-response method isintroduced, requiring only Eqs. (3.14), (3.17) and (3.19) for reconstructingthe electrostatic response of arbitrary parasitic charge distribution. Thismethod can be used for optimizing and predicting the subthreshold (chap-ter 4) and off-state (chapter 5) performance of gradient based FP assistedRESURF devices after HCI.
CHAPTER 4SUBTHRESHOLD CURRENT AND
EXTRACTION
Abstract
A methodology for extracting the lateral electric field (Ex ) in thedrain extension of gradient based field-plate assisted RESURF devicesis detailed including its limits and its accuracy. For this study analyticalcalculations and TCAD device modeling corresponding to experimen-tal data are used. From the extracted fields trapped interface chargedistributions (e.g. due to HCI) are obtained. Thus, a new method isintroduced to determine the position and quantity of injected chargesin the drain extension of RESURF power transistors.
The core of this chapter was published in IEEE Transactions on Electron Devices, Vol.62,No.2, [5].
51
52
4.1.IN
TR
OD
UC
TIO
N
4.1 Introduction
For the optimization and understanding of breakdown and reliability inhigh voltage (HV) MOS devices, knowledge of the lateral electric field(Ex) distribution in the extended drain region at reverse bias is essential.In a gradient based field-plate (FP) assisted RESURF device this field isdetermined by the doping, oxide and field-plate construction of the ex-tension (chapter 2). This field can be altered by trapped charge after HCI(chapter 3). The unique effective field shaping in these FP-RESURF devicesoffers the ability to analyze the field and its HCI induced changes. Thenoninvasive extraction of lateral field from measured ID-VDS characteristicscan be used as proposed in [86] and extended in [4]. The extraction method-ology is applicable to the, 1-D like, field expansion (Fig. 4.1c,d) found inthe gradient based FP assisted RESURF devices [2], using either trench orlateral [33, 66, 87–89]) drain extension configurations. A important require-ment is that the extension is longer than 5 times the characteristic length λ(Fig. 4.1c, [4]), with λ (chapters 2 and 3) governed by the semiconductor,e.g. silicon, and oxide thickness.
Figure 4.1a shows a schematic cross-section of the HV SOI device understudy. Since the oxide over the drain extension has generally the samethickness as that of the buried-oxide (BOX) layer, we consider half a crosssection in which the top surface represents the plane of symmetry. At highdrain bias in addition to the thermal leakage (chapter 5) and subthresholdcurrent a current occurs due to impact ionization, as explained in para-graph 4.2. This impact ionization current enhanced by lateral field peaks inEx (Fig. 4.1c,d) leads to increased drain currents (ID), as shown in Fig. 4.1b,which can ultimately lead to premature breakdown. The method proposedby van Dalen et al. as explained in [86], [4] was shown to provide a goodway to locate these Ex non-idealities.
An in-depth analysis of the details and limits of this field extractionmethod was however still lacking. For example, it was not clear how toaccount for the effect of λ on the position to determine the origin of thechange in impact ionization current (paragraph 4.3.A), or why there arediscrepancies in extracted field valleys (Fig. 4.1d, paragraph 4.3.B). Theobjective of this chapter is to provide this analysis through a combinedanalytical and TCAD [50] approach which was calibrated with experimen-tal (HCI) data (chapters 5 and 6). It is also shown how to determine theinterface charge distributions causing the changes in Ex [3].
The chapter is outlined as follows: Paragraph 4.2 presents an overviewof charge-carrier multiplication and the analytical basis for field extraction.Paragraph 4.3 discusses the extraction method and its limiting factors. Para-graph 4.4 discusses for what breakdown voltage range the field extractionmethod is applicable. Paragraph 4.5 presents interface charge distribution(Nit(x)) extraction. While in paragraph 4.6 conclusions are drawn.
53
CH
AP
TE
R4.
SUB
TH
RE
SHO
LD
CU
RR
EN
TA
ND
EX
TR
AC
TIO
N
Figure 4.1: a) Half-width cross-section of the studied device with interfacecharge, source electron current (IS), electron-hole pair generation and mainflow paths [6, 86] indicated in the depleted n-drift extension; b) Subthresh-old source and drain currents vs. drain potential in an optimal (virgin) anda degraded device. The device gate width is 1000μm; c,d) TCAD modeledand extracted lateral fields for the virgin and the hot-carrier degradeddevices; also shown the field expansion for a (fixed ΔW) VDS increase andthe 5 λ location [4]. Note the field peak and valley in the degraded devicecaused by the interface charge.
54
4.2.SU
BT
HR
ESH
OL
DM
ULT
IPL
ICA
TIO
NA
ND
FIEL
DE
XT
RA
CT
ION
4.2 Subthreshold multiplication and field extraction
In this paragraph we explain the core mechanisms of charge-carrier mul-tiplication and the essential concepts of the field extraction methodology.In Fig. 4.2a, an ideal device with a laterally expanding block field Ex , isconsidered. It is assumed that [4]:
(a) an increase in drain current caused by an increase in applied biasΔVDS is solely caused by impact ionization in the additionally createddepleted region.
(b) an increase in depletion width ΔW does not (significantly) affect thefield inside the already depleted region.
This chapter focuses on Impact Ionization (II) currents generated inthe non-reachthrough depletion range, i.e. for those drain-source voltages(VDS) where the depletion width (W) is less than the drain extension length(L). For example, Fig. 4.2b shows thatW < L = 50μm for VDS<730 V. Theproposed methodology is not applicable to the on-state operation (low VDS,high VGS) since then the drain extension is hardly depleted and II is not thedominant source of current.
All TCAD results shown are obtained using Silvaco Atlas [50] standardmodels (at 300 K). The impact-ionization model used is Selberherr’s model[90], with the ionization coefficients determined node by node as a functionof the field in the direction of the current. These models matched multipli-cation changes observed in the measurement data presented in chapters 5and 6 [6].
When the drain of the HV MOS device is biased (VDS > 0 V) and a sub-threshold gate voltage is applied, the injected source electrons (Fig. 4.1a, 4.3)flow along the line of potential symmetry [2, 3]. Here the vertical field isminimal (Ey = 0) and Ex induced generation of electron-hole pairs, by IImultiplication, is dominant [6].
The multiplication factor (M) for electrons is the ratio of these carriersexiting the depleted drain extension, the drain current ID, and those enter-ing the depleted drain extension (at x = 0, Fig. 4.1a), the electron sourcecurrent IS. At the separate back gate contact the generated holes form theback gate current (IBg) with IBg = ID − IS = (M− 1) · IS. Multiplication isgiven by:
M(W(VDS)
)=ID(VDS)
IS(VDS)= 1 +
IBg(VDS)
IS(VDS), (4.1)
whereM is a function ofW which in turn depends on the drain potential[4, 37]. For an accurate Ex extraction, subthreshold gate biasing is essentialas it provides a dominant supply of electrons (Fig. 4.1a) flowing along theabsolute field valley, Fig. 4.3. In this case M is governed by Ex and thethermally generated leakage component which induces a more complexmultiplication mechanism (chapter 5) can be ignored. To study the changes
55
CH
AP
TE
R4.
SUB
TH
RE
SHO
LD
CU
RR
EN
TA
ND
EX
TR
AC
TIO
N
Figure 4.2: a) Schematic representation of the uniform block ( λ = 0) field(left) and corresponding Impact Ionization Coefficient (right) expansionfor a step ΔW induced by an increase in VDS; b) Analytical [3] and TCADobtained multiplication and impact ionization integral (IIint) as a functionof the drain potential (bottom axis) and depletion width (top axis) for avirgin device. Shown is the non reachthrough condition.
in multiplication caused by HCI stress ([6, 91], paragraph 4.5) it is best touse a fixed level carrier supply entering the device (IS). This can be achievedby using a fixed current at a relatively low reverse bias, e.g. 0.1 nA/μmat 50 V, 100 nA (Fig. 4.1b, gate width = 1000μm), for which there is hardlyany multiplication (IS ≈ ID). This avoids having to perform additionalMnormalization due to possible stress induced threshold voltage (Vth) shifts,or temperature related shifts (chapter 6). The chosen subthreshold sourcecurrent should be low enough to prevent Kirk effect like field changes.
The II induced electron current, per unit distance x, used to determineM, is described by [21]:
dIn(x)
dx= αn(x)In(x) + αp(x)Ip(x), (4.2)
where In, Ip are the electron and hole currents, respectively, and αn, αp
the electron resp. hole impact ionization coefficient. The impact ionizationcoefficients describe the amount of electron-hole pairs generated at a certainfield, per unit distance x per entering carrier. For the electric field rangeof interest, in silicon, electron-hole pair generation is mostly caused by
56
4.2.SU
BT
HR
ESH
OL
DM
ULT
IPL
ICA
TIO
NA
ND
FIEL
DE
XT
RA
CT
ION
Figure 4.3: Illustration of the virgin electric field distributions and thesubthreshold source electron path (path 1, Fig. 2.4).
electrons as, αn � αp. In combination with the subthreshold operationwhere In � Ip (at the depletion edge), the hole contribution of (4.2) isneglected (see Appendix B).
The weighted average of αn and αp coefficients α can be describedusing Fulop’s approximation [15]:
α(x) = Afit|E(x)|7, (4.3)
where Afit is a prefactor [4, 86], 1 · 10−34cm6 · V−7, used to fit TCAD(Fig. 4.2b) or measured results. Since it holds here that αn � αp it isassumed that, α ≈ αn [86]. Fulop’s approximation is used as it allows for asimple analytical analysis of subthreshold field extraction. However, formore intricate dependencies, e.g. with temperature and field, the moreaccurate Chynoweth’s-like expressions [14, 92, 93] can be used.
The electron-hole pair generation for a single carrier flowing acrossWis given by the impact ionization integral (IIint) (see Appendix B):
IIint(W) =
W∫0
α(x)dx = ln(M(W)
). (4.4)
This equation is used to relate the measured multiplication as a functionof VDS to impact ionization caused by a single carrier (IIint, Fig. 4.2b). Thisallows an overview of the normalized field induced II, along the full drainextension. A change ΔIIint, as shown in Fig. 4.2b, can thus be utilized tocompare the increase in electron-hole pair generation due to a field changeat any position, or equivalent drain potential, along the drain extension.UsingM and I changes, an increasing amount of carriers flowing alongW
57
CH
AP
TE
R4.
SUB
TH
RE
SHO
LD
CU
RR
EN
TA
ND
EX
TR
AC
TIO
N
is measured requiring normalization, as performed in [86] resp. [4], using:
ΔI
I=ΔM
M= ΔIIint, (4.5)
which can be obtained from Eqs. (4.2) and (4.4).
With the two assumptions at the beginning of this chapter, the fieldsresponsible for the increases in IIint caused by steps in depletion width(ΔW, Fig. 4.2) can be extracted [4, 86]. This is achieved using:
ΔIIint ≈ α · ΔW = Afit|Extr|7 · ΔW, (4.6a)
giving the field extraction equation,
Extr ≈∣∣∣∣(
1Afit
· ΔIIint
ΔW
)∣∣∣∣17
. (4.6b)
WithΔVDS = Extr · ΔW, (4.7)
it holds that
ΔIIint ≈ Afit|Extr|7 · ΔVDS
Extr= Afit|Extr|
6 · ΔVDS, (4.8a)
giving the extracted field as a function of the applied VDS:
Extr =
∣∣∣∣(
1Afit
· ΔIIint
ΔVDS
)∣∣∣∣16
. (4.8b)
The extraction location is found by:
xxtr =ΔVDS
Extr+W + xcr, (4.9)
with xcr a correction parameter that is zero for the ideal block field caserepresented in Fig. 4.2a.
Applying the equations to the measured currents results in the extractedfield as shown in Fig. 4.1b,c. The top and bottom axes of Fig. 4.2b show thelink between voltage and depletion width assuming a constant field Ex .Since this will generally not hold, field extraction on actual measurementsshould be performed using Eq. (4.8b) and (4.9). The next paragraph givesa more detailed analysis on the validity of the initial assumptions and theirrelation to accurate field extraction.
4.3 Field extraction in RESURF devices
In the depleted parts of FP assisted SOI RESURF devices, even ideal ones,a non-abrupt lateral fall-off is present in the electric field (Fig. 4.1c,d) andpotential (Fig. 4.4a), related to the characteristic length λ (chapter 3). Asa consequence, λ determines the extent to which assumption (b) in para-graph 4.2 holds. With increasing λ extraction inaccuracies appear, notpresent in the block field case (Fig. 4.2a, λ = 0).
58
4.3.FIE
LD
EX
TR
AC
TIO
NIN
RE
SUR
FD
EV
ICE
S
Figure 4.4: a) Lateral potential distribution (u(x)) for a virgin device ob-tained from TCAD simulations with λ = 2.5μm for W (cyan), W + ΔW(red) and L (black). Grey dashed line: modeled W versus VDS relation;b) Potential distribution change (Δu) for increment ΔW showing threeregions of change; c) Field distribution change (ΔE) using a smaller ΔW,with the change in drain potential (ΔV) being the area under the curve; d)
Left axis: ΔE in log scale, showing the characteristic e1λ falloff [3]. Right
axis: Impact Ionization Coefficient change for a ΔW showing a 1.8 λ shiftedpeak, with the area under the curve the change in impact ionization integral(ΔIIint).
4.3.1 Constant Field case
The effect of a non abrupt fall off ( λ = 2.5μm) will be analyzed using aconstant field (virgin, Fig 4.1c). These fields are modeled using equationsfor potential distribution as reported in [4, 37] and shown in appendix A,with TCAD extracted values of λ (chapter 3).
From the (quasi-) 2D Poisson equation the non reachthrough potentialdistribution (Fig. 4.4a) of an ideal RESURF device along the line of potentialsymmetry (y=0) is given by (Eq. A.45, [4, 37]):
uW(x) =
⎧⎪⎪⎨⎪⎪⎩−Esatλ
(xλ−
sinh( xλ)
cosh(Wλ)
)x < W < L
−Esatλ
(Wλ
− tanh(Wλ)
)W � x < L
(4.10)
Esat ≈ −BV
L, and u(W) = VDS
59
CH
AP
TE
R4.
SUB
TH
RE
SHO
LD
CU
RR
EN
TA
ND
EX
TR
AC
TIO
N
with Esat the lateral clamping field (15 V/μm, Fig. 4.1c), W the depletionedge, λ the characteristic length, BV the off-state breakdown voltage and Lthe drain extension length. From Eq. (4.10) the depletion width vs drainvoltage relation W(VDS) is obtained. This width (Fig. 4.4a, dashed line)expands nearly linearly [4] for W > 2 λ as the tanh component for u(W) inEq. (4.10) becomes negligible. The depletion width from where the lateralfield is clamped (W ≈ 5 λ, Fig. 1c), and hence the extraction assumption(b) becomes applicable, was also obtained using Eq. (4.10). Utilizing thisW > 5 λ field clamping criterion gives insights on estimating the devicebreakdown voltage ranges across which the field extraction can be applied(paragraph 4.4, [4]).
The changes Δu, ΔE and Δα for a step ΔW are shown in Fig. 4.4b, cand d respectively. These distribution changes form the core parametersnecessary for field extraction (Paragraph 4.2). The non abrupt lateral falloff ( λ �= 0) results in less local ΔE and Δα changes with peak Δα changesoutside the region of depletion expansion (region (i), Fig. 4.4c,d). To analyzethe extraction errors caused by this, the potential difference distributionΔu(x) for a change in depletion width ΔW is:
Δu(x) = uW+ΔW(x) − uW(x). (4.11)
Substituting Eq. (4.10) in Eq. (4.11) results in:
Δu(x) =
⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩
Esatλ sinh(
xλ
)(1
cosh(W+ΔWλ
)− 1
cosh(Wλ)
)(i)
−Esatλ
(x−W
λ−
sinh(
xλ
)cosh
(W+ΔW
λ
) + tanh(
Wλ
))(ii)
−Esatλ
(ΔWλ
− tanh(
W+ΔWλ
)+ tanh
(Wλ
))(iii)
(4.12)
where, the drain extension is divided in three regions:
(i) the depleted region, x < W < L,
(ii) the region of depletion expansion,W < x < W + ΔW < L,
(iii) the quasi-neutral region,W + ΔW � x < L.
Figure 4.4b shows good agreement between TCAD and analytical re-sults for Δu(x) across all three regions. The field change in Fig. 4.4c is thederivative (ΔE(x) = −dΔu(x)
dx) of the potential change. The area under the
curve represents the change in VDS while the slope as plotted in Fig. 4.4d(left axis) shows the characteristic e
1λ fall-off [3].
The lateral (field) position resolution is the highest when the ΔW (ΔV)step is infinitesimally small. Keeping this in mind changes in region (ii)can be neglected for sufficiently small steps (ΔW λ, [3]). In practice theresolution of the measurement equipment will be the determining factor
60
4.3.FIE
LD
EX
TR
AC
TIO
NIN
RE
SUR
FD
EV
ICE
S
for the minimum step size ΔV . If the current (change) is too low for themeasurement equipment, a larger ΔI can be obtained for the same ΔV(ΔW) by increasing the subthreshold current. The current should howeverstill remain low to avoid changes in Ex due to high injection effects.
The change in distribution of generated electron-hole pairs (Δα, Fig. 4.4d)per carrier, for a given ΔW determines the change in impact ionizationintegral ΔIIint (enclosed area Fig. 4.4d), the key parameter for extraction(Eqs. (4.6b) and (4.8b)). This change can be written as:
Δα(x) = αW+ΔW(x) − αW(x), (4.13)
giving
Δα(x) = AfitE7sat ·
⎧⎪⎪⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎪⎪⎩
(cosh
(xλ
)cosh(W
λ)− 1
)7
−
(cosh
(xλ
)cosh(ΔW+W
λ)− 1
)7
(i)
(1 −
cosh
(xλ
)cosh(ΔW+W
λ)
)7
(ii)
0 (iii)
(4.14)
using Fulop’s equation (Eq. (4.3)) with Ex = −dudx
and regions (i), (ii) and(iii) as mentioned previously. The modeled results are shown in Fig. 4.4d,right axis. The increase in ionization integral (ΔIIint) measured for aΔW (orΔV) represents the area under the curve. The peak change in electron-holepair generation does not occur at the edge of the depletion region, wherethe peak change in field occurs (Fig. 4.4c), but some distance before.
Figure 4.5 gives an overview of the shift of the extraction location (theII current origin), between the block field and the ideal RESURF field. Thepeak location of change (dΔα
dx= 0) for the latter is found to be located 1.8 λ
from the depletion edge W. This is because α is strongly dependent onthe absolute field as shown in Eq. (4.3). Consequently a relatively smallfield change at an already high field (Fig. 4.5b) contributes more to theimpact ionization process (Fig. 4.5d) than a relatively large field changeat a low field. This is seen in the realistic devices from the curvature (nonzero λ) in the field near the edge of the depletion region. When relatingthe measured impact ionization integral change (ΔIIint) to the position theshifted peak Δα contribution has to be taken into account to obtain theextraction location xxtr. This (xxtr =W − 1.8 λ) was done for the extractedfield (Eq. 4.6b) shown in Fig. 4.1c. It is of interest that the W = 5 λ fieldclamping criterion (Fig. 4.1c,[4]) can also be interpreted as the (approximate)length of significant Δα contribution as shown in Fig. 4.5d.
4.3.2 The non-constant field case
Because a multiplication change in non reachthrough condition is directlyrelated to a change in the depletion width (Eq. (4.4)), the constant field
61
CH
AP
TE
R4.
SUB
TH
RE
SHO
LD
CU
RR
EN
TA
ND
EX
TR
AC
TIO
N
Figure 4.5: Overview block field vs. RESURF field. a,b) Field expansion forΔW = 1.7μm (≈ 25 V); c,d) Resultant Δα distributions showing 1.8 λ Δαpeak shift from depletion edge with effective length ≈ 5 λ, for λ �= 0 case.
extraction in the previous subsection, was performed by varying ΔW us-ing Eq. (4.6b). This is only useful when the W vs. VDS relation (Eq. (4.10),u(W) = VDS) is known. Since TCAD simulations and measurementsprovide the multiplication as a function of VDS without knowing the corre-spondingW, the extraction using Eq. (4.8b) is more suited.
Field extraction using the ΔVDS based equation (Eq. (4.8b)) is performedon the TCAD obtained I-V characteristics of the (degraded) device, seeFigs. 4.1b and 4.6. This results in the extracted fields shown in Fig. 4.7awith a shift (delay) when applying no correction (TCAD vs. xcr = 0).
Since the peak contribution in the measured impact ionization change,for a step ΔW, was shown to have a 1.8 λ shift (Fig. 4.5d), this correctionis applied. This is insufficient as depicted by the dashed line in Fig. 4.7a.Due to the slower depletion expansion in the initial part of the extension,an additional ≈ 1 λ correction is required, as shown in Fig. 4.7a (solid line).
The required additional shift is inherent to the VDS method, whichattributes measured multiplication changes and their corresponding ex-traction location (Eq. (4.9)) only to laterally expanding clamped fields. Thisis not the case in the initial part of the extension, i.e. pre-field clamping(W < 5 λ, Fig. 4.1c), resulting in the overestimation of extraction locationrequiring the additional (≈ 1 λ) correction. A direct correction for possibleextraction shifts is provided when the extracted field can be linked to aphysical location in the extension such as a LOCOS bird’s beak [6, 86].
62
4.3.FIE
LD
EX
TR
AC
TIO
NIN
RE
SUR
FD
EV
ICE
S
Figure 4.6: Analytically [3] and TCAD obtained multiplication and impactionization integral (IIint) as a function of the drain potential for the non-constant field (degraded) device shown in Fig. 4.1b.
Figure 4.7: a) Extracted field of a degraded device using Eq. (4.8b), showinga shift in extraction position and required position correction (xcr); b)Higher extraction accuracy for a device with smaller λ; c,d) Analysis of Δαat position of highest extraction discrepancy for two values of λ. A morelocalized Δα for smaller λ is shown.
In Fig. 4.7a and b the extracted fields of two devices with different λ’s(in this case: different dielectric thicknesses) are compared. It is seen thatfor a lower λ (Fig. 4.7b) the extracted field, particularly in the field valley,has better overlap. The overlap issues are caused by the non local contri-bution, associated with the λ related lateral fall off, of impact ionizationcaused by minor field changes at field peaks in the already depleted region.Figures 4.7c and d show the corresponding Δα for a ΔV in their respective
63
CH
AP
TE
R4.
SUB
TH
RE
SHO
LD
CU
RR
EN
TA
ND
EX
TR
AC
TIO
N
Figure 4.8: Impact ionization coefficient change (left) and correspondingΔIIint (right) at increasingW (VDS) for; the a) constant and b) non-constantfield distribution case.
field valleys. For a ΔV it is seen that the difference in distribution of theavalanche coefficient (Δα) is less influenced by peaks in the already de-pleted region and is more local for a sharper field fall off (ΔE), i.e. a smallerλ. Attributing this non local (Δα) distribution to a single position (i.e. ΔIIint
value) as done in the extraction methodology results in a flattening ofextracted fields, which is most apparent as an extraction overestimation infield valleys (Fig. 4.1d). For a higher accuracy an iterative method using acombination of measurement, extraction and TCAD verification is needed.
4.3.3 Δα distribution change for increasing VDS
The impact ionization coefficient changes (Δα) shown throughout thischapter were for a single step ΔVDS at a specificW or VDS. Figure 4.8 givesan overview of these distribution changes (gray) at increasing VDS for boththe constant and non-constant field distribution case. The ΔIIint changes(black) corresponding to these Δα ′s are also shown, thereby illustrating theorigin of the measured changes in IIint for increasing VDS (Fig. 4.2b, 4.6).
64
4.4.V
OLTA
GE
RA
NG
EO
FV
AL
IDIT
Y
Figure 4.9: Isoline representation of the Wclamp = 5 λ distribution. Wclampand corresponding minimum (ideal) lateral breakdown voltages are shownas a function of tsi and tox.
4.4 Voltage range of validity
For W = 5 λ as the field clamping criterion (Fig. 4.1c) and the calculatedclamping voltages (Vclamp = u(5 λ), Eq. (4.10)) for a range of differentλ’s an isoline representation is shown in Fig. 4.9 of the minimum (ideal)device breakdown voltages from where extraction is still valid. It shouldbe noted that the λ values in this section are calculated using the analyticalparabolic approximation as presented in chapter 2 and appendix A [2, 37].As discussed in chapter 3 more accurate estimates can be obtained using(numerical) evanescent mode or TCAD obtained λ’s.
For optimized devices the extraction method is valid when L > Wclamp.Figure 4.10 illustrates a model limit overview, for a range of ideal single-sided (SS) RESURF devices. The extension length (L) is chosen for thehighest BV (Esat=Excrit), steepest slope (a) and lowest RON. The solid redline indicates the model’s absolute limit, i.e. the line below which extraction,anywhere in the device drain extension, is not possible. The dashed blueline indicates from where on field extraction will be valid for more thanhalf of the drain extension.
Taking accurate field extraction across more than half of the drain exten-sion as a realistic model limit shows that for a tsi of 0.25μm the model isapplicable to 150 V devices and higher. Applying the extraction methodol-ogy outside the extraction range (L � Wclamp) results in large discrepanciesbetween the field distribution and extracted values as illustrated for the(SS) 50 V device in Fig.4.11.
Paragraph 4.4 was published as part of the Bruges, Belgium, ISPSD’12 proceedings [4].
65
CH
AP
TE
R4.
SUB
TH
RE
SHO
LD
CU
RR
EN
TA
ND
EX
TR
AC
TIO
N
Figure 4.10: LWclamp
vs breakdown voltage for doping gradient based FPassisted RESURF optimized (SS) devices. Three tsi cases are shown with avarying (minimal) tox.
Figure 4.11: Lateral field evolution (solid) and corresponding extractedfield distribution of a (BV) 50V device outside the extraction range ofvalidity. The device tsi = 0.25μm and tox = 0.2μm, with a λ of 0.7μm.
4.5 Interface charge extraction
As discussed in chapter 3 trapped charge (Qit = q · Nit) at the Si/SiO2
interface caused by HCI induces field changes along the drain extension.It is therefore of interest to investigate (interface) charge induced changesusing the presented field extraction methodology.
The inset of Figure 4.12a shows an example IIint vs. VDS evolution asobtained (Eq. (4.4)) from multiplication (M) increases seen [6] for subse-quent (HCI) stress times (modeled by interface charge, Fig. 4.12d): virgincase (t=0), t=t1 and t=t2. The field extraction is performed to obtain the
66
4.5.IN
TE
RFA
CE
CH
AR
GE
EX
TR
AC
TIO
N
HCI induced field response (Fig. 4.12a), i.e. the field difference (Eit), of thevirgin field and the degraded field (Eit = Et1|t2 − Evirgin, solid lines) andbetween the degraded fields themselves (Eit = Et2 − Et1, dashed line). Itis known that the response (uit, Eit, Fig. 3.9a,b and 4.12a) of an arbitrarydistribution of the interface trap density (Nit) can be approximated by theconvolution (denoted as ∗) of responses (uδit Fig. 3.8d-f, Eδit Fig. 3.8g) froma set of interface charges. For the field response this convolution (Eq. (3.16))and its corresponding (bilateral) Laplace [94] transform are:
Eit(x) =[Nit ∗ Eδit
](x) = L−1 {Nit(s)× Eδit(s)} , (4.15)
where the field response to a delta-function-shaped interface charge atposition xi, as shown in Fig. 4.12b and c, is:
Eδit(x) =
⎧⎪⎪⎨⎪⎪⎩Epeaki · cosh(x/λ)
sinh(xi/λ)x � xi
Epeaki · cosh((W−x)/λ)
sinh((W−xi)/λ)x > xi
0 x < 0 ∨ x > W
(4.16)
with Epeaki the peak electric field (Fig. 5c):
Epeaki (Wit) =
qNit
Coxλ
(1 − e−
Wit2λ
),
where Cox is the areal oxide capacitance, xi the position of the delta charge,Wit the discretization width ( λ,[3]) and W the depletion edge. Asdiscussed in chapter 3, the influence of HCI charges on the potential isobtained by integration of the electric field, uit = −
∫Eitdx (Eqs. (3.17)
and (3.19)).The analytical description of the delta response (Eq. (4.16)) combined
with the extracted field responses (Fig. 4.12a) allows the interface chargecausing such a change to be obtained by deconvolution. A straightforwardway to perform this is by deconvolution (inverse filtering) in the s or ωdomain and transforming the result back to the space (x) domain by meansof the inverse (bilateral) Laplace (or Fourier) transform:
Nit(x) = L−1{Eit(s)
Eδit(s)
}= F−1
{Eit(ω)
Eδit(ω)
}for s = jω (4.17)
Transformation to and from the s orω domain is achieved using numericalLaplace or Fourier transform packages. As such, Eq. (4.17) is solved by:
1) translating the analytically described Eδit(x), Eq. (4.16), and extractedEit(x) (Fig. 4.12a) to the ω (or s) domain using a Fast Fourier Transform(FFT) package,
2) performing the deconvolution (simple division) in this domain,
3) transforming the results back to the space domain (Nit(ω) → Nit(x))using an inverse FFT package [95].
67
CH
AP
TE
R4.
SUB
TH
RE
SHO
LD
CU
RR
EN
TA
ND
EX
TR
AC
TIO
N
Figure 4.12: a) Extracted field change (Eit) and field difference (dashedline) from IIint vs. VDS curves (inset) of devices with an unknown interfacetrap density distribution Nit; b) Delta function shaped interface charge atposition xi = 25μm and; c) corresponding field response (Eδit); d) Inputcharge distributions (lines) and extracted interface charge distributions(symbols) from the field changes of (a).
68
4.6.C
ON
CL
USIO
NS
The interface charge distributions, causing the field changes of Fig. 4.12aas obtained using this process, are shown in Fig. 4.12d and show goodagreement between the TCAD (input) and extracted values.
The difference in sequentially extracted fields (Fig. 4.12a, dashed line)and the corresponding extracted interface charge (Fig. 4.12d) show that forsequential subthreshold measurements the additional injected charge canbe extracted. Such sequential measurements provide valuable informationin understanding and modeling how charge injection over time (chapter 6)is related to field and position [6], under given (stress) conditions.
In this chapter a symmetric field oxide (Fig. 4.1a) structure is consideredwith equal top and bottom contribution of Nit to measured changes inthe field. In the case of vertically asymmetric devices (chapter 2) thedifference in oxide capacitance in Eq. (4.16) has to be taken into accountwhen attributing Nit to a particular interface.
4.5.1 Extracting the virgin lateral doping profile
When applied to the (extracted) virgin fields, the Fourier/Laplace basedextraction method, can also be used to obtain the lateral doping profile(ND, cm−3) assuming the doping is fixed along y ( tsi), perpendicular tothe current flow direction. This provides an electrical means to test andoptimize the doping process of (charge) gradient devices. It also allowsthe required doping profiles for any imposed lateral (virgin) field to becalculated. Since the (numerical) deconvolution approach allows for non-constant λ(x) it can be of use when doping profiles for a constant Ex(optimal RESURF, chapter 2) have to be calculated in devices with varyingtsi(x) or tox(x) along the drift extension.
4.6 Conclusions
A study on the extraction of the lateral electric field in the drain extension offield-plate assisted RESURF devices is presented. By analysis of the mecha-nisms causing the measured (ID-VDS) changes, extraction inaccuracies havebeen discussed and methods to interpret and correct for them have beenpresented. A method to extract the interface charge from extracted fieldchanges has been introduced. Together these methods provide a power-ful noninvasive way to extract and analyze hot carrier induced trappedcharge from device ID-VDS characteristics allowing device optimization.The method is shown to be valid for RESURF devices with drain exten-sions larger than 5λ which in practice holds for devices with a breakdownvoltage of 150V and higher.
CHAPTER 5OFF-STATE CURRENT AND
TEMPERATURE DEPENDENCE
Abstract
The off-state leakage I-V characteristics of gradient based FP as-sisted RESURF devices are analyzed and modeled in detail. Electricfield dependencies, the influence of interface non-idealities and thetemperature dependency of different contributing phenomena, suchas thermal generation and impact ionization are treated. It is shownthat via noninvasive off-state leakage characterization the surface gen-eration velocity or trap densities profiles after (high-voltage) stress canbe extracted, and related to HCI charge. For a single extracted profilethe developed model enables off-state leakage and subthreshold I-Vdegradation predictions across a wide temperature range.
The Core of this Chapter was published as part of the San Francisco, IEDM’12 proceedings[6].
69
70
5.1.IN
TR
OD
UC
TIO
N
5.1 Introduction
The main focus of this work has been on the subthreshold behavior ofgradient based FP assisted RESURF devices and how this operating regimecan be used for extracting the field and interface charge distributions(chapters 3 and 4). However, a complete and accurate description ofthe device I-V in off-state condition, i.e. at VGS = 0 V, is still missing.High-voltage (HV) transistors can operate a significant part of their time inthis (VGS = 0 V) condition. Therefore, understanding the off-state leakagebehavior pre and post stress is important. In this chapter we show that:
1) off-state charge carrier generation consists of, bulk generation, interfacegeneration and possibly band to band tunneling components,
2) for describing off state multiplication both lateral (Ex ) and vertical (Ey )impact ionization paths should be taken into account,
3) the influence of drain side interface states manifests itself in both thelow-voltage (thermal generation) and high-voltage (impact ionization)drain bias regimes,
4) the I-V characteristics after degradation can be quantitatively repro-duced with a new analytical device model based on well-establishedtheory,
5) and that this model allows for degradation predictions at differenttemperatures through noninvasive low-voltage scanning at a singletemperature.
5.2 Off-state leakage current model
When the LDMOS is in off-state operation there is a leakage current atthe pn-junction formed between the (p) body/back gate and the (n) drainregion. In this chapter a model describing this pn-junction or off-state leak-age current, including stress induced changes, is developed. Similar to the(semi-on) subthreshold regime, the field distribution plays an integral partin understanding the (off-state) leakage behavior in high-voltage devices.The measured drain leakage current (Ileak) can be described by:
Ileak(VDS) = IGen(VDS)×M, (5.1)
with IGen the total off-state generation current (paragraph 5.3) andM thefield dependent II multiplication factor (paragraph 5.4).
A schematic cross-section and the parameters necessary for leakage cur-rent modeling of the device under study is shown in Fig. 5.1. Using TCADdevice simulations [50] the behavior described by Eq. (5.1) is illustratedin Fig. 5.2. By turning the impact ionization model on (Ileak) and off (IGen)this is shown for a conventional PN− (as introduced in chapter 1, Fig. 1.1a),
71
CH
AP
TE
R5.
OFF-STA
TE
CU
RR
EN
TA
ND
TE
MP
ER
AT
UR
ED
EP
EN
DE
NC
E
Figure 5.1: Schematic cross-section of a typical doping gradient basedHV-SOI FP assisted RESURF (N)LDMOS.
Effective drain extension parameters
Ldrift = 50μm a = 4 · 1019cm−4
tsi = 0.5μm BVDS = 750 Vtox = 3.2μm τg = 1.2 · 10−6s
WGate = 0.1 cm
Table 5.1: Parameters used to simulate and model the device under test [6]
Figure 5.2: Simulated leakage I-V characteristics of various types of pn-junctions. Currents are normalized to maximum ’bulk’ generation currentsand voltages to BVDS.
a junction RESURF (Fig. 1.8a) and a gradient based FP assisted RESURFextension (Fig. 1.8b). The simulated currents are normalized to their respec-tive maximum off-state generation currents (IGen) and the voltages to theirbreakdown voltage (BVDS). As shown in chapter 4 the ideal gradient basedFP assisted RESURF drain extension [37] with graded doping (chapter 2)
72
5.3.D
EP
LE
TIO
NE
XPA
NSIO
NA
ND
CA
RR
IER
GE
NE
RA
TIO
N
has an optimal surface field distribution which uniquely expands laterallywith VDS (Fig. 4.1c, d). Earlier it was shown that for a drain potentialincrease (ΔVDS) the extension depletes almost linearly (W > 2 λ, [4]). Asshown in Fig. 5.2 this results in a more evenly distributed increase in IGen
for the gradient based FP assisted RESURF devices. An in dept analysisof this generation component and its (2-D) relation to the depletion of thedrift extension is given in the coming paragraph.
5.3 Depletion expansion and carrier generation
Pre-multiplication electron-hole pair generation (IGen, Eq. (5.1)) in virgindielectric interfaced devices can be divided according to [96]:
IGen(VDS) = ISGen(VDS) + I
IGen(VDS) + IB2B(VDS), (5.2)
the thermal generation component is split in generation in the depleted sili-con volume (ISGen ) and at the depleted SiO2 interface (IIGen ). Additionallycarriers can also be generated by band to band tunneling (IB2B), which isonly of importance at extremely high fields (>70 V/μm, Fig. 2.8) and willbe treated separately in paragraph 5.6.
5.3.1 Depletion
The distinct depletion expansion of the gradient based FP assisted RESURFdevice extension allows for a modular look at the different contributingthermal generation components. This is schematically illustrated in Fig. 5.3for an applied drain-source voltage (VDS), distinguishing the depletion ofthe silicon volume ( W) from the interface (Wi) [97]. The voltage relationsof these expanding depletion layers (Fig. 5.3f) are given. For the siliconvolume depletion, W :
VDS =aqλ3
εSi
(W
λ− tanh
(Wλ
))(5.3)
with q the elementary charge, a the doping gradient, λ the characteristiclength (chapter 3) and εsi the silicon dielectric constant. This VDS vs Wrelation (Eq. (5.3)) is obtained by solving the 2-D Poisson equation alongthe line of potential symmetry as discussed in chapter 4. The depletedinterface beyond W, with length Wi- W (Fig. 5.3a-e), can be interpreted asthe depletion of a 1-D MOS capacitor (MOSCAP) according to the standardequations. For interface depletion (Wi) in a graded doped device it holdsthat:
VDS ≈q · a ·Wi · tox ·
√2·εSi·ϕb(Wi)
q·a·Wi
εox, (5.4)
with εox the oxide dielectric constant, tox the oxide thickness and ϕb thesurface or built-in potential. Appendix C describes the derivation of this(VDS vsWi, Eq. (5.4)) 1-D interface depletion equation.
73
CH
AP
TE
R5.
OFF-STA
TE
CU
RR
EN
TA
ND
TE
MP
ER
AT
UR
ED
EP
EN
DE
NC
E
Figure 5.3: a-e) Graphical overview of the drain extension depletion profileat different VDS; f) Voltage dependence of the fully depleted depletion layerlength W and interface depletion layer lengthWi.
74
5.3.D
EP
LE
TIO
NE
XPA
NSIO
NA
ND
CA
RR
IER
GE
NE
RA
TIO
N
Distinguishing the interface depletion from full depletion (Fig. 5.3f)allows for separate scanning of different interface degradation related phe-nomena. The (charge) gradient nature of these devices enables a highaccuracy Multi Region DC IV (MR-DCIV) scanning of the dielectric inter-face (Fig. C.1). This is more accurate than the typical MR-DCIV method[98] as the latter is based on devices with constant extension doping andsteps in oxide thicknesses (i.e. gate, STI) only allowing multiple discrete(MOSCAP) interfaces to be distinguished instead of truly scanning it.
5.3.2 Thermal generation
The total generation of electron-hole pairs per second in the depleted siliconvolume (V) is [99, 100]:
IGen =q · ni
τg· V (5.5)
with q the elementary charge, ni the intrinsic carrier concentration and τg
the (effective) lifetime. Net generation occurs when there are insufficientcarriers, as in the depleted volume of the reverse biased extension and thedevice tries to reach equilibrium. The generation lifetime τg characterizesthe average time needed to generate an electron-hole pair due to interacting(multiphonon [96]) thermal lattice vibrations. According to Eq. (5.5) thegeneration current in the fully depleted extension volume (Fig. 5.3) is:
ISGen =q · ni
τg·W · tSi · z, (5.6)
while the generation current along the additionally depleted interfacevolume (> W, Fig. 5.3) is:
IIGen =q · ni
τg· (Wi −W) · 2
∫Wi
Wtidx
Wi −W· z, (5.7)
with z the device’s silicon layer depth or gate width (WGate, Fig. 5.1) andti the interface depletion thickness (Fig. 5.3a). The latter is obtained usingdepletion as seen in a graded doped 1-D MOSCAP (appendix C).
Temperature dependence
The total thermal generation is strongly dependent on the available carri-ers that can generate additional electron-hole pairs, this is related to theintrinsic carrier concentration (ni). The intrinsic carrier concentration has astrong positive temperature dependence. The IGen (Eq. (5.5) temperaturedependence can be modeled by including the ni vs. temperature relationin Eq. (5.5) as described by [101]:
ni(T) = 5.29 · 1019 ·(T
300
)2.54
· exp(−6726T
). (5.8)
75
CH
AP
TE
R5.
OFF-STA
TE
CU
RR
EN
TA
ND
TE
MP
ER
AT
UR
ED
EP
EN
DE
NC
E
Figure 5.4: Schematic illustration of thermally generated carriers (redspheres) and the (electron) ionization paths in the drain extension ofthe RESURF device during off-state operation. Two main paths are dis-tinguished compared to the single path (1) for subthreshold operation(Fig. 4.3).
5.4 Off-state multiplication
In chapter 4 it was shown that Eq (4.4),M = exp(IIint), is most suitable forcalculating pre-breakdown multiplication (M). The results in this chapterhowever are based on [6] where (simulation and measurement) valuesare fitted to the more generally used relation for the multiplication factor(appendix B):
M =1
1 − IIint. (5.9)
The off-state ionization paths along which multiplication occurs are morecomplex than those for the subthreshold case. This is because thermallygenerated carriers are formed across the complete depleted volume (Fig. 5.4)instead of only along the potential line of symmetry (see chapter 4, Fig. 4.3).Therefore in case of leakage multiplication there are two main (electron)ionization paths (Fig. 5.4):
1) low Ex field but longest path from source to drain along the potentialline of symmetry,
2) extremely high Ey but short path from the Si/SiO2 interface to thecenter of the Si.
As discussed in chapter 2, to determine the off-state breakdown theimpact ionization integral for electrons along these lateral and vertical
76
5.4.O
FF-STAT
EM
ULT
IPL
ICA
TIO
N
Figure 5.5: The calculated II integral andM values along the different pathsare visualized for the ideal case.
multiplication paths are:
IIxint =
∫W0An · exp
(−Bn
Ex(x)
)dx (5.10)
respectively
IIyint =
∫ 12 tSi
0An · exp
(−Bn
Ey(W)
)dy (5.11)
with An = 7.03 · 105cm−1 and Bn = 1.47 · 105Vcm−1 [52] the (silicon) co-efficients at room temperature. Figure 5.5 shows the ionization integraland corresponding multiplication along these separate paths for the deviceunder study (Fig. 5.1). The path giving the largest II integral becomes dom-inant for the off-state avalanche multiplication. For the device analyzed thetransition from path 1 to path 2 dominance is seen at around VDS = 400 V.
Temperature dependence
Multiplication through impact ionization is caused by high energy carriersthat generate additional free carriers through (lattice) collisions. For anincreasing mean free path between collisions the average accelerationlength and resultant carrier velocity rises, hence increasing multiplication.Since increased lattice vibrations at increasing temperatures reduces themean free path (i.e. carriers lose their kinetic energy more easily) impactionization has a negative temperature dependence. As proposed in [92],this temperature dependence can be modeled by a linearising coefficientBn used in equations (5.10) and (5.11) according to 1:
Bn(T) = 1.29 · 106 + 0.61 · 103T (5.12)
1Equation (5.12) is modified w.r.t. [92] to fit the Bn of [52] at T= 300K
77
CH
AP
TE
R5.
OFF-STA
TE
CU
RR
EN
TA
ND
TE
MP
ER
AT
UR
ED
EP
EN
DE
NC
E
Figure 5.6: Analytical, simulated and measured leakage current compari-son of a virgin device. a) Linear scale. b) Log scale comparison at differenttemperatures. The B2B tunneling component [62] has also been shown.
5.5 Virgin leakage current
As illustrated in Fig. 5.6a to obtain the leakage I-V behavior, the carriermultiplication (Fig. 5.5b) is applied to the thermal generation current ac-cording to Eq. (5.1). Good agreement (Figure 5.6a, b) has been obtained fora wide temperature range between the analytical, TCAD-simulation andthe experimental I-V data. Since increased temperatures increase thermalgeneration (IGen,) but also reduce the multiplication (M) these oppositedependencies are key in understanding and analyzing the off-state I-V(and breakdown) behavior. Figure 5.6b shows an increase of the thermalgeneration current while the multiplication reduces with temperature. Thelatter is observable in the decreasing slope of Ileak vs.VDS (> 600 V) forincreasing temperatures. Finally for (thin) SOI/Trench devices the hightemperature off-state leakage will be drastically lower than their bulk-Si
78
5.6.B
AN
DT
OB
AN
DT
UN
NE
LIN
GG
EN
ER
AT
ION
Figure 5.7: Modeled leakage curves of a B2B generation limited device(Solid). Dashed lines indicate the non B2B limited case of Fig. 5.6b.
counterparts. This is the case because of the scaling of thermal generationcurrent with the thickness of the silicon layer (Eq. (5.6)), see also [102].
5.6 Band to band tunneling generation
It was mentioned in chapter 2.3.2 that sufficiently high (vertical) electricalfields can cause a tunneling generation component. The equations andparameters used to calculate this component and its (minimal) temperaturedependence have been taken from [62]. The tunneling carrier generationrate is given by:
Gbbt = B0E52 e
−F0E (5.13)
with the total band-to-band (B2B) tunneling generation current across the(fully) depleted drift extension given by:
Ibbt = qz
∫W0
∫ 12 tsi
− 12 tsi
Gbbt
(E(x,y)
)dydx (5.14)
with E the (absolute) field and B0 and F0 fitting parameters. The test de-vice is designed such that the B2B tunneling component is sufficientlysuppressed (Fig. 5.6b). The B2B tunneling component only becomes ap-parent at 0 ◦C and below while it is overshadowed at higher temperatures.This is the case since only a small part of the depleted silicon volumecontains fields that fall within the tunneling field range (Fig. 2.8a, [61, 62])of E > 70 V/μm (Fig. 5.4). The resulting Ibbt as described by Eq. (5.14) istherefore minimal (Fig. 5.6b). As explained in Chapt. 2.3.2 for a reducedoxide thickness a larger part of the vertical potential will drop in the silicon
79
CH
AP
TE
R5.
OFF-STA
TE
CU
RR
EN
TA
ND
TE
MP
ER
AT
UR
ED
EP
EN
DE
NC
E
Figure 5.8: Influence of drain side located interface damage on the off-statethermal generation using TCAD device simulations. An increase in surfacegeneration (sg) results in an increase of ITotGen. Different sg profiles result indifferent shapes of the I-V curves.
resulting in increased vertical silicon fields (Ey ) and therefore B2B genera-tion. For example Fig. 5.7 shows that the tunneling generation increasessubstantially when reducing tox to 1.6μm, resulting in a tunneling limitedbreakdown.
Temperature dependence
The temperature dependence is included in F0 [62] in Eqs. (5.13) and (5.14)and is related to the temperature dependent narrowing of the band gap.Figure 5.6b shows that the temperature dependence of Ibbt is minimalcompared to that of thermal generation and multiplication. The lack of tem-perature dependence seen at the measured leakage current hump around200 V at 25 ◦C shown in Fig. 5.6b, is attributed to a local B2B tunnelingeffect at the thinner oxide part of the LOCOS field oxide (Fig. 5.1). Note thatthis is not due to the (highly temperature dependent) interface generation,as discussed in the coming paragraph.
5.7 Interface charge carrier generation
Similar to the thermal generation of free carriers in depleted silicon latticevibrations (phonons) at the silicon interface free additional carriers. Since adamaged interface more easily releases carriers via trap sites an increasein (thermal) carrier generation is observed after interface degradation[96]. Charge injection as discussed in chapter 3 and 4 could be a cause ofthis type of interface degradation. In those chapters the injected chargewas shown to affect the multiplication in the fully depleted parts of theextension. However, there will also be an increase in thermal generation atthe additional interface generation centra, as soon as the interface at thedamaged location is depleted. For drain-side localized interface damage
80
5.8.D
EG
RA
DE
DL
EA
KA
GE
CU
RR
EN
T
this depletion separation (Fig. 5.3f) results in the generation part of theleakage current increasing at a relatively low, and multiplication at a higherVDS with the onset and shape of these depending on the position andshape of the interface charge distribution (chapter 3) or surface generationvelocity (sg) profiles (Fig. 5.8). The surface generation velocity describes thevelocity at which carriers, generated at interface traps, leave the interface[96]. For positive trapped charge this can be described as:
sg = σpsvthNit (5.15)
with vth the thermal velocity (cm/s), Nit the interface trap density (cm−2)and σps the interface trap capture cross section (cm2). The capture crosssection is strongly dependent on the type of interface and the defects. Theused value of σps (= 2 · 10−17cm2) was obtained by fitting the experimentaldata [6] and matches with that of trapped holes as discussed in [96].
The amount of carriers thermally generated per second (Fig. 5.8b) in adepleted drift extension with degraded interface is:
ITotGen = qni ·(
1τg
· V + stot ·A)
(5.16)
with
stot =
∫Wi
0 sgdx
Wi
, (5.17)
and the surface area:A =Wi · z. (5.18)
Interface depletion Wi as a function of VDS (Fig. 5.3f) has been obtainednumerically from Eq. (5.4) derived in Appendix. C. The thermal generationin the depleted volume (paragraph 5.3.2) is considered to be fixed, i.e. nodegradation in the silicon depletion layer itself, while that of the interfacechanges with degradation. Hence, the generation profile and equivalenttrap density can be extracted from this change (Fig. 5.8b→ Fig. 5.8a). Thismethod, albeit less accurate, is useful for extracting drain side located Nit
at relatively low voltages instead of the higher, potentially stress inducing,voltages required for the lateral electric field extraction in subthresholdoperation (chapter 4).
5.8 Degraded leakage current
Combining the techniques discussed in this chapter and the former chap-ters 3 and 4, the influence of interface traps on thermal generation andmultiplication can be analyzed and modeled. Figure 5.9 illustrates both thechanges in leakage and subthreshold behavior at T = 50 ◦C for a Gaussianshaped Nit distribution and its corresponding sg profile (Eq. (5.15)) usingthe developed models. In off-state the thermal generation ’kink’ seen inFig. 5.9b is due to this sg change.
81
CH
AP
TE
R5.
OFF-STA
TE
CU
RR
EN
TA
ND
TE
MP
ER
AT
UR
ED
EP
EN
DE
NC
E
Figure 5.9: Overview of the leakage and subthreshold current at T = 50 ◦Cfor a degraded device using the developed models; a) Gaussian Nit distri-bution (left) equal to the one used in chapters 3 and 4, with correspondingsurface generation distribution (right); b) Subthreshold source current(VGS �= 0 V, chapter 4) and off-state thermal generation current (VGS=0 V,chapter 5); c) Ionization integrals calculated along the key (Fig. 5.4 resp.Fig. 4.3) ionization paths; d) Multiplication corresponding to the two oper-ating conditions; e) Resultant leakage and subthreshold I-V .
As seen in Fig. 5.9b the subthreshold source current is significantlylarger than the leakage current. For this operating condition the maincontributing impact ionization path is along the line of potential symmetryas discussed in chapter 4. The dashed line (path 1) of Fig. 5.9c and d isthe calculated ionization integral and corresponding multiplication along
82
5.8.D
EG
RA
DE
DL
EA
KA
GE
CU
RR
EN
T
this (subthreshold) path. The solid line in these figures shows the (off-state) multiplication (Fig. 5.9d) along the largest of the lateral (path 1)and vertical (path 2) impact ionization paths (Fig. 5.9c). Applying themultiplication (Fig. 5.9d) to the corresponding subthreshold source andthermal generation currents (Fig. 5.9b), using Eqs. (4.1) resp. (5.1), results inthe (modeled) drain currents of Fig. 5.9e. Thus, this illustrates how a singleinterface trap distribution (Fig. 5.9a) influences the device I-V behaviordifferently for off-state leakage and subthreshold operating conditions.Measurement results showing this difference in behavior are treated inchapter 6.
Increased thermal generation under high temperature operation canresult in the off-state leakage component, influenced by both lateral andvertical multiplication, to be of the same order as the subthreshold sourcecurrent. In these high temperature situations the lateral field extraction,using subthreshold measurements (chapter 4), requires the leakage I-V(VGS=0 V) at the elevated temperature to be measured and subtracted fromthe subthreshold I-V (VGS �= 0 V). As will be shown in chapter 6 this isdone to obtain suitable multiplication values for field extraction influencedonly by the lateral field.
5.8.1 Absolute field change and multiplication
Till now the modeled vertical impact ionization rate has been slightlyoverestimating multiplication along the vertical path. This is the case sincein Eq. (5.11), for modeling convenience, the vertical field was used insteadof the the absolute field. The actual ionization path is along the absolutefield (black, Fig. 5.10)
Eabs =√E 2x + E 2
y. (5.19)
This field does not go to 0 V/μm as Ey (green, Fig. 5.10) but has a minimum(valley) caused by the horizontal field (red, Fig. 5.10). Therefore, eventhough Ey does not change due to interface charge (chapter 3), a changein the lateral field will result in a change in absolute field and as such willstill influence vertical ionization. Consequently, the vertical multiplication:
1) reduces where the lateral field increases (cyan arrow, Fig. 5.10),
2) increases where the lateral field decreases (red arrow, Fig. 5.10).
Since this is an effect that happens across the lowest parts of the (vertical)field and across a short vertical distance, the effect on multiplication is min-imal when modeling the leakage I-V . The lateral multiplication increase(subthreshold operation) and vertical multiplication decrease (off-stateoperation) due to the lateral field change can however be observed dur-ing device stress cycles that track the drain current at fixed VDS. Devicestress measurement showing the difference in subthreshold and off-statemultiplication due to (lateral) field changes are shown in the upcomingchapter.
83
CH
AP
TE
R5.
OFF-STA
TE
CU
RR
EN
TA
ND
TE
MP
ER
AT
UR
ED
EP
EN
DE
NC
E
Figure 5.10: Schematic representation of the absolute (Eabs, black), vertical(Ey , green) and lateral (Ex , red) field of a degraded device. Shown aretwo different ionization paths of which carrier multiplication along thesevertical paths is influenced by a lateral field change.
5.9 Conclusions
As this was not previously done, a new model has been developed for gra-dient based FP assisted RESURF power devices that allows for quantitativemodeling and analysis of the off-state leakage I-V across a wide tempera-ture range. The effect of interface damage is investigated showing that thestress-induced damage affects both the low-VDS leakage current and thehigh voltage breakdown behavior. Via noninvasive low-voltage scanningonly, the model enables the surface generation velocity profile and relatedinterface charge of degraded devices to be extracted. As such the modelallows for leakage I-V predictions of degraded devices across a largerthan measured I-V and temperature range. Combined with lateral fieldextraction and subthreshold modeling (chapter 4), a detailed overviewof hot carrier induced degradation changes has been made. Thereforethe necessary insights and tools for in depth electrical characterization ofdegradation in charge gradient based RESURF devices is provided.
CHAPTER 6MEASUREMENTS AND STRESS
ANALYSIS
Abstract
Degradation phenomena and changes in I-V characteristics ofgradient based FP assisted RESURF devices caused by high voltageoff-state and subthreshold stressing are investigated. The device degra-dation is studied using a repeated stress-characterize-stress procedure.A set of accelerated stress procedures is introduced and analyzed us-ing the developed subthreshold and off-state leakage theory of theprevious chapters.
Parts of this Chapter were published in the San Francisco, IEDM’12 proceedings [6]
85
86
6.1.IN
TR
OD
UC
TIO
N
Figure 6.1: A scanning electron microscope (SEM) lateral cross section ofan SOI based gradient doped field-plate assisted RESURF device ([104]).The different regions are indicated while a part of the drain extension hasbeen removed for clarity.
6.1 Introduction
Field-plate (FP) assisted RESURF power devices in Silicon on Insula-tor (SOI) (Fig. 6.1) provide a cost-effective solution for monolithic inte-gration (Fig. 6.2) of high-voltage switching and low off-state leakage acrosslarge operating temperature ranges. They are applied in several marketsranging from power conversion integrated circuit (IC)’s (adapters) to light-ing solutions such as compact fluorescent lamp (CFL) light control IC’sand LED drivers [103]. Since ambient operating temperatures for lightingsolutions can vary significantly and LEDs have intrinsic lifetimes in the20-30 years range, reliability demands for the integrated high voltage tran-sistors are stringent. In particular the off-state (leakage) reliability [91] isa key concern given the low duty cycle in certain LED mission profiles.For sound understanding and subsequent prediction of device reliability,knowledge of the degradation phenomena and their acceleration factors isrequired.
This chapter provides initially obtained measurement results for off-state and subthreshold degradation including their analysis using thecharacterization methods developed in previous chapters. To reduce stresstimes, a set of accelerated stress procedures is introduced using high tem-peratures in the off-state and increased source currents in the semi-on(subthreshold) state. Finally the origin of the differences in stress behaviorand how to interpret them are explained.
87
CH
AP
TE
R6.
ME
ASU
RE
ME
NT
SA
ND
STR
ESS
AN
ALY
SIS
Figure 6.2: Example of a driver IC with integrated, SOI based gradientdoped field-plate assisted RESURF power transistors [105]. The red dashedline illustrates the size difference between the (two) power transistors andthe rest of the low-voltage IC.
Figure 6.3: The device under test (DUT) used throughout this chapter withthe different available terminals indicated. The FP connection is internallyshorted to the source. The red line indicates where a cross section such asFig. 6.1 can be obtained for this ’racetrack’ type device layout. The devicehas a BV of 750 Van Ldrift of 50μm andWGate of 1 mm, see also table 5.1.
6.2 Stress procedure
Using a stress-characterize-stress procedure the device under test (DUT,Fig. 6.3) introduced in chapter 5, table 5.1 was analyzed. The DUT has agate width of 1 mm, and a drift length of 50μm. During the (DC) stresscycle the device was biased at a fixed VGS, VDS and temperature while thedrain current was monitored over stress time. After set time intervals thestress procedure was interrupted to measure the ID-VGS and ID-VDS char-acteristics at fixed or different temperatures [6]. Subsequently from theseI-V characteristics, changes in Vth, RON, off-state leakage and subthresholdbehaviour were obtained and analyzed.
88
6.3.SP
EC
IFICO
N-R
ESISTA
NC
EA
ND
TH
RE
SHO
LD
VO
LTAG
E
As previously mentioned one of the benefits of (thin) SOI high-voltagedevices is their low off-state leakage currents (paragraph 5.5). This lowcurrent can however pose a problem for the measurements. This is the casebecause equipment that can supply voltages in the 1 kV range while stillbeing able to measure (changes in) currents in the low pA range (Fig. 5.6b)are difficult to find, expensive and likely not readily available for long termstress measurements.
Therefore, it was decided to bias the drain potential with a high-voltage(> 1 kV) supply with a ’low’ accuracy source measurement unit (SMU)while monitoring the incoming currents at the other low-voltage terminals(e.g. gate, source, backgate, field-plates) using high accuracy SMUs. Hence,the drain current can then be accurately measured by taking the sum of all(accurately) measured incoming currents.
To bias the high drain potentials presented in this work a Keithley 2410,rated at 1.1 kV maximum output voltage was used. All other (low-voltage)terminals were measured using the medium power SMU’s of the Agilent4155, with a minimum current measurement range of 10 fA.
6.3 Specific on-resistance and threshold voltage
From the measured ID-VGS characteristics (Fig. 6.4a, [6]) the thresholdvoltage [106] and on-resistance (Eq. (1.6), table 5.1) can be determined.
Figure 6.4b shows the specific on-resistance of a device similar to thethe DUT (≈ 10Ω · mm2, [105]) and its position with respect to the 1-Dsilicon (chapter 1) and graded doped (chapter 2) RONA-BV limit. As thisis a partially optimized lateral graded doped device its position is lowerthan the 1-D Si limit but still higher than theoretically possible for anoptimized device of its type. Since the adverse influence of Hot-Carrier(HC) degradation can be restrictive for further optimization towards thistheoretical limit, insights in the different HC degradation mechanisms areessential.
The threshold voltage is determined by the channel region, while RON isgoverned by the current flow in the center of the quasi-neutral drift region.These regions are both located away from potentially HC degraded drainextension interfaces. In [6] it was therefore shown that these measuredon-state device characteristics, i.e. RON and Vth, are not affected by thehigh VDS, off-state or subthreshold stressing discussed in the followingparagraphs. However, off-state breakdown and its strong relation to thedrain extension electric field distribution (chapters 2, 3 and 5) will beinfluenced by HC injection. Therefore, although RON is not affected, chargeinjection can cause a reduction in BV and a shift in the device’s RONA-BV relation (arrow Fig. 6.4b). Further discussion on the off-state leakagedegradation is given in the following sections.
89
CH
AP
TE
R6.
ME
ASU
RE
ME
NT
SA
ND
STR
ESS
AN
ALY
SIS
Figure 6.4: a) Measured device ID-VGS curve. b) The specific on-resistance(RONA) and its place compared to different RONA-BV limits. The arrowindicates possible BV reduction due to HC stress. Note that RONA is notincreased during stressing.
Figure 6.5: Measured off-state leakage I-V degradation for increasing off-state stress (VGS=0 V, VDS=650 V) times. The dashed line indicates thethermal generation component ITotGen (Fig. 5.8).
6.4 Off-state leakage degradation
The DUT was off-state (VGS=0 V) stressed at T=50 ◦C, VDS=650 V and charac-terized at fixed time intervals. In Fig. 6.5 the off-state leakage characteristicsat t1=10, t2=48 and t3=96 hours are shown. The measured off-state leakagedegradation changes are as expected from the surface generation (sg) andinterface charge (Nit) theory developed in chapter 5 (see Fig. 5.9). Themeasured ’low’ voltage leakage more than doubles due to increased sur-face generation (sg) at the high voltage HC degraded interface [6]. Theinfluence of the charge (Nit) accompanying this HC degraded interface canbe identified by analyzing the changes in (Ey) multiplication seen at highVDS. This voltage separation of sg and Nit influence from a single drain
90
6.5.O
FF-STAT
EST
RE
SSA
CC
EL
ER
AT
ION
Figure 6.6: a) Measured increase in ’low’ VDS leakage current (≈ inter-face generation rate, chapter 5). b) Extracted surface generation velocity(obtained by ’inverse’ modeling, see Fig. 5.8).
side located degraded interface was treated in detail in chapter 5 and isessential for the off-state degradation analysis presented throughout thischapter.
Using the methods of chapter 5 the stress induced sg increase seen inthe low VDS range (Fig. 6.6a) is analyzed. Since multiplication is minimalat low VDS (IGen ≈ IvirD , Eq. (5.5)), sg profile extraction is performed bysubtracting the measured virgin leakage current from the degraded leakagecurrent. This only leaves the increase in generation rate originating fromthe degraded interface (Eq. (5.16)). From these relations, the sg profile(Fig. 6.6b) is extracted using the quadraticWi vs. VDS relation to determinethe interface degradation location (chapter 5, Eq. (5.4)). As explained inappendix C a slight offset is possible in these extracted profiles due tothe injected charge influencing the depletion layer along the degradedinterface.
6.5 Off-state stress acceleration
As seen from the stress times in the previous section off-state stressing,with its low current levels, can be time consuming. Assuming that HCdegradation is only dependent on the total externally forced dissipatedpower (=Istress · Vstress
DS ) over stress time and the stressing voltages arewithin the same range (here 650 V - 675 V), then it would be expected thatthe degradation is dependent on the total charge flown, i.e. the total currentflown over time. Under these simplified conditions stress acceleration ispossible by increasing the stress current. To achieve this one can:
a) increase the temperature,
b) increase the source current (e.g. by increasing VGS).
91
CH
AP
TE
R6.
ME
ASU
RE
ME
NT
SA
ND
STR
ESS
AN
ALY
SIS
Figure 6.7: a) Measured off-state leakage I-V degradation for increasingoff-state stress times at an elevated temperature of T=150 ◦C. b) Measuredsubthreshold I-V (grey) and the corrected ID-Ileak curves.
It is however important that under accelerated stress conditions themechanism responsible for degradation can still be related to realistic off-state degradation situations. The coming sections will discuss the twoacceleration cases mentioned above, analyze their results and address theirlimitations.
6.5.1 Elevated temperatures
A comparison between the (virgin) current levels of Fig.6.5 and Fig.6.7ashows that an increase in temperature from T=50 ◦C to 150 ◦C results in anapproximately 100x increase in (stress) current. This is due to the strongpositive temperature dependence of the thermal generation component inoff-state leakage as explained in chapter 5. Under these increased off-statestress current conditions accelerated stressing at T=150 ◦C and VDS=675 Vwas performed for 27.5 hours (Fig. 6.9).
Besides the off-state characterization shown in Fig. 6.7a subthresholdcharacterization was also performed. As discussed in chapter 4, for easeof comparison across temperatures and degradation, a fixed subthresholdsource current of 100 nA at 50 V was adopted in all subthreshold relatedmeasurements throughout this chapter.
High temperature field extraction
For the elevated temperature (T=150 ◦C) situation of Fig. 6.7b performinglateral field extraction requires that the leakage I-V curves be measured(Fig.6.7a) and subtracted from the subthreshold I-V curves (Fig.6.7b, grey).As explained in chapter 5.8 it is the resultant ID-Ileak curves that were usedfor lateral field extraction. Due to the injected/trapped interface chargeat the Si/SiO2 interface (chapter 3) an increase in multiplication (IS →ID-Ileak) is observed. From these Ex induced subthreshold multiplicationchanges, the lateral field distribution was extracted employing the methods
92
6.5.O
FF-STAT
EST
RE
SSA
CC
EL
ER
AT
ION
Figure 6.8: Extracted lateral field Ex using the ID-Ileak subthreshold curvesshown in Fig. 6.7b. For convenience sake two voltage step sizes were usedand a lateral position correction of xcr=2.8 λ is performed (chapter 4).
presented in chapter 4. This chapter also explains why only a single (Ex)induced kink is seen in the (corrected) subthreshold situation compared tothe two (sg resp. Ey induced) kinks seen in the off-state (chapter 5) case.
In Fig.6.8 it is seen that the extracted fields locally increase and saturateat the drain side [91]. This increase can be attributed to the large verticalfields at high VDS, directed towards the interface and its related accelerationand injection of (hot) holes ([76], chapter 3).
Since multiplication is reduced at elevated temperatures and the fieldextraction is based on the measured multiplication change for a step ΔVDS
(chapter 4), the limited accuracy of measurement equipment, and smallΔVDS’s may result in extraction noise. An example of such extractionnoise is seen in Fig. 6.8. To remedy this we seek a voltage step size, ΔVDS,that gives the highest lateral extraction accuracy while still being able toaccurately measure the source to drain current (multiplication) changes.Measurement solutions for multiplication changes that are too small are:
1) increasing the voltage step size ΔVDS,
• Pro: reduced characterization time.
• Con: decreased lateral extraction resolution (chapter 4).
2) lowering the characterization temperature,
• Pro: increased carrier II for a given ΔVDS (chapter. 5)
• Con: setup complexity and increased characterization times.
3) increasing the (subthreshold) source current.
• Pro: increased amount of carriers to multiply for a given ΔVDS
• Con: increased characterization induced stressing for given time
It is important that each of the method’s pros and cons are taken into ac-count when deciding on the subthreshold (field extraction) characterization
93
CH
AP
TE
R6.
ME
ASU
RE
ME
NT
SA
ND
STR
ESS
AN
ALY
SIS
Figure 6.9: a) Drain leakage current evolution vs. stress time. b) Stressbehavior before and after (characterization) stress interruptions. Stressingis performed for periods 30 min followed by stress stop periods of 3 hours.
methodology. This is the case because redistribution of injected chargeduring stress stop periods and characterization itself might substantiallyinfluence the stress characteristics and possibly reliability predictions basedon them (paragraph 6.6).
Off-state leakage current vs. stress time
During the analysis of the (drain) leakage current evolution over stress time(Fig. 6.9a) a current increase (black arrow) followed by a saturation phase(green arrow) was observed. Under the accelerated conditions at T=150 ◦Cthe saturation point was reached in around 10 hours. For comparisonthis point, took 96 hours to reach for the T=50 ◦C case as shown in Fig. 6.5.Given the 100x increase in leakage (stress) current at T=150 ◦C the 9x shorterstress time is far less than expected from a straightforward total chargeflown perspective, especially considering the slightly higher (650 V vs.675 V) stress voltage.
The interface is degraded due to (Ey) field accelerated holes (chapter3). It is the inverse temperature dependence of (Ey induced) II causing areduction in off-state leakage degradation as temperature increases. This isbecause a reduction in II implies that the accelerated (hot) holes degradingthe interface (on average) will posses less kinetic energy.
Stress intervals of half an hour followed by a 3 hour period of no stress-ing, at the end of which characterization was performed, were used. Thelong stress stop periods were necessary to make sure that during character-ization only the influence of trapped or fixed charge is characterized. Here,the trapped charge is part of Si/SiO2 injected mobile charge that does notdetrap during the stress stop period. Figure 6.9b shows the stress currentbehavior before stopping and after resuming (DC) stressing. To understandthis behavior one needs to know the dominant mechanism responsiblefor the current measured over time. Since an off-state leakage current at
94
6.5.O
FF-STAT
EST
RE
SSA
CC
EL
ER
AT
ION
VDS=675 V is measured, Ey multiplication will dominate the measuredcurrent behavior (chapter 5, Fig.5.9).The measurements indicated that theHC injected charge resulted in a drain side Ex increase (Fig. 6.8). Thislateral field peak increase will result in a reduction in Ey multiplication,as explained in paragraph 5.8.1. It can be hypothesized that it is this Eymultiplication reduction causing the observed decrease in drain currentseen in Fig. 6.9b.
When stressing was resumed after the 3 hour stress interrupt an increasein the measured drain current is observed (Fig. 6.9b). During the stressprocess positive mobile charge is injected which subsequently damages theinterface. During these periods in which stressing is halted (part of) thepositive mobile interface charge will detrap, no longer screen and thereforeexpose the additionally degraded interface. The increase in surface gen-eration (sg) along these damaged interfaces (chapter 5) manifests itself asa jump in the drain current in Fig. 6.9b. In the saturated part of the stresscurve this jump is not seen, indicating a saturation of interface damage andits increased surface generation. The slight overall decrease in current overtime observed in this saturation region (Fig. 6.9a) can be attributed to in-creased amounts of trapped charge that either reduce the Eymultiplicationor that slightly screen the damaged interface thereby reducing thermalgeneration.
6.5.2 Increased subthreshold source current
To accelerate the degradation process a positive gate potential was used toincrease the (source) stress current over time. Since we are interested in off-state degradation, stress acceleration was performed in the ("low power")subthreshold or semi-on regime. Direct current (DC) stressing in the highpower VGS>Vth regime was avoided as this is mainly an (AC) operatingcondition only present for short periods of time when switching from theoff (VGS=0 V, VDS=high) to the on-state (VGS>Vth, VDS=low). In this highpower regime reliability issues related to self heating [49, 107], which fallbeyond the scope of this work, can start playing a role. Therefore duringthe increased source current acceleration tests a subthreshold (0<VGS<Vth)criterion should be employed. The (t=0) subthreshold stress criterionadopted in this work was ID=5μA for VDS=650 V at T=25 ◦C (Fig. 6.10).This t=0 current is 5000x that of the current levels shown in Fig. 6.5 and 50xthat of the current levels shown in Fig. 6.7a.
Subthreshold current vs. stress time
The subthreshold current evolution over stress time (Fig. 6.10a) showsa current increase (black arrow) followed by a saturation phase (greenarrow) and finally runaway failure (red arrow). Under these acceleratedconditions the saturation point was reached in around 30 minutes, whichis 190x resp. 20x (Fig.6.9a) faster than the off-state stressed cases. Again
95
CH
AP
TE
R6.
ME
ASU
RE
ME
NT
SA
ND
STR
ESS
AN
ALY
SIS
Figure 6.10: a) Subthreshold drain current evolution vs. stress time. b)Stress behavior before and after (characterization) stress interruptions.Stressing is performed for periods of 5 min followed by stress stop periodsof 30 min.
Figure 6.11: Extracted lateral field distribution Ex using the subthresholdcurves shown in Fig. 6.12a. For convenience sake two voltage step sizeswere used and a lateral position correction of xcr=2.8 λ was performed(chapter 4).
there is however no straightforward 1:1 relation between degradation andtotal charge flown. Contrary to the off-state, for a subthreshold stresscriterion the dominant mechanism responsible for the measured current(Fig. 6.10a) is induced by Ex and not by Ey . This Ex multiplication dom-inated (chapter 4) behavior is observed in Fig. 6.10b. During the 5 minstress phase positive interface charge injection will induce Ex field peaks(Fig. 6.11) increasing Ex multiplication (chapters 3 and 4) and thereforethe subthreshold current (Fig. 6.10b). During the 30 min stress stop perioddetrapping of positive (mobile) charge results in a reduction of the Expeaks and therefore a drop in the measured (subthreshold) stress currentonce stressing is resumed. The change in current between two points rightafter the stress stop period is and indication of an Ex change caused byrecently injected or redistributed charge.
96
6.6.ST
RE
SSE
VO
LU
TIO
N
Figure 6.12: a) Measured subthreshold I-V degradation at T=25 ◦C forincreasing subthreshold stress times. b) Measured off-state leakage current.
Device characterization
At the end of the 30 min stress stop phase both subthreshold and off-stateleakage characterization was performed (Fig. 6.12). For the subthresh-old condition at T=25 ◦C no leakage correction was required. This is be-cause the 100 nA at 50 V forced subthreshold source current is significantlylarger than the (<1 nA) leakage current. Using the subthreshold curves ofFig. 6.12a the Ex distribution was extracted as shown in Fig. 6.11. An Exincrease (black) followed by a lateral shift (green) and finally runaway peakEx failure (red) is observed. The cause of this failure peak being chargebuild up at the Si/SiO2 interface below the gate field-plate edge (chapter 1,Fig. 1.10).
To extract field changes caused by stress subthreshold characterizationsweeps beyond the stress voltage (= 650 V) have to be performed. Thesetypes of sweeps can however affect the injected charge distribution. Itis therefore best to scan and extract the Ex field until the VDS point ofstress. This will however result in extracted fields for only part of theextension as indicated in Fig. 6.11 (solid lines). Finally as expected fromchapter 5 comparing the off-state leakage degradation curves (Fig. 6.7a vs.Fig. 6.12b) shows the ’low’ VDS thermal generation increase has a positiveT dependence while the high VDS vertical field multiplication increase hasan inverse T dependence.
6.6 Stress evolution
Comparing the stress time vs. current figures (Fig. 6.9a and 6.10a) theenvelope of the curves show an equivalent trend, whereby the specificstress stop-start differences in behavior were explained in the previoussections. Because the (HCI) current source mechanisms are different in theoff-state and subthreshold conditions (chapters 4, 5) it was discussed thatno straight-forward relation could be made between the total charge flown
97
CH
AP
TE
R6.
ME
ASU
RE
ME
NT
SA
ND
STR
ESS
AN
ALY
SIS
Figure 6.13: Example of a device after destructive failure using the sub-threshold stress criterion.
Figure 6.14: Measured on state stress current for continuous (CS) andintermitted stressing. Stress conditions (black) as shown in Fig. 6.10 (green)two stress times of 5 resp. 10 min with the stress stop ≈ 5 min.
and degradation. For instance, destructive failure as shown in Fig. 6.13equivalent to that caused by Ex runaway at the field-plate edge was neverobserved under off-state stressed conditions.
To check whether the stress stop phase and the length thereof influencesthe time to failure a DC subthreshold stress cycle is interrupted for differentlengths at specific time intervals (Fig. 6.14). The (black) curve with thelongest time to failure is achieved under the (5 min stress, 30 min stop)conditions of the previous section, as shown in Fig. 6.10. The other (green)intermitted curve is obtained using 2 stress time periods of 5 resp. 10 min.The stress stop phase is kept at the minimum time for characterizationI-V sweeps to be performed (here ≈ 5 min). A large difference in time
98
6.7.M
OD
EL
ING
Figure 6.15: The sg profile extracted at T= 50 ◦C allows for accurate pre-dictions over a wide temperature range using the analytical models ofchapter 5
to failure is observed, indicating that there is a (mobile) charge build upunder constant stressing that cannot detrap since there is no stress stopphase. The portion of mobile charge that would typically detrap duringa stress stop, will influence the Ex field such that failure happens earlier.These differences in failure times and behavior make accelerated testingfor off-state and subthreshold operation particularly difficult. This can bean issue for AC reliability predictions, since the DC predictions can onlyprovide a minimum failure time that, without the (AC) charge ’relaxation’phase, can be significantly lower than in practice. It is therefore importantto find the right stress condition for each specific application.
6.7 Modeling
Using a series of stress curves (Fig. 6.14) across different stress biasing con-ditions and temperatures parameters needed for describing the reliabilitymodels can be extracted. However, since this type of failure modeling willprovide mostly process specific results, it is of no broader interest for thematerial presented in this work. Some preliminary results can howeverbe found in [91]. Even though it was shown that destructive failure isunlikely under off-state operation, an increase in current due to HC stresscould still be detrimental for device operation if not properly taken intoaccount. Predicting leakage changes especially across a wide temperaturerange is therefore essential. Using the theory of chapter 5 such a predictionwas done for the (t3) degraded device of Fig. 6.6. The analytical model,TCAD-simulation and experimental I-V data were compared for a widetemperature range showing good agreement (Fig. 6.15). It should be men-
99
CH
AP
TE
R6.
ME
ASU
RE
ME
NT
SA
ND
STR
ESS
AN
ALY
SIS
tioned that the Nit extraction (chapter 4) and inclusion (chapter 3) was notpart of the low voltage scan and predictive model as shown in Fig. 6.15and first presented in [6]. For the high VDS range there is therefore a slightmismatch between the predicted and the measured values. Nonetheless,the method shows that performing quick, non-destructive low VDS scan-ning (Fig. 6.6) allows for extracting T -dependent degradation informationin a voltage range significantly broader than the scanning range itself.
6.8 Conclusion
Through off-state and subthreshold stress and characterization proceduresthe degradation phenomena in gradient based FP assisted RESURF powerdevices were investigated. The results show that after high voltage stress-ing the Si/SiO2 interface at the drain side of the drift region will degrade.A set of accelerated stress tests were introduced and analyzed. The stress-induced drain side damage was shown to affect both the low-VDS leakagecurrent and the high voltage breakdown behavior, respectively. Combinedwith lateral field extraction from the subthreshold characteristic of these de-vices, detailed profiling of the HC induced degradation through electricalcharacterization has been shown. Finally, using the developed low voltagesurface generation velocity profile extraction, I-V degradation predictionsfor a wide temperature range can be made via noninvasive low-voltagescanning.
CHAPTER 7SUMMARY & RECOMMENDATIONS
Abstract
In this chapter, the main conclusions presented throughout thiswork are summarized followed by a point by point overview of theoriginal contributions. Finally, recommendations are given for futurework related to gradient optimized FP assisted RESURF devices.
101
102
7.1.SU
MM
AR
Y
7.1 Summary
Chapter 1
This chapter introduces the relevant parts in the field of power semiconduc-tor devices through a literature and simulation study. The inherent problemfaced with the desire towards smaller devices, higher breakdown voltages(BV) and yet lower specific on-resistances (RONA) was discussed. Some ofthe design trends used to circumvent these problems were discussed, in-cluding the main focus of this work the gradient based FP assisted RESURFconcept. Finally, the reliability problems faced with these complex designsand their high current, high voltage operation were briefly addressed.
Chapter 2
This chapter introduces a generalized mathematical model describing fieldand potential distributions in different configurations of gradient based FPassisted RESURF devices. Based on this model and the different electricalbreakdown conditions a step by step breakdown optimization guidelinewas presented. Using this proposed guideline device designs with op-timized (virgin) RONA-BV values can be achieved for both lateral andvertical devices.
Chapter 3
This chapter presents a systematic study on the effects of arbitrary par-asitic charge profiles on the field and potential distribution in the drainextension of (gradient based) FP assisted RESURF devices. The impor-tance of the device characteristic length λ in dielectric-interfaced (depleted)semiconductor systems was also discussed. Finally, adopting this key pa-rameter a new relatively simple charge-response method was introducedfor reconstructing the electrostatic response of arbitrary parasitic chargedistributions.
Chapter 4
In this chapter the subthreshold operating condition of gradient based FPassisted RESURF devices and its related impact ionization behavior wastreated. Under these circumstances, a method to extract the lateral electricfield in the drain extension of these types of RESURF devices was intro-duced and its limitations discussed. Finally a new method to extract theinterface charge from extracted field changes was also presented. Togetherthese methods provided a new noninvasive way to electrically extract andanalyze (changing) lateral fields and hot carrier induced trapped chargefrom the subthreshold ID-VDS characteristics.
103
CH
AP
TE
R7.
SUM
MA
RY
&R
EC
OM
ME
ND
AT
ION
S
Chapter 5
In this chapter a new off-state leakage I-V model was developed for gradi-ent based FP assisted RESURF power devices that allowed for quantitativemodeling and analysis across wide temperature ranges. It was shown thatstress-induced interface damage affects both the leakage current and thehigh voltage breakdown behavior. Therefore, via noninvasive low-voltagescanning only, the model enabled the extraction of the surface generationvelocity profile and related interface charge of degraded devices. Finally byincluding the key temperature relations the model also allowed for leakagecurrent predictions of degraded devices across a range in current, voltageand temperature well beyond the measured window.
Chapter 6
In this chapter the developed subthreshold and off-state characterizationmethods are applied to analyze degradation phenomena in stressed gradi-ent based FP assisted RESURF power devices. The results show that afterhigh voltage stressing the Si/SiO2 interface at the drain side of the driftregion will degrade. A set of accelerated stress tests was introduced andits pros and cons investigated. Using the lateral field extraction method,detailed profiling of the HC induced degradation through electrical charac-terization was shown. Finally using the developed low voltage surface gen-eration velocity profile extraction method, it was also shown that off-stateleakage I-V degradation predictions could be made for a wide temperaturerange.
7.2 General Conclusion
In this work an expanded overview on gradient based FP assisted RESURFdevices is given. Even though the initial applications and many exploratorypublications date back to the early 1990’s a collective work focusing specifi-cally on this type of FP assisted RESURF was never made before. This workfocuses on the most important aspects in these devices, how they are inter-related, what limits them, how to (electrically) interpret them and how tomodel them. In so doing new methods for device optimization and charac-terization were developed. As such, this work provides a broad frameworkwith the necessary insights and tools for the design and in depth (electrical)analysis of any gradient based FP assisted RESURF optimized device ordevice region.
104
7.3.O
RIG
INA
LC
ON
TR
IBU
TIO
NS
7.3 Original contributions
Below a point by point overview is given of the original contributionspresented in this work.
• Generalized design equations, and consequently lateral decay char-acteristics λ, for optimal RESURF gradients have been derived [2].
– Breakdown optimization guidelines are proposed that includelateral field, vertical field, junction and tunneling breakdown.
– The adoption of the field plate potential as an optimizationparameter has been proposed.
• A charge-based response methodology to determine the electrostaticinfluence of arbitrary interface charge profiles (Nit) has been pre-sented [3].
– The subthreshold impact ionization behavior in gradient basedFP assisted RESURF devices has been modeled.
– Fourier/Laplace based extraction of (parasitic) charge profilesfrom lateral field changes has been proposed.
• A generalized lateral field extraction method has been presented [5].
• The impact ionization, thermal generation and tunneling across widetemperature ranges under off-state conditions has been modeled [6].
• The extraction of the surface generation (sg) profile via noninvasive’low’ voltage scanning has been proposed [6].
• It has been shown that a single drain side located degraded interfaceresults in both low (sg) and high (Nit) voltage I-V changes.
• Off-state and subthreshold dc stress degradation analysis has beenpresented.
7.4 Recommendations and Future work
The constant field in gradient optimized FP assisted RESURF devices andits strongly localized voltage or charge controlled distribution providesmany optimization and electrical characterization capabilities. Some rec-ommendations and proposed future work, both directly related to gradientoptimization, but also for more general (HV) phenomena of importance,that were not treated in this work are summarized in the coming subsec-tions.
105
CH
AP
TE
R7.
SUM
MA
RY
&R
EC
OM
ME
ND
AT
ION
S
7.4.1 On-state operation
This work focuses on the subthreshold (chapter 4) and off-state (chapter 5)behavior of gradient based FP assisted devices. In these situations ad-ditional charge due to mobile carriers will not compete with that of thethe drift extension depletion charge. In on-state operation however a sub-stantial source electron current can flow of which the charge (n = Jsat
−q·vsat)
corresponding to these mobile carriers will affect the device performance.Under this high current condition breakdown limitations can occur dueto latch-up induced by parasitic bipolar transistors, due to the Kirk effect[42, 108] or possibly due to self-heating.
Kirk effect
For high drain voltage, high current applications the Kirk effect is knownto limit on-state breakdown [42, 108]. In devices with a constant dopedextension this occurs due to the (peak) Ex field shifting from the p-body/n-drift to the n-drift/n+ drain junction (Fig. 1.8a), where it subsequentlycauses runaway impact ionization (on-state breakdown). The change infield distribution is caused by the injected mobile carrier charge (highsource current) shifting the potential lines to the drain with respect to itsoff-state potential distribution. The onset of this effect occurs when the(negative) mobile carrier charge is equal to the (positive) depletion charge(doping ND(x), see also Eq. (1.9)). Considering that the constant lateralfield distribution in gradient based FP assisted RESURF devices is basedon a charge gradient (Fig. 1.8b) a constant mobile charge increase due toon-state operation will not affect this optimal gradient. The additionalconstant mobile charge will only shift the zero charge point (n− = ND(x)
+)away from the (x = 0) p-body/n-drift junction into the drift extension [43].
Because of this a unique Kirk effect and related impact ionization in-duced (hole) backgate current is expected. For instance the peak in back-gate current in IBg vs. VGS curves, typically used as a worst case scenarioon-state stressing condition, will not be present in these devices at drainvoltages beyond which Ex is clamped (chapter 4). This is the case since forvoltages at which the field is clamped additional mobile charge will notresult in a reduction and subsequent ’flipping’ of the Ex field peak (thecause of the IBg vs. VGS peak) but simply push the clamped fields awayfrom the p-body/n-drift junction. Therefore finding the drain voltage atwhich the peak in backgate (body) current disappears can be used as a wayto determine when field clamping (chapter 4) occurs. Figure 7.1 showsa simulation example of this behavior. The clear peak in IBg disappearsaround VDS > 150 V. This corresponds to the 5 λ field clamping criterionpresented in chapter 4. More research is needed to find out if and how on-state operation, degradation and reliability in gradient based FP assistedRESURF devices are affected by this type of unique Kirk effect.
106
7.4.R
EC
OM
ME
ND
AT
ION
SA
ND
FUT
UR
EW
OR
K
Figure 7.1: Simulated IBg vs. VGS at increasing VDS for a gradient based FPassisted device using the device parameters of Table 5.1.
Parasitic bipolar transistor
Due to their dielectric isolation SOI/trench based devices have higher latch-up immunity [109] than their bulk counterparts. Still, if not optimizedcorrectly runaway currents due to this parasitic latch-up effect would limitbreakdown. Latch-up is an effect initiated by an increased hole generationdue to impact ionization in the drain extension. This hole current willflow to the p-body (backgate) that, due to the internal p-body resistance,will forward bias the source/p-body junction and turn on the n-source/p-body/n-drift parasitic bipolar transistor. An example to eliminate thiseffect would be the use of a metal/semiconductor (Schottky) source contact.When optimizing the n-drain extension region of gradient based FP assisteddevices according to chapter 2 it is therefore recommended that one alsomakes sure that latch-up does not occur due to a non-optimized adjacentp-body.
Self heating
Finally in on-state (high power) operation self heating could also play arole. The generalization of thermal behavior is difficult. This is because forthermal issues not only front-end but also back-end, contact and packagedesign might play a significant role. Prediction and overall differences insafe device operation for different device designs and operating conditionsare best obtained and visualized using their respective SOV’s, a frameworkintroduced in [49] and expanded in [107, 110]. Applying this to gradientbased FP assisted RESURF devices has yet to be done and could providevaluable insights in the electro-thermal behavior of these devices and howthey compare to their constant doped counterparts.
107
CH
AP
TE
R7.
SUM
MA
RY
&R
EC
OM
ME
ND
AT
ION
S
Since current flowing through a certain field will ultimately heat upa device to its thermal equilibrium, a direct benefit of the gradient basedFP assisted RESURF devices and their unique field distribution is that itcould potentially provide a method to electrically localize or through (drainextension) design shift the ’origin’ of self-heating. Knowing or controllingthe location of these joule heating (= J · E) hot-spots can be beneficial forthermal optimization e.g. for placement of heat-sinks etc.
7.4.2 Platform for improved physical understanding
In gradient based FP assisted RESURF devices the (clamped) lateral fieldevolution and the corresponding linear expansion of the depletion layerwith applied drain voltage (chapter 4) provides a unique electrical mea-surement platform. As shown in this work locating, studying, separatingand extracting interrelated parameters from the I-V characteristics is morestraightforward than in their constant drift doping counterparts. A quickoverview of possible characterization and extraction methods not treatedor fully developed before are given in the coming section.
Impact ionization coefficients
Impact ionization (II) measurements at low reverse fields and high tem-peratures are typically difficult to perform since then electron-hole pairgeneration (due to II) is minimal. The unique clamped field behavior ofgradient based FP assisted RESURF devices can however be used to extractimpact ionization coefficients under these difficult conditions. While ex-plaining the basis of electric field extraction in chapter 4 it was shown thatfor clamped linearly expanding field distributions the impact ionizationintegral vs drain voltage (IIint vs. VDS) relations show a constant slope(Fig. 4.2b). Consequently, when Ex is known beforehand the impact ioniza-tion coefficients and their temperature dependence can be extracted fromchanges in this slope.
For optimized gradient based FP assisted RESURF devices decreasingclamped Ex fields can be obtained by designing structures with gradients(Eq. (2.14)) corresponding to increasing drift extension lengths L and afixed (lateral reachthrough) breakdown voltage BV or vice versa. Hence,the impact ionization rate for these different (clamped) lateral fields (≈ BV
L)
can be extracted using subthreshold I-V sweeps and comparing the slopesof their respective IIint vs. VDS relations (chapter 4). Similarly, by changingthe measurement temperatures the temperature dependencies of II can beextracted.
Hot carrier injection characteristics
It would be desirable that the I-V characteristics of a device can be pre-dicted after any realistic stress sequence at any temperature [111, 112].
108
7.4.R
EC
OM
ME
ND
AT
ION
SA
ND
FUT
UR
EW
OR
K
The first steps towards such an all inclusive model for gradient based FPassisted RESURF devices has been developed in this work. It was shownthat before and after degradation both the subthreshold (chapters 3 and 4)and off-state (chapter 5) characteristics across a wide measurement rangecould be modeled provided that theNit and corresponding sg profiles wereknown. Thus if their evolution as a function of stress time (t), stress field (E)and stress temperatures (T) would be known the I-V characteristics at anyrealistic/practical temperature for any stress condition at any time couldbe modeled. By systematically adopting the extraction methods presentedin chapters 4 resp. 5 across different stress conditions the sg(t,E,T) andNit(t,E,T) relations can be determined. Although not performed in thiswork, developing a measurement procedure that extracts these key degra-dation relations is of great interest. This is because these relations allowfor accurate reliability predictions and provide an easy way to comparedegradation across several specific IC processes. For instance, differenttypes of oxide formation (such as formed in STI or LOCOS) will yield dif-ferent degradation characteristics of which possible design benefits couldbe negated simply due to their worse reliability.
Off-state field extraction
Performing off-state field extraction using leakage I-V sweeps induces theleast amount of interface degradation at a given drain voltage. In caseminimal characterization induced stressing (chapter 6) is required this off-state field extraction is of interest. The key information necessary for thedevelopment of such an extraction method is presented in chapters 4 and5. However because both Ex and Ey play a role in drain leakage behavior(chapter 5) the development of a generalized off-state field extraction pro-cedure will be more complex than the subthreshold extraction method aspresented in chapter 4. An additional benefit of off-state field extractionwould be that it could also be applied to extract fields in reverse biasedgradient based FP assisted RESURF diodes.
7.4.3 Optimization
A gradient based FP assisted RESURF drift extension in its most basic formcan simply be interpreted as a semiconductor design block for a dopedregion with an optimal field distribution and low RONA. The optimizationand related characterization methods also focused on relatively high break-down voltage ranges and n type regions. As such alternative device types,applications for lower BV ranges and p-type extensions regions are worthfurther research.
109
CH
AP
TE
R7.
SUM
MA
RY
&R
EC
OM
ME
ND
AT
ION
S
Alternative devices
Although this work focused on diodes and (N)MOS transistors, gradientbased optimization has also been reported in other types of devices forvarious applications such as (RF) bipolar transistors to improve the tradeoffbetween the cutoff frequency and off-state breakdown voltage [43, 113]but also in alternative power devices such as IGBTs [66] and thyristors[114] to name a few. Another example that should be mentioned is thevariable capacitor. This device also known as varactor or varicap is, as thename implies, a capacitor with an electrically tunable capacitance. Tunablevariations in capacitance (e.g. between FP and HW) are inherent to theRESURF principle since the drain extension depletion depends on theapplied (drain) potential (chapter 5). The super junction RESURF principlewas originally proposed for the development of a varactor with a highlydense capacitance (chapter 1, [29]) and low RONA. Hence, returning to theorigin of the RESURF principle the gradient based FP assisted RESURFtechniques treated in this work can also be used for the future developmentof varactors, as well as other devices.
Gradient based optimization for lower BV ranges
The optimization of silicon based power device design in integrated circuits(IC’s) is generally limited to process steps required for the standard CMOStransistors embedded in the same IC’s. Power device implementation instandard processes are therefore in most cases limited to finding the rightcombination of steps to get effective designs without additional (process)cost. The introduction of charge gradients as an effective method to opti-mally distribute fields, as discussed in this work, has mostly been limitedto the higher voltage / long drift extension power devices (> 300 V). Thisis because effective implementation of doping gradients [34, 35] in driftextensions requires increasingly precise process control for the lower thevoltage range (i.e. shorter drain extension lengths). Therefore as the gen-eral device feature size shrinks and these processes become available forpower device integration the myriad of design optimization, analysis andmodeling methods developed and discussed in this work could become ofincreased interest for lower (breakdown) voltage ranges.
Edge termination
In integrated solutions it is essential to galvanically isolate high voltagedevices from their low voltage counterparts. Typically this is achievedusing extended lowly doped regions or dielectrics in some capacity [13].One such an example is the use of deep trenches filled with a dielectric atthe device boundary. For instance since the working principle of (bulk)superjunction RESURF is based on n/p pillar periodicity [31, 60] it can behypothesized that because of this potential boundary mirroring a non-idealedge boundary will cause premature edge breakdown limiting breakdown
110
7.4.R
EC
OM
ME
ND
AT
ION
SA
ND
FUT
UR
EW
OR
K
in the entire superjunction configuration. Therefore in this type of devicean optimized edge termination as for instance reported in [115] is essen-tial. When using a dielectric filled edge termination (with field plate) forinstance it can therefore be beneficial to use a gradient based edge termina-tion both to act as a strong potential boundary [116] and to impose theiroptimized potential distributions on all subsequent depleted n/p pillars.To minimize total isolation area it is essential to drop the maximum amountof voltage across as small an area as possible. Therefore edge terminationtechniques have been reported where low-k dielectric trench filling is em-ployed [117]. Finding the optimal gradient for different dielectrics can beobtained by changing the dielectric constant ( εd) as described in chapter2. Finally, the methods reported in chapter 3 can be used for understand-ing field non-idealities caused by arbitrary charge distributions at suchdielectric filled FP assisted trench edge terminations.
PMOS
From an electrostatic point of view developing the PMOS equivalent toNMOS devices (Fig. 7.2a) is not only a matter of changing the gradedn-type extension doping to p-type. The potential boundary conditionsimposed by the backgate (BG)/source (S), drain (D), field plate (FP) andhandler wafer (HW) or substrate will also play an important role in bothoptimization and reliability concerns. For a reverse biased NMOS devicethe source and drain potentials may vary laterally from 0 V to the supplyvoltage (+V) (Fig. 7.2a). Conversely for a PMOS device it is the sourcepotential that should be higher than the drain (Fig. 7.2b,c).
For an equivalent PMOS double sided RESURF condition (Fig. 7.2b) theinverted lateral potential distribution also requires inverted vertical poten-tial boundary conditions at the FP and HW (from 0 V to +V). However,since the hole mobility is lower than the electron mobility the electro-statically similar PMOS will still have a higher RONA (chapter 1, Eq. 1.6).Furthermore, as illustrated S, FP and HW have to be shorted which isrealistic for discrete vertical (trench) devices but generally not a realisticbiasing condition for SOI based devices. Since in those cases the HW isgenerally grounded a less than optimal potential distribution as shown inFig. 7.2c is obtained. In such a situation the depletion layer expansion isonly assisted from the top (source shorted) field plate, which results in asingle sided (SS) instead of a double sided RESURF condition (chapter 2)resulting in yet higher RONA than its NMOS counterpart.
Besides the relatively high RONA, premature Ey breakdown induced bythe higher semiconductor vertical potential drop in SS devices could alsooccur. These higher Ey fields, if not limiting breakdown, will result in anincreased hot-carrier (here electron) injection and as such reduce reliability(chapter 6). The potential distribution in Fig. 7.2c illustrates that the largestvertical potential drop, hence, highest vertical fields are now not at thedrain side but at the source side Si/BOX interface. Charge injection at
111
CH
AP
TE
R7.
SUM
MA
RY
&R
EC
OM
ME
ND
AT
ION
S
Figure 7.2: Schematic cross-sections showing the potential distributionsfor different device configurations. a) The typical SOI based doping gradi-ent FP assisted RESURF NDMOS. b) Its PMOS equivalent using invertedboundary conditions whereby the HW is also at +V. c) The PMOS equiva-lent with realistic boundary conditions (HW = 0 V) for lateral SOI basedintegration.
interfaces closer to the source/gate will possibly also further deterioratethe reliability with respect to its NMOS counterpart. With the correctboundary conditions the results of this work can be helpful in developingoptimization and extraction routines, and reliability models focussed onPMOS devices.
High-side NMOS
In low voltage applications it is usually the PMOS transistor that is used asthe high-side transistor i.e. a transistor connecting a load to VDD (a currentsource), instead of connecting a load to ground (a current sink) whichis typically done with NMOS transistors. However as briefly explainedin the previous subsection the generally higher RONA, worse reliabilityand limited availability of integrated high voltage PMOS makes high sideimplementation of HV NMOS an often used alternative. When a high side
112
7.4.R
EC
OM
ME
ND
AT
ION
SA
ND
FUT
UR
EW
OR
K
NMOS is turned on the source potential equals the supply voltage +V.Since a positive gate-source (VGS) potential is required to keep an NMOStransistor on this requires a ’boosted’ gate potential which is (at least) Vth
above the +V source. Typically this requires additional (high side) gatedriving circuitry [118], which for integrated solutions will understandablyincrease the total device size and result in an (effective) increase of RONA.Therefore, high-side boundary conditions and operating limits of gradientbased FP assisted RESURF NMOS devices and how they relate to theirPMOS alternatives is worth further investigation.
APPENDIX ATHE PARABOLIC POTENTIAL
APPROXIMATION
The second order differential equation using the parabolic potential ap-proximation for solving the 2-D Poisson equation in the reverse biaseddrain extension of a RESURF device, provides the basis for many of thedeveloped gradient based FP assisted RESURF device optimization (chap-ter 2), modeling (chapter 3, 5) and analysis (chapter 4, 6) methods. Since itwas still lacking this appendix provides a step by step derivation resultingin these widely used equations [2, 3, 37, 78] which in this work are gen-erally referred to as Merchant’s equation. As these derivations, requirequite some mathematical stamina, this appendix can be a valuable aidto the reader in understanding the origin, the limitations and expansionpossibilities of many of the key equations used throughout this work.
In the subsequent derivations a single-sided (SS) drain extension ver-tical design is considered of which the double-sided asymmetric (ASYM)and symmetric (SYM) equivalents (Fig. 2.3) can be obtained using themethods treated in chapter 2.
A.1 Derivation - Single Sided device
To obtain Merchant’s equation the 2-D Poisson’s equation is solved for areverse biased RESURF diode under the assumption that:
1) the field in the direction of current flow, here the lateral field, is constant,
2) the doping in the vertical direction, perpendicular to current flow, isconstant,
3) the vertical semiconductor potential drop is parabolic.
113
114
AP
PE
ND
IXA
.T
HE
PAR
AB
OL
ICP
OT
EN
TIA
LA
PP
RO
XIM
AT
ION
Figure A.1: Overview of the vertical boundary conditions for a single-sideddevice under the parabolic potential approximation with VFP=0 V.
The boundary conditions obtained under these assumptions are visualizedfor an ’SS’ device in Fig. A.1. The 2-D Poisson’s equation,
∂2ψ(x,y)∂x2 +
∂2ψ(x,y)∂y2 = −
ρ(x,y)ε
(A.1)
is solved step by step using these boundary conditions. According toassumptions 1 and 2:
Ex = constant and ρ(x,y) = ρ(x). (A.2)
This gives the homogenous differential equation:
∂2ψ(x,y)∂x2 = 0 (A.3)
with:∂2ψ(y)
∂y2 = −ρ
εor
∂Ey(y)
∂y=ρ
ε. (A.4)
Hence, for the vertical field in the semiconductor (y > 0) it holds:
Ey(y)|y>0 = Es(y) =ρ
εsy+ c1 (A.5)
with boundary condition Ey(ts) = 0, c1 = − ρεsts giving:
Es(y) =ρ
εs(y− ts). (A.6)
For the potential in the semiconductor (y > 0) it holds that:
Vy(y)|y>0 = −
∫Es(y)dy
= −12ρ
εsy2 +
ρ
εstsy+ c2
(A.7)
115
AP
PE
ND
IXA
.T
HE
PAR
AB
OL
ICP
OT
EN
TIA
LA
PP
RO
XIM
AT
ION
with boundary condition Vy(ts) = u, c2 = − ρ2εst2s + u giving:
Vy(y)|y>0 = −12ρ
εs(y− ts)
2 + u. (A.8)
In the dielectric (y < 0) it holds that:
Ey(y)|y<0 = −Ed, (A.9)
and:Vy(y)|y<0 = Edy+ c3. (A.10)
with boundary condition Vy(−td) = VFP, c3 = Edtd + VFP giving:
Vy(y)|y<0 = Ed(y+ td) + VFP. (A.11)
Since the potential has to be continuous across the interface (y = 0):
Vy(0)|y<0 = Vy(0)|y>0
Edtd + VFP = −ρ
2εst2s + u,
(A.12)
and since the electric displacement field (D = εE) is continuous across theinterface (y = 0):
−Ed =εs
εdEs(0) (A.13)
it holds that:
−εs
εdEs(0)td + VFP = −
ρ
2εst2s + u
εs
εd
ρ
εststd + VFP = −
ρ
2εst2s + u
u =ρ
εs
(εs
εdtstd +
12t2s
)+ VFP.
(A.14)
The bracketed parameter is the (squared) parabolic approximated, single-sided, effective thickness λ as discussed in chapter 2:
λ =
√ts
(ts
2+εs
εdtd
)(A.15)
u =ρ
εs(λ2) + VFP (A.16)
since it holds that:∂2ψ(y)
∂y2 = −ρ
εs(A.17)
this reduces to:
−(u− VFP)
λ2 = −ρ
εs(A.18)
116
AP
PE
ND
IXA
.T
HE
PAR
AB
OL
ICP
OT
EN
TIA
LA
PP
RO
XIM
AT
ION
with the general differential equation for potential distribution u(x), i.e.Merchant’s equation, given by:
∂2u(x)
∂x2 −u(x) − VFP(x)
λ2 = −ρ(x)
εs. (A.19)
This is an expansion of [37] including VFP �= 0 which was subsequentlyexpanded to include the influence of interface charge in chapter 3, Eq. (3.2).
A.2 Dielectric asymmetry
As discussed in chapter 2 the single-sided (SS) solution can easily be mod-ified to a generally applicable solution when the (vertical) location ofpotential symmetry is known. For instance, for an SS and SYM device thisis ts resp. ts
2 from the dielectric interface. For the fully depleted ASYMcase this location depends on the asymmetrical dielectric properties andthicknesses (hence capacitances). The general solution for this location,assuming VFP = 0, is derived by applying the SS derivation (A.1-A.16) toboth the ts1 and ts2 sides shown in Figs. 2.2 and 2.3. This yields for side 1:
u =ρ
εsλ2
1 (A.20)
with
λ1 =
√ts1
(ts1
2+εs
εd1td1
)(A.21)
and side 2
u =ρ
εsλ2
2 (A.22)
with
λ2 =
√ts2
(ts2
2+εs
εd2td2
)(A.23)
from (A.20) and (A.22) it follows that λ1 = λ2 = λ thus:
ts1
2+εs
εd1td1 =
ts2
2+εs
εd2td2 (A.24)
Further, ts1+ts2 = ts, hence the ASYM vertical point of potential symmetrycan be obtained using:
ts1,2 =
ts2 (ts + 2 εs
εd2,1td2,1)
ts +εs
εd1td1 +
εs
εd2td2
. (A.25)
117
AP
PE
ND
IXA
.T
HE
PAR
AB
OL
ICP
OT
EN
TIA
LA
PP
RO
XIM
AT
ION
A.3 Solving Merchant’s equation - non-reachtrough case
For the case of ρ(x) = q(ax +N0) and fixed field-plate potential VFP thenon homogenous differential equation to be solved, see (A.19), is:
u ′′(x) −1λ2u(x) = −
q(N0 + ax)
εs−VFP
λ2
= −qa
εsx−
qN0
εs−VFP
λ2 .(A.26)
The general solution of (A.26), considering u = g, is the sum of the homo-geneous solution (gh) and the particular solutions (gp1,gp2)
g = gh + gp1 + gp2. (A.27)
A.3.1 Homogenous solution
The homogenous equation is:
g′′−
1λ2g = 0 (A.28)
with the characteristic equation and solution
r2 −1λ2 = 0, r2 =
1λ2 , r = ±1
λ, (A.29)
giving the homogenous solution:
gh = c1e− x
λ + c2exλ . (A.30)
A.3.2 Particular solution 1 (gp1), first order polynomial "x"
The non-homogenous equation for the first order polynomial is:
g′′−
1λ2g = −
qa
εsx. (A.31)
A particular solution is guessed and solved using the ’method of undeter-mined coefficients’:
gp1 = A1x+A0,
g′p1 = A1,
g′′p1 = 0,
(A.32)
substituting this in (A.31) results in:
−1λ2 (A1x+A0) = −
qa
εsx, (A.33)
giving A1 = qaλ2
εsand A0 = 0, therefore:
gp1 =qaλ2
εsx. (A.34)
118
AP
PE
ND
IXA
.T
HE
PAR
AB
OL
ICP
OT
EN
TIA
LA
PP
RO
XIM
AT
ION
A.3.3 Particular solution 2 (gp2), constant terms
The non-homogenous equation for the constant terms is:
g′′−
1λ2g = −
qN0
εs−VFP
λ2 . (A.35)
A particular solution is guessed:
gp2 = A1,
g′p2 = 0,
g′′p2 = 0,
(A.36)
substituting this in (A.35) results in:
−1λ2A1 = −
qN0
εs−VFP
λ2 , (A.37)
giving:
gp2 = A1 =qN0λ
2
εs+ VFP. (A.38)
A.3.4 General solution
Substituting (A.30), (A.34) and (A.38) into (A.27) gives the general solution
u(x) =qλ2
εs(N0 + ax) + VFP + c1e
− xλ + c2e
xλ . (A.39)
A homogeneous solution with equal but opposite exponents can be rewrit-ten using the hyperbolic notation [94]:
u(x) =qλ2
εs(N0 + ax) + VFP + k1 cosh
(x
λ
)+ k2 sinh
(x
λ
), (A.40)
since ddx
sinh x = cosh x, ddx
cosh x = sinh x and applying the chain rule:
u ′(x) =qλ2a
εs+k1
λsinh
(x
λ
)+k2
λcosh
(x
λ
). (A.41)
A.3.5 The initial value problem
To maintain clarity in the derivation, as is a common simplification in thiswork, both N0 and VFP are assumed to be zero. Under these assumptionsand the non-reachthrough boundary condition (see chapter 4) the analyticaldescription of u(x) and u’(x) are derived. Hence,
N0 = 0, VFP = 0, u(0) = 0, u ′(w) = 0, u(w) = VD (A.42)
Since cosh(0) = 1 and sinh(0) = 0, k1 is:
u(0) = 0 + k1 + 0 = 0,
k1 = 0,(A.43)
119
AP
PE
ND
IXA
.T
HE
PAR
AB
OL
ICP
OT
EN
TIA
LA
PP
RO
XIM
AT
ION
and k2 is:
u ′(w) =qλ2a
εs+k1
λsinh
(w
λ
)+k2
λcosh
(w
λ
)= 0,
qλ2
εsa+ 0 +
k2
λcosh
(w
λ
)= 0,
k2
λcosh
(w
λ
)= −
qλ2
εsa,
k2 = −qλ3a
εs
1cosh(w
λ)
.
(A.44)
Thus the analytical description for non reach through potential distribu-tions is:
u(x) =qλ2a
εsx−
qλ3a
εs
sinh(xλ)
cosh(wλ)
,
=qλ3a
εs
(x
λ−
sinh(xλ)
cosh(wλ)
),
= −Esatλ
(x
λ−
sinh(xλ)
cosh(wλ)
),
(A.45)
with Esat is the clamping lateral electric field. For the lateral field holds:
u ′(x) = Ex(x) = −Esatλ
(1λ−
1λ
cosh(xλ)
cosh(wλ)
)
= −Esat
(1 −
cosh(xλ)
cosh(wλ)
).
(A.46)
A.4 2-D distribution
With the solutions along the line of potential symmetry u(x) the 2-D fielddistributions in the semiconductor and dielectric can be calculated. This isdone using the (vertical) parabolic semiconductor potential and fixed elec-tric field displacement (A.13) across the semiconductor/dielectric interface.The 2-D lateral, vertical and absolute (Eq. (5.19)) silicon field distributionsobtained for a gradient based FP assisted RESURF device based on thedevice parameters of chapter 5 table 5.1 are visualized in Fig. A.2. UsingGauss’s law Fig. A.3 includes the dielectric field distributions. From thisfigure it is immediately apparent that the oxides are essential in divertingthe highest fields away from the current carrying semiconductor.
120
AP
PE
ND
IXA
.T
HE
PAR
AB
OL
ICP
OT
EN
TIA
LA
PP
RO
XIM
AT
ION
Figure A.2: Separate overview of the Ex , Ey and (absolute) semiconduc-tor field distributions for a SYM BV=750 V, Ldrift=50μm , ts=0.5μm andtd=3.2μm device.
Figure A.3: Overview of fields including the oxide field distributions.
APPENDIX BIMPACT IONIZATION INTEGRAL
AND MULTIPLICATION
Traditionally, the impact ionization integral is shown to be related to themultiplication factor using IIint = 1 − 1
M(W) . This is valid under theassumption that αn = αp [13, 21] or when determining breakdown valuesin the case of αn � αp [119], as done in chapter 2. However, to obtain thefull multiplication curves, pre breakdown, when αn � αp (chapter 4), amore accurate relation needs to be derived. Under this condition the αp
term in Eq. (4.2) is neglected, giving:
dIn
dx= αn · In. (B.1)
Integration gives:
ln (In) + c =
∫W0αndx, (B.2)
where c is an integration constant.Since at x=0, In = IS (Fig. 4.1), c = − ln (IS). Hence,
In(x) = IS · exp(∫W
0αndx
), (B.3)
consequently giving
Mn(W) =In(x)
IS= exp
(∫W0αndx
), (B.4)
thus resulting in
ln(M(W)
)=
W∫0
αn(x)dx = IIint, (B.5)
as stated in Eq. (4.4).
121
APPENDIX CGRADED MOSCAP DEPLETION
Interface depletion is essential for understanding and modeling thermalgeneration behavior in gradient based FP assisted RESURF devices. In-terface depletion in the partially depleted section of a drain extension(Fig. 5.3a-e) can be approximated as a 1-D MOS capacitor (MOSCAP) withan applied voltage equal to VDS − VFP (here VFP=0). This is illustrated inFig. C.1 for a graded doped 1-D MOSCAP.
The interface depletion thickness ti at lateral location x is [21]:
ti(x) =
√2 · εSi ·ϕm
q ·ND(x)(C.1)
where ϕm is the surface potential. This potential signifies the differencebetween the vertical point of potential symmetry and the potential at theSi/SiO2 interface (chapter 2). The interface is considered to be depletedfor those depletion thicknesses (ti(x)) at which ϕm = ϕb, the MOSCAP’sdoped silicon (ND(x)) build-in potential [21]. The maximum depletionthicknesses achievable by the 1-D MOSCAP are those ti(x) where ϕm =
2ϕb, the potential at which interface inversion would occur [21].For a graded doped MOSCAP ϕb is location dependent and equal to:
ϕb(x) =kT
q· ln
(ND(x)
ni
). (C.2)
The charge depleted at interface position x is:
Qdep(x) = q ·ND(x) · ti(x). (C.3)
When ND(x) is known the ti(x) for ϕm = ϕb can be calculated. Sincenecessary depletion charge is known the potential needed to deplete theinterface at any lateral interface positionWi can be calculated using:
V(Wi) ≈ Qdep(Wi)
Cox
= qND(Wi)ti(Wi) · toxεox
. (C.4)
123
124
AP
PE
ND
IXC
.G
RA
DE
DM
OSC
AP
DE
PL
ET
ION
Figure C.1: Interface depletion (Wi) in a graded doped MOSCAP at differ-ent applied bias
Combining (C.1) with (C.4) for ϕm = ϕb and ND(x) = a · x gives thedrain-source potential (VDS) necessary for depletion at interface locationWi (see chapter 5, Fig. 5.3f):
V(Wi) = VDS ≈q · a ·Wi · tox ·
√2·εSi·ϕb(Wi)
q·a·Wi
εox. (C.5)
Charge (Qit) injected at the interface will alter (C.4) according to:
V(Wi) ≈ Qdep(Wi) +Qit(Wi)
Cox
. (C.6)
This will result in an increase or decrease in the VDS needed to deplete theinterface (C.5). For increased accuracy, when extracting charge locationusing changes in thermal generation (chapter 5), this has to be taken intoaccount.
APPENDIX DPARAMETERS
125
126
AP
PE
ND
IXD
.PA
RA
ME
TE
RS
Table D.1: List of Symbols: Device
a Slope of graded characteristicLdrift Drift extension lengthstsi Silicon layer thicknessts Semiconductor layer thicknessεsi Silicon permittivity (= 11.7)εs Semiconductor permittivitytox Oxide layer thicknesstd Dielectric layer thicknessεox Oxide permittivity (= 3.9)εd Dielectric permittivityCox Oxide capacitance (areal)Cd Dielectric capacitance (areal)teq Equivalent thicknessλ Lateral decay characteristicW Fully depleted semiconductor depletion width (x-dir)Wi Interface (Si/SiO2) depletion width (x-dir)ti Interface (Si/SiO2) depletion thickness (y-dir)WGate Gate width (z-dir)
Table D.2: List of Symbols: Charge
q Elementary charge (= 1.610−19C)NA Acceptor, p-type dopingND Donor, n-type dopingni Intrinsic doping concentrationQdep Depletion chargeNit Interface charge distributionQit Interface chargeWit Interface charge width
Table D.3: List of Symbols: Electric Fields
Esi Silicon fieldEs Semiconductor fieldEox Oxide fieldEd Dielectric fieldEx Lateral fieldEy Vertical fieldEcrit Critical field valueEB2B Band to Band tunneling fieldEmax Maximum field valueEsat Field saturation (clamp) valueEpeak Peak field valueEvir Virgin (non-stressed) field caseEdgr Degraded field caseExtr Extracted (lateral) electric fieldEδit Field change due to delta interface chargeEit Field change due to interface charge distribution
127
AP
PE
ND
IXD
.PA
RA
ME
TE
RS
Table D.4: List of Symbols: Potentials
ψs Semiconductor potentialψd Dielectric potentialψy Vertical potentialψstep Interface charge induced (1-D) vertical potential stepu(x) Lateral potential along the potential symmetry lineuit Lateral potential change due to interface chargeuδit Lateral potential change due to delta interface chargeVGS Gate-Source voltageVth Threshold voltageVDS Drain-Source voltageVclamp Drain voltage at field clamping (Wdep ≈ 5 λ)VFP Field-Plate potentialBV Breakdown voltageBVmax Maximum ideal breakdown voltage
Table D.5: List of Symbols: Currents
ID Drain currentIS Source currentIBg Back-gate (body) currentIn Electron currentIp Hole currentISGen Fully depleted drift extension thermal generationIIGen Interface depleted thermal generationIdgrGen Additional thermal generation from degraded interfaceIGen Total thermal generationIleak Total leakage current
Table D.6: List of Symbols: Other
RON On resistanceRONA Specfic on resistanceαn Electron impact ionization coefficientαp Hole impact ionization coefficientMn Electron multiplicationMp Hole multiplicationIIint Impact ionization integralAfit Fulop’s eq prefactor (= 10−34cm6 · V−7)An Chynoweths’s eq prefactor (= 7.03 · 105cm−1)Bn Chynoweths’s eq prefactor (= 1.47 · 105Vcm−1)sg Surface velocityτg Carrier lifetimeσns Electron capture cross sectionσps Hole capture cross section
BIBLIOGRAPHY
[1] B. K. Boksteen, R. J. E. Hueting, C. Salm, and J. Schmitz, “An initial study on the reliabilityof power semiconductor devices,” in Proc. STW.ICT’10, 2010, pp. 68–72. [Online]. Available:http://purl.utwente.nl/publications/76311
[2] B. K. Boksteen, A. Ferrara, A. Heringa, P. G. Steeneken, G. E. J. Koops, and R. J. E. Hueting, “Designoptimization of field-plate assisted RESURF devices,” in Proc. ISPSD’13, 2013, pp. 237–240. [Online].Available: http://dx.doi.org/10.1109/ISPSD.2013.6694460
[3] B. K. Boksteen, A. Ferrara, A. Heringa, P. G. Steeneken, and R. J. E. Hueting, “Impact of interface chargeon the electrostatics of field-plate assisted RESURF devices,” IEEE Trans. Electron Devices, vol. 61, no. 8,pp. 2859–2866, Aug. 2014. [Online]. Available: http://dx.doi.org/10.1109/TED.2014.2327574
[4] B. K. Boksteen, S. Dhar, A. Heringa, G. E. J. Koops, and R. J. E. Hueting, “Extraction of the electricfield in field plate assisted RESURF devices,” in Proc. ISPSD’12, 2012, pp. 145–148. [Online]. Available:http://dx.doi.org/10.1109/ISPSD.2012.6229044
[5] B. K. Boksteen, A. Heringa, A. Ferrara, P. G. Steeneken, J. Schmitz, and R. J. E. Hueting, “Electric fieldand interface charge extraction in field-plate assited RESURF devices,” IEEE Trans. Electron Devices,vol. 62, no. 2, pp. 662–628, Feb 2015. [Online]. Available: http://dx.doi.org/10.1109/TED.2014.2383360
[6] B. K. Boksteen, S. Dhar, A. Ferrara, A. Heringa, R. J. E. Hueting, G. E. J. Koops, C. Salm, and J. Schmitz,“On the degradation of field-plate assisted RESURF power devices,” in Proc. IEDM’12, 2012, pp.13.4.1–13.4.4. [Online]. Available: http://dx.doi.org/10.1109/IEDM.2012.6479036
[7] G. E. Moore, “Cramming more components onto integrated circuits, Reprinted from Electronics,volume 38, number 8, April 19, 1965, pp.114 ff.” IEEE Solid State Circuits Newslet., vol. 20, no. 3, pp.33–35, 2006. [Online]. Available: http://dx.doi.org/10.1109/N-SSC.2006.4785860
[8] A. R. Sears, B. J. Baliga, M. M. Barnicle, P. M. Campbell, and W. Garwacki, “High voltage, high speed,GaAs Schottky power rectifier,” in Proc. IEDM’83, vol. 29, 1983, pp. 229–232. [Online]. Available:http://dx.doi.org/10.1109/IEDM.1983.190483
[9] B. J. Baliga, “Trends in power semiconductor devices,” IEEE Trans. Electron Devices, vol. 43, no. 10, pp.1717–1731, 1996. [Online]. Available: http://dx.doi.org/10.1109/16.536818
[10] G. Karady and T. Gilsig, “The thyristor valve in HVDC transmission,” IEEE Spectr., vol. 10, no. 12, pp.36–43, 1973. [Online]. Available: http://dx.doi.org/10.1109/MSPEC.1973.5216631
[11] B. J. Baliga, “Enhancement- and depletion-mode vertical-channel m.o.s. gated thyristors,” IEEEElectron Device Lett., vol. 15, no. 20, pp. 645–647, 1979. [Online]. Available: http://dx.doi.org/10.1049/el:19790459
[12] Y. Tarui, Y. Hayashi, and T. Sekigawa, “Diffusion self-aligned MOST - A new approach for high speeddevices,” in Proc. 1st Conf. Solid-State Devices, supplement to J. Japan Soc. Appl. Phys.,vol.39, pp. 105-110,1970.
[13] B. J. Baliga, Fundamentals of power semiconductor devices. Springer, 2008. [Online]. Available:http://dx.doi.org/10.1007/978-0-387-47314-7
[14] A. G. Chynoweth, “Ionization Rates for Electrons and Holes in Silicon,” Phys. Rev., vol. 109, pp.1537–1540, Mar 1958. [Online]. Available: http://link.aps.org/doi/10.1103/PhysRev.109.1537
[15] W. Fulop, “Calculation of avalanche breakdown voltages of silicon p-n junctions,” Solid-State Electron.,vol. 10, no. 1, pp. 39–43, 1967. [Online]. Available: http://dx.doi.org/10.1016/0038-1101(67)90111-6
[16] B. J. Baliga and S. K. Ghandi, “Analytical solutions for the breakdown voltage of abrupt cylindricaland spherical junctions,” Solid-State Electron., vol. 19, no. 9, pp. 739 – 744, 1976. [Online]. Available:http://dx.doi.org/10.1016/0038-1101(76)90152-0
[17] Z. M. Li, P. A. Mawby, and K. Board, “A physical insight into the quasi-saturation effect inVDMOS power transistors,” Int. J. Electron., vol. 83, no. 1, pp. 13–22, 1997. [Online]. Available:http://dx.doi.org/10.1080/002072197135599
[18] A. W. Ludikhuize, “A versatile 250/300-V IC process for analog and switching applications,”IEEE Trans. Electron Devices, vol. 33, no. 12, pp. 2008 – 2015, dec 1986. [Online]. Available:http://dx.doi.org/10.1109/T-ED.1986.22860
129
130
BIB
LIO
GR
AP
HY
[19] R. Herzer, “Integrated gate driver circuit solutions,” in Proc. CIPS’10, 2010, pp. 1–10. [Online].Available: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5730628
[20] K. Nakamura, Y. Kawaguchi, K. Karouji, K. Watanabe, Y. Yamaguchi, and A. Nakagawa,“Complementary 25 V LDMOS for analog applications based on 0.6 um BiCMOS technology,” in Proc.BCTM’00, 2000, pp. 94 –97. [Online]. Available: http://dx.doi.org/10.1109/BIPOL.2000.886181
[21] S. Sze and K. Ng, Physics of Semiconductor Devices. Wiley, 2006. [Online]. Available: http://dx.doi.org/10.1002/0470068329
[22] R. P. Zingg, “On the specific on-resistance of high-voltage and power devices,” IEEE Trans. ElectronDevices, vol. 51, no. 3, pp. 492–499, 2004. [Online]. Available: http://dx.doi.org/10.1109/TED.2003.822948
[23] J. A. van der Pol, A. W. Ludikhuize, H. G. A. Huizing, B. van Velzen, R. J. E. Hueting, J. F. Mom,G. van Lijnschoten, G. J. J. Hessels, E. F. Hooghoudt, R. van Huizen, M. J. Swanenberg, J. H. H. A.Egbers, F. van den Elshout, J. J. Koning, H. Schligtenhorst, and J. Soeteman, “A-BCD: An economic100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications,” inProc. ISPSD’00, 2000, pp. 327 –330. [Online]. Available: http://dx.doi.org/10.1109/ISPSD.2000.856836
[24] T. Kobayashi, H. Abe, Y. Niimura, T. Yamada, A. Kurosaki, T. Hosen, and T. Fujihira, “High-voltagepower MOSFETs reached almost to the silicon limit,” in Proc. ISPSD’01, 2001, pp. 435–438. [Online].Available: http://dx.doi.org/10.1109/ISPSD.2001.934646
[25] G. Deboy, N. Marz, J. P. Stengl, H. Strack, J. Tihanyi, and H. Weber, “A new generation of high voltageMOSFETs breaks the limit line of silicon,” in Proc. IEDM’98, 1998, pp. 683–685. [Online]. Available:http://dx.doi.org/10.1109/IEDM.1998.746448
[26] J. A. Appels and H. M. J. Vaes, “High voltage thin layer devices (RESURF devices),” in Proc. IEDM’79,vol. 25, 1979, pp. 238–241. [Online]. Available: http://dx.doi.org/10.1109/IEDM.1979.189589
[27] J. A. Appels, M. H. Collet, P. A. Hart, H. M. J. Vaes, and J. F. C. M. Verhoeven, “Thin Layer High-VoltageDevices,” Philips J. Res., vol. 35, 1980.
[28] A. W. Ludikhuize, “A review of RESURF technology,” in Proc. ISPSD’00, 2000, pp. 11–18. [Online].Available: http://dx.doi.org/10.1109/ISPSD.2000.856763
[29] S. Shirota and S. Kaneda, “New type of varactor diode consisting of multilayer p-n junctions,” J. Appl.Phys., vol. 49, no. 12, pp. 6012–6019, 1978. [Online]. Available: http://dx.doi.org/10.1063/1.324570
[30] D. Coe, “High voltage semiconductor device,” U.S. Patent 4 754 310 A, June 28, 1988. [Online].Available: http://www.google.com/patents/US4754310
[31] T. Fujihira, “Theory of Semiconductor Superjunction Devices,” Jpn. J. Appl. Phys., vol. 36, no. Part 1,No. 10, pp. 6254–6262, 1997. [Online]. Available: http://dx.doi.org/10.1143/JJAP.36.6254
[32] D. Krizaj, G. Charitat, and S. Amon, “A new analytical model for determination of breakdown voltageof Resurf structures,” Solid-State Electron., vol. 39, no. 9, pp. 1353–1358, Sep. 1996. [Online]. Available:http://dx.doi.org/10.1016/0038-1101(96)00051-2
[33] S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, and R. Pinker, “Realization of highbreakdown voltage (> 700V) in thin SOI devices,” in Proc. ISPSD’91, 1991, pp. 31–35. [Online].Available: http://dx.doi.org/10.1109/ISPSD.1991.146060
[34] S. Merchant and E. Arnold, “High voltage thin film transistor having a linear doping profile andmethod for making,” U.S. Patent 5 300 448 A, Apr 5, 1994, uS Patent 5,300,448. [Online]. Available:http://www.google.com/patents/US5300448
[35] S. Merchant, “Arbitrary lateral diffusion profiles,” IEEE Trans. Electron Devices, vol. 42, no. 12, pp.2226–2230, 1995. [Online]. Available: http://dx.doi.org/10.1109/16.477783
[36] B. J. Baliga, “MOS devices for power electronic applications,” in Proc. ESSDERC’98, 1998, pp. 81–85.[Online]. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1503494
[37] S. Merchant, “Analytical model for the electric field distribution in SOI RESURF and TMBSstructures,” IEEE Trans. Electron Devices, vol. 46, no. 6, pp. 1264–1267, 1999. [Online]. Available:http://dx.doi.org/10.1109/16.766896
[38] D. Brisbin, A. Strachan, and P. Chaparala, “Hot carrier reliability of N-LDMOS transistor arraysfor power BiCMOS applications,” in Proc. IRPS’02, 2002, pp. 105 – 110. [Online]. Available:http://dx.doi.org/10.1109/RELPHY.2002.996617
[39] B. Doyle, M. Bourcerie, J. C. Marchetaux, and A. Boudou, “Interface state creation and charge trappingin the medium-to-high gate voltage range (Vd/2 � Vg � Vd) during hot-carrier stressing ofn-MOS transistors,” IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 744–754, 1990. [Online]. Available:http://dx.doi.org/10.1109/16.47781
[40] N. Koike and K. Tatsuuma, “A drain avalanche hot carrier lifetime model for n- and p-channelMOSFETs,” IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 457–466, 2004. [Online]. Available:http://dx.doi.org/10.1109/TDMR.2004.831992
[41] Z. Chen, K. Hess, J. Lee, J. W. Lyding, E. Rosenbaum, I. Kizilyalli, S. Chetlur, and R. Huang,
131
BIB
LIO
GR
AP
HY
“On the mechanism for interface trap generation in MOS transistors due to channel hot carrierstressing,” IEEE Electron Device Lett., vol. 21, no. 1, pp. 24–26, 2000. [Online]. Available:http://dx.doi.org/10.1109/55.817441
[42] C. T. Kirk, “A theory of tranistor cutoff frequency (ft) falloff and high current densities,” IEEE Trans.Electron Devices, vol. 9, pp. 164–174, 1962. [Online]. Available: http://dx.doi.org/10.1109/T-ED.1962.14965
[43] R. J. E. Hueting and R. van der Toorn, “Analysis of the Kirk effect in silicon-based bipolar transistorswith a nonuniform collector profile,” IEEE Trans. Electron Devices, vol. 52, no. 11, pp. 2489–2495, 2005.[Online]. Available: http://dx.doi.org/10.1109/TED.2005.857176
[44] A. W. Ludikhuize, M. Slotboom, A. Nezar, N. Nowlin, and R. Brock, “Analysis of hot-carrier-induceddegradation and snapback in submicron 50 V lateral MOS transistors,” in Proc. ISPSD’97, 1997, pp.53–56. [Online]. Available: http://dx.doi.org/10.1109/ISPSD.1997.601430
[45] A. W. Ludikhuize, “Kirk effect limitations in high voltage IC’s,” in Proc. ISPSD’94, 1994, pp. 249 –252.[Online]. Available: http://dx.doi.org/10.1109/ISPSD.1994.583734
[46] M. Dai, “Lifetime model for advanced n-channel transistor hot-carrier-injection degradation,”IEEE Electron Device Lett., vol. 31, no. 6, pp. 525–527, 2010. [Online]. Available: http://dx.doi.org/10.1109/LED.2010.2046392
[47] A. Ferrara, P. G. Steeneken, K. Reimann, A. Heringa, L. Yan, B. K. Boksteen, G. E. J. Koops, A. J.Scholten, R. Surdeanu, J. Schmitz, and R. J. E. Hueting, “Comparison of electrical techniques fortemperature evaluation in power MOS transistors,” in Proc. ICMTS’13, 2013, pp. 115–120. [Online].Available: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6528156
[48] J. M. Roux, X. Federspiel, D. Roy, and P. Abramowitz, “Correction of Self-Heating forHCI Lifetime Prediction,” in Proc. IRPS ’07, 2007, pp. 281–287. [Online]. Available: http://dx.doi.org/10.1109/RELPHY.2007.369905
[49] A. Ferrara, P. G. Steeneken, A. Heringa, B. K. Boksteen, M. Swanenberg, A. J. Scholten, L. vanDijk, J. Schmitz, and R. J. E. Hueting, “The safe operating volume as a general measure for theoperating limits of LDMOS transistors,” in Proc. IEDM’13, 2013, pp. 6.7.1– 6.7.4. [Online]. Available:http://dx.doi.org/10.1109/IEDM.2013.6724577
[50] “ATLAS (Version: 5.18.3.R).” Silvaco Inc., Mar. 2012.
[51] P. Wessels, M. Swanenberg, H. van Zwol, B. Krabbenborg, H. Boezen, M. Berkhout, and A. Grakist,“Advanced BCD technology for automotive, audio and power applications,” Solid-State Electron.,vol. 51, no. 2, pp. 195–211, 2007. [Online]. Available: http://dx.doi.org/10.1016/j.sse.2007.01.019
[52] S. Merchant, E. Arnold, H. Baumgart, R. Egloff, T. Letavic, S. Mukherjee, and H. Pein, “Dependence ofbreakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors,” inProc. ISPSD’93, 1993, pp. 124–128. [Online]. Available: http://dx.doi.org/10.1109/ISPSD.1993.297121
[53] E. K. Choi, Y. I. Choi, and S. K. Chung, “Breakdown voltage and on-resistance of multi-RESURF LDMOS,” Microelectr. J., vol. 34, no. 5, pp. 683–686, 2003. [Online]. Available:http://dx.doi.org/10.1016/S0026-2692(03)00096-X
[54] S. Mahalingam and B. J. Baliga, “A low forward drop high voltage trench MOS barrier Schottkyrectifier with linearly graded doping profile,” in Proc. ISPSD’98, 1998, pp. 187–190. [Online]. Available:http://dx.doi.org/10.1109/ISPSD.1998.702665
[55] X. Luo, B. Zhang, and Z. Li, “A new structure and its analytical model for the electricfield and breakdown voltage of SOI high voltage device with variable- k dielectric buriedlayer,” Solid-State Electron., vol. 51, no. 3, pp. 493–499, 2007. [Online]. Available: http://dx.doi.org/10.1016/j.sse.2007.01.034
[56] T. Letavic and J. Petruzzello, “High-voltage device structure,” U.S. Patent 7 968 938 B2, jun 28, 2011.[Online]. Available: http://www.google.com/patents/US7968938
[57] Y. Chen, Y. C. Liang, and G. S. Samudra, “Design of gradient oxide-bypassed superjunction powerMOSFET devices,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1303–1310, 2007. [Online]. Available:http://dx.doi.org/10.1109/TPEL.2007.900559
[58] G. M. Hurkx and R. van Dalen, “Semiconductor device with voltage sustaining zone,” U.S. Patent6 624 472 B2, Sep 23, 2003. [Online]. Available: http://www.google.com/patents/US6624472
[59] S. Schwantes, T. Florian, T. Stephan, M. Graf, and V. Dudek, “Analysis and optimization of theback-gate effect on lateral high-voltage SOI devices,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp.1649–1655, 2005. [Online]. Available: http://dx.doi.org/10.1109/TED.2005.850952
[60] A. Ferrara, B. K. Boksteen, R. J. E. Hueting, A. Heringa, J. Schmitz, and P. G. Steeneken, “Ideal RESURFgeometries,” IEEE Trans. Electron Devices [in press], 2015.
[61] G. Hurkx, D. Klaassen, and M. Knuvers, “A new recombination model for device simulationincluding tunneling,” IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 331–338, 1992. [Online]. Available:http://dx.doi.org/10.1109/16.121690
132
BIB
LIO
GR
AP
HY
[62] S. Merchant, E. Arnold, and M. Simpson, “Tunneling in thin SOI high voltage devices,” in Proc.ISPSD’95, 1995, pp. 130–135. [Online]. Available: http://dx.doi.org/10.1109/ISPSD.1995.515022
[63] A. Heringa, G. Koops, B. K. Boksteen, and A. Ferrara, “Field plate assisted resistance reductionin a semiconductor device,” U.S. Patent 20 140 103 968 A1, Apr 17, 2014. [Online]. Available:http://www.google.com/patents/US20140103968
[64] A. Ferrara, A. Heringa, B. K. Boksteen, J. Claes, A. van der Wel, J. Schmitz, R. J. E. Hueting, andP. G. Steeneken, “The boost transistor: a field-plate controlled LDMOS,” in Proc. ISPSD’15, 2015, pp.165–168. [Online]. Available: http://dx.doi.org/10.1109/ISPSD.2015.7123415
[65] S. Schwantes, J. Furthaler, B. Schauwecker, F. Dietz, M. Graf, and V. Dudek, “Analysis of the back-gateeffect on the on-state breakdown voltage of smartpower SOI devices,” IEEE Trans. Device Mater. Rel.,vol. 6, no. 3, pp. 377–385, 2006. [Online]. Available: http://dx.doi.org/10.1109/TDMR.2006.883128
[66] Y.-K. Leung, A. K. Paul, J. D. Plummer, and S. S. Wong, “Lateral IGBT in thin SOI for high voltage,high speed power IC,” IEEE Trans. Electron Devices, vol. 45, no. 10, pp. 2251–2254, 1998. [Online].Available: http://dx.doi.org/10.1109/16.725263
[67] G. E. J. Koops, E. A. Hijzen, R. J. E. Hueting, and M. A. A. in ’t Zandt, “RESURF stepped oxide (RSO)MOSFET for 85V having a record-low specific on-resistance,” in Proc. ISPSD’04, 2004, pp. 185–188.[Online]. Available: http://dx.doi.org/10.1109/ISPSD.2004.1332896
[68] J. Sonsky and A. Heringa, “Dielectric resurf: breakdown voltage control by STI layout in standardCMOS,” in Proc. IEDM’05, 2005, pp. 372–376. [Online]. Available: http://dx.doi.org/10.1109/IEDM.2005.1609354
[69] P. Moens, F. Bauwens, J. Baele, K. Vershinin, E. De Backer, E. M. Sankara Narayanan, and M. Tack,“XtreMOS : the first integrated power transistor breaking the silicon limit,” in Proc. IEDM ’06, 2006,pp. 1–4. [Online]. Available: http://dx.doi.org/10.1109/IEDM.2006.346933
[70] D. Varghese, H. Kufluoglu, V. Reddy, H. Shichijo, D. Mosher, S. Krishnan, and M. A. Alam, “off-Statedegradation in drain- extended NMOS transistors: interface damage and correlation to dielectricbreakdown,” IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2669–2678, 2007. [Online]. Available:http://dx.doi.org/10.1109/TED.2007.904587
[71] P. Moens, D. Varghese, and M. Alam, “Towards a universal model for hot carrier degradation inDMOS transistors,” in Proc. ISPSD’10, 2010, pp. 61–64. [Online]. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5543974
[72] S. Reggiani, G. Barone, S. Poli, E. Gnani, A. Gnudi, G. Baccarani, M.-Y. Chuang, W. Tian,and R. Wise, “TCAD simulation of hot-carrier and thermal degradation in STI-LDMOStransistors,” IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 691–698, 2013. [Online]. Available:http://dx.doi.org/10.1109/TED.2012.2227321
[73] J. Colinge, FinFETS and other multi-gate transistors. Springer, 2008. [Online]. Available: http://dx.doi.org/10.1007/978-0-387-71752-4
[74] J.-H. Woo, J.-M. Choi, and Y.-K. Choi, “Analytical threshold voltage model of junctionless double-gateMOSFETs with localized charges,” IEEE Trans. Electron Devices, vol. 60, pp. 2951–2955, 2013. [Online].Available: http://dx.doi.org/10.1109/TED.2013.2273223
[75] J.-P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. N. Nazarov, andR. T. Doria, “Reduced electric field in junctionless transistors,” Appl. Phys. Lett., vol. 96, no. 7, pp.073 510–073 510, 2010. [Online]. Available: http://dx.doi.org/10.1063/1.3299014
[76] S. Manzini and A. Gallerano, “Avalanche injection of hot holes in the gate oxide of LDMOStransistors,” Solid-State Electron., vol. 44, no. 7, pp. 1325–1330, 2000. [Online]. Available:http://dx.doi.org/10.1016/S0038-1101(99)00317-2
[77] K. K. Young, “Analysis of conduction in fully depleted SOI MOSFETs,” IEEE Trans. Electron Devices,vol. 36, no. 3, pp. 504–506, 1989. [Online]. Available: http://dx.doi.org/10.1109/16.19960
[78] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOIMOSFET’s,” IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2326–2329, 1993. [Online]. Available:http://dx.doi.org/10.1109/16.249482
[79] T.-K. Chiang, “A quasi-two-dimensional threshold voltage model for short-channel junctionlessdouble-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2284–2289, 2012. [Online].Available: http://dx.doi.org/10.1109/TED.2012.2202119
[80] S.-H. Oh, D. Monroe, and J. M. Hergenrother, “Analytic description of short-channel effects infully-depleted double-gate and cylindrical, surrounding-gate MOSFETs,” IEEE Electron Device Lett.,vol. 21, no. 9, pp. 445–447, 2000. [Online]. Available: http://dx.doi.org/10.1109/55.863106
[81] A. Gnudi, S. Reggiani, E. Gnani, and G. Baccarani, “Semianalytical model of the subthreshold currentin short-channel junctionless symmetric double-gate field-effect transistors,” IEEE Trans. ElectronDevices, vol. 60, no. 4, pp. 1342–1348, 2013. [Online]. Available: http://dx.doi.org/10.1109/TED.2013.2247765
[82] K. Young, “Short-channel effect in fully depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 36,
133
BIB
LIO
GR
AP
HY
no. 2, pp. 399–402, 1989. [Online]. Available: http://dx.doi.org/10.1109/16.19942
[83] R.-H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: from bulk to SOI tobulk,” IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704–1710, 1992. [Online]. Available:http://dx.doi.org/10.1109/16.141237
[84] D. Monroe and J. M. Hergenrother, “Evanescent-mode analysis of short-channel effects in fullydepleted SOI and related MOSFETs,” in Proc. Int. SOI Conference ’98, 1998, pp. 157–158. [Online].Available: http://dx.doi.org/10.1109/SOI.1998.723159
[85] D. J. Frank, Y. Taur, and H.-S. Wong, “Generalized scale length for two-dimensional effects inMOSFETs,” IEEE Trans. Electron Devices, vol. 19, no. 10, pp. 385–387, 1998. [Online]. Available:http://dx.doi.org/10.1109/55.720194
[86] R. van Dalen, A. Heringa, P. W. M. Boos, A. B. van der Wal, and M. J. Swanenberg, “Usingmultiplication to evaluate HCI degradation in HV-SOI devices,” in Proc. ISPSD’10, 2010, pp. 89–92.[Online]. Available: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5544937
[87] Y. C. Liang, K. P. Gan, and G. S. Samudra, “Oxide-bypassed VDMOS (OBVDMOS): an alternativeto superjunction high voltage MOS power devices,” IEEE Trans. Electron Devices, vol. 22, no. 8, pp.407–409, 2001. [Online]. Available: http://dx.doi.org/10.1109/55.936359
[88] J. Zhu, W. Sun, Q. Qian, L. Cao, N. He, and S. Zhang, “700V thin SOI-LIGBT withhigh current capability,” in Proc. ISPSD’13, 2013, pp. 119–122. [Online]. Available: http://dx.doi.org/10.1109/ISPSD.2013.6694443
[89] W. Zhang, B. Zhang, M. Qiao, L. Wu, K. Mao, and Z. Li, “A novel vertical field-plate lateral devicewith ultralow specific on-resistance,” IEEE Trans. Electron Devices, vol. 61, no. 2, pp. 518–524, 2014.[Online]. Available: http://dx.doi.org/10.1109/TED.2013.2294643
[90] S. Selberherr, Analysis and simulation of semiconductor devices. Springer Wien; New York, 1984.[Online]. Available: http://dx.doi.org/10.1007/978-3-7091-8752-4
[91] R. van Dalen, S. Dhar, A. Heringa, M. J. Swanenberg, A. B. van der Wal, P. W. M.Boos, and V. l. Braspenning-Girault, “Hot carrier degradation of HV-SOI devices under off-and on-state current conditions,” in Proc. ISPSD’11, 2011, pp. 348–351. [Online]. Available:http://dx.doi.org/10.1109/ISPSD.2011.5890862
[92] M. Ershov and V. Ryzhii, “Temperature dependence of the electron impact ionization coefficientin silicon,” Semicond. Sci. Technol., vol. 10, no. 2, p. 138, 1995. [Online]. Available: http://dx.doi.org/10.1088/0268-1242/10/2/003
[93] S. Reggiani, E. Gnani, M. Rudan, G. Baccarani, C. Corvasce, D. Barlini, M. Ciappa, W. Fichtner,M. Denison, N. Jensen, G. Groos, and M. Stecher, “Measurement and modeling of the electronimpact-ionization coefficient in silicon up to very high temperatures,” IEEE Trans. Electron Devices,vol. 52, no. 10, pp. 2290–2299, 2005. [Online]. Available: http://dx.doi.org/10.1109/TED.2005.856807
[94] A. Jeffrey and H. H. Dai, Handbook of mathematical formulas and integrals. Academic Press, 2008.
[95] “Mathcad (Version: 15.0).” Parametric Technology Corporation (PTC), 2010.
[96] D. K. Schroder, “Carrier lifetimes in silicon,” IEEE Trans. Electron Devices, vol. 44, no. 1, pp. 160–170,1997. [Online]. Available: http://dx.doi.org/10.1109/16.554806
[97] A. Grove and D. Fitzgerald, “Surface effects on p-n junctions: Characteristics of surface space-chargeregions under non-equilibrium conditions,” Solid-State Electron., vol. 9, no. 8, pp. 783–806, 1966.[Online]. Available: http://dx.doi.org/10.1016/0038-1101(66)90118-3
[98] Y. He, G. Zhang, L. Han, and X. Zhang, “Multiregion DCIV: a sensitive tool for characterizing theinterfaces in LDMOSFETs,” IEEE Electron Device Lett., vol. 33, no. 10, pp. 1435–1437, 2012. [Online].Available: http://dx.doi.org/10.1109/LED.2012.2208730
[99] W. Shockley and W. T. Read, Jr., “Statistics of the recombinations of holes and electrons,” Phys. Rev.,vol. 87, no. 5, p. 835, 1952. [Online]. Available: http://link.aps.org/doi/10.1103/PhysRev.87.835
[100] R. N. Hall, “Electron-hole recombination in germanium,” Phys. Rev., vol. 87, no. 2, p. 387, 1952.[Online]. Available: http://link.aps.org/doi/10.1103/PhysRev.87.387
[101] K. Misiakos and D. Tsamakis, “Accurate measurements of the silicon intrinsic carrier densityfrom 78 to 340 K,” J. Appl. Phys., vol. 74, no. 5, pp. 3293–3297, 1993. [Online]. Available:http://dx.doi.org/10.1063/1.354551
[102] E. Arnold, T. Letavic, and H. Bhimnathwala, “High-temperature off-state characteristics of thin-SOIpower devices,” IEEE Electron Device Lett., vol. 17, no. 12, pp. 557–559, 1996. [Online]. Available:http://dx.doi.org/10.1109/55.545769
[103] B. Weir, “Driving the 21st century’s lights,” IEEE Spectr., vol. 49, no. 3, pp. 42–47, 2012. [Online].Available: http://dx.doi.org/10.1109/MSPEC.2012.6156864
[104] R. P. Zingg, “Silicon-on-insulator for power-semiconductors and power-ICs,” in Proc. OnlineSymposium for Electronics Engineers (OSEE), 2007. [Online]. Available: www.edn.com/Pdf/ViewPdf?contentItemId=4124427
134
BIB
LIO
GR
AP
HY
[105] J. Petruzzello, T. Letavic, H. Van Zwol, M. Simpson, and S. Mukherjee, “A thin-layer high-voltagesilicon-on-insulator hybrid LDMOS/LIGBT device,” in Proc. ISPSD’02, 2002, pp. 117–120. [Online].Available: http://dx.doi.org/10.1109/ISPSD.2002.1016185
[106] A. Ortiz-Conde, F. G. Sánchez, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, “A review of recentMOSFET threshold voltage extraction methods,” Microelectr. Rel., vol. 42, no. 4, pp. 583–596, 2002.[Online]. Available: http://dx.doi.org/10.1016/S0026-2714(02)00027-6
[107] A. Ferrara, P. G. Steeneken, B. K. Boksteen, A. Heringa, A. J. Scholten, J. Schmitz, and R. Hueting,“Identifying failure mechanisms in LDMOS transistors by analytical stability analysis,” in Proc.ESSDERC’14, 2014, pp. 321–324. [Online]. Available: http://dx.doi.org/10.1109/ESSDERC.2014.6948825
[108] A. Ludikhuize, “Kirk effect limitations in high voltage IC’s,” in Proc. ISPSD’94, 1994, pp. 249–252.[Online]. Available: http://dx.doi.org/10.1109/ISPSD.1994.583734
[109] M. Robberg, R. Herzer, and S. Pawel, “Latch-up free 600 V SOI gate driver IC for medium powerand high temperature applications,” in Proc. EPE’05, 2005, pp. 10 pp. – P.10. [Online]. Available:http://dx.doi.org/10.1109/EPE.2005.219732
[110] A. Ferrara, P. G. Steeneken, B. K. Boksteen, A. Heringa, A. J. Scholten, J. Schmitz, and R. Hueting,“Physics-based stability analysis of MOS transistors,” Solid-State Electron., vol. 113, pp. 28–34, 2015.[Online]. Available: http://dx.doi.org/10.1016/j.sse.2015.05.010
[111] D. K. Schroder, Semiconductor material and device characterization. John Wiley & Sons, 2006. [Online].Available: http://dx.doi.org/10.1002/0471749095
[112] A. Neugroschel, R.-Y. Sah, K. M. Han, M. Carroll, T. Nishida, J. Kavalieros, and Y. Lu, “Direct-currentmeasurements of oxide and interface traps on oxidized silicon,” IEEE Trans. Electron Devices, vol. 42,no. 9, pp. 1657–1662, 1995. [Online]. Available: http://dx.doi.org/10.1109/16.405281
[113] R. J. Hueting, J. W. Slotboom, J. Melai, P. Agarwal, and P. H. Magnée, “A new trench bipolar transistorfor RF applications,” IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1108–1113, 2004. [Online].Available: http://dx.doi.org/10.1109/TED.2004.829867
[114] I. Emmerik-Weijland, R. van Dalen, A. van der Wal, and M. Swanenberg, “Development of high-sidecapable thyristors in thin SOI technology,” in Proc. ISPSD’13, 2013, pp. 353–356. [Online]. Available:http://dx.doi.org/10.1109/ISPSD.2013.6694420
[115] R.-y. Miao, F. Lu, Y.-y. Wang, and D.-w. Gong, “Deep oxide trench termination structure forsuper-junction MOSFET,” Electronics Lett., vol. 48, no. 16, pp. 1018–1019, 2012. [Online]. Available:http://dx.doi.org/10.1049/el.2012.2061
[116] H. Mahfoz-Kotb, L. Theolier, F. Morancho, K. Isoird, P. Dubreuil, and T. Do Conto, “Feasibilitystudy of a junction termination using deep trench isolation technique for the realizationof DT-SJMOSFETs,” in Proc. ISPSD’08. IEEE, 2008, pp. 303–306. [Online]. Available: http://dx.doi.org/10.1109/ISPSD.2008.4538959
[117] L. Theolier, H. Mahfoz-Kotb, K. Isoird, F. Morancho, S. Assie-Souleille, and N. Mauran, “A newjunction termination using a deep trench filled with BenzoCycloButene,” IEEE Electron Device Lett.,vol. 30, no. 6, pp. 687–689, 2009. [Online]. Available: http://dx.doi.org/10.1109/LED.2009.2020348
[118] W. C. Dunn, “Driving and protection of high side NMOS power switches,” IEEE Trans. IndustryApplications, vol. 28, no. 1, pp. 26–30, 1992. [Online]. Available: http://dx.doi.org/10.1109/28.120209
[119] R. van Overstraeten and H. de Man, “Measurement of the ionization rates in diffused siliconp-n junctions,” Solid-State Electron., vol. 13, no. 5, pp. 583 – 608, 1970. [Online]. Available:http://dx.doi.org/10.1016/0038-1101(70)90139-5
LIST OF PUBLICATIONS
Peer-reviewed
[BKB:1] A. Ferrara, B. K. Boksteen, R. J. E. Hueting, A. Heringa, J. Schmitz, and P. G. Steeneken, “IdealRESURF geometries,” IEEE Trans. Electron Devices [in press], 2015.
[BKB:2] A. Ferrara, P. G. Steeneken, B. K. Boksteen, A. Heringa, A. J. Scholten, J. Schmitz, andR. Hueting, “Physics-based stability analysis of MOS transistors,” Solid-State Electron., 2015,pp. 28–34.[Online]. Available: http://dx.doi.org/10.1016/j.sse.2015.05.010
[BKB:3] A. Ferrara, A. Heringa, B. K. Boksteen, J. Claes, A. van der Wel, J. Schmitz, R. J. E. Hueting,and P. G. Steeneken, “The boost transistor: a field-plate controlled LDMOS,” in Proc. ISPSD’15,2015, pp. 165–168.[Online]. Available: http://dx.doi.org/10.1109/ISPSD.2015.7123415
[BKB:4] B. K. Boksteen, A. Heringa, A. Ferrara, P. G. Steeneken, J. Schmitz, and R. J. E. Hueting,“Electric field and interface charge extraction in field-plate assited RESURF devices,”IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 662–628, Feb 2015. [Online]. Available:http://dx.doi.org/10.1109/TED.2014.2383360
[BKB:5] B. K. Boksteen, A. Ferrara, A. Heringa, P. G. Steeneken, and R. J. E. Hueting, “Impactof interface charge on the electrostatics of field-plate assisted RESURF devices,” IEEETrans. Electron Devices, vol. 61, no. 8, pp. 2859–2866, Aug. 2014. [Online]. Available:http://dx.doi.org/10.1109/TED.2014.2327574
[BKB:6] A. Ferrara, P. G. Steeneken, B. K. Boksteen, A. Heringa, A. J. Scholten, J. Schmitz,and R. Hueting, “Identifying failure mechanisms in LDMOS transistors by analyticalstability analysis,” in Proc. ESSDERC’14, 2014, pp. 321–324. [Online]. Available: http://dx.doi.org/10.1109/ESSDERC.2014.6948825
[BKB:7] A. Ferrara, P. G. Steeneken, A. Heringa, B. K. Boksteen, M. Swanenberg, A. J. Scholten, L. vanDijk, J. Schmitz, and R. J. E. Hueting, “The safe operating volume as a general measure forthe operating limits of LDMOS transistors,” in Proc. IEDM’13, 2013, pp. 6.7.1– 6.7.4. [Online].Available: http://dx.doi.org/10.1109/IEDM.2013.6724577
[BKB:8] B. K. Boksteen, A. Ferrara, A. Heringa, P. G. Steeneken, G. E. J. Koops, and R. J. E. Hueting,“Design optimization of field-plate assisted RESURF devices,” in Proc. ISPSD’13, 2013, pp.237–240. [Online]. Available: http://dx.doi.org/10.1109/ISPSD.2013.6694460
[BKB:9] A. Ferrara, P. G. Steeneken, K. Reimann, A. Heringa, L. Yan, B. K. Boksteen, G. E. J. Koops,A. J. Scholten, R. Surdeanu, J. Schmitz, and R. J. E. Hueting, “Comparison of electricaltechniques for temperature evaluation in power MOS transistors,” in Proc. ICMTS’13, 2013, pp.115–120. [Online]. Available: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6528156
[BKB:10] B. K. Boksteen, S. Dhar, A. Ferrara, A. Heringa, R. J. E. Hueting, G. E. J. Koops, C. Salm,and J. Schmitz, “On the degradation of field-plate assisted RESURF power devices,” in Proc.IEDM’12, 2012, pp. 13.4.1–13.4.4. [Online]. Available: http://dx.doi.org/10.1109/IEDM.2012.6479036
[BKB:11] B. K. Boksteen, S. Dhar, A. Heringa, G. E. J. Koops, and R. J. E. Hueting, “Extraction of theelectric field in field plate assisted RESURF devices,” in Proc. ISPSD’12, 2012, pp. 145–148.[Online]. Available: http://dx.doi.org/10.1109/ISPSD.2012.6229044
Other
[BKB:12] A. Heringa, G. Koops, B. K. Boksteen, and A. Ferrara, “Field plate assisted resistancereduction in a semiconductor device,” U.S. Patent 20 140 103 968 A1, Apr 17, 2014. [Online].Available: http://www.google.com/patents/US20140103968
[BKB:13] B. K. Boksteen, R. J. E. Hueting, R. Jhaveri, J. C. S. Woo, and J. Schmitz, “A novel asymmetricgate Schottky barrier FET,” in Proc. ICT.OPEN’11, [Poster], 2011.
135
136
LIST
OF
PU
BL
ICA
TIO
NS
[BKB:14] B. K. Boksteen, R. J. E. Hueting, C. Salm, and J. Schmitz, “An initial study on the reliabilityof power semiconductor devices,” in Proc. STW.ICT’10, 2010, pp. 68–72. [Online]. Available:http://purl.utwente.nl/publications/76311
[BKB:15] B. K. Boksteen, “A simulation study and analysis of advanced silicon Schottky barrierfield effect transistors,” Master’s thesis, University of Twente, 2010. [Online]. Available:http://purl.utwente.nl/essays/59426
[BKB:16] N. Stavitski, J. H. Klootwijk, H. W. Zeijl, B. K. Boksteen, A. Y. Kovalgin, and R. A. M. Wolters,“Cross-bridge kelvin resistor (CBKR) structures for measurement of low contact resistances,”in Proc. SAFE’07, 2007. [Online]. Available: http://purl.utwente.nl/publications/64583
ACKNOWLEDGMENTS
Throughout my years as a PhD candidate I had the pleasure to work andinteract with many people who directly or indirectly influenced me andthis work you now have in front of you. It is impossible to fully expressmy gratitude to everyone who supported me in my scientific work, as wellas in everyday life. Therefore I want to start by saying:
Thank you all.
Of course there are a couple of names I must mention. Starting offwith my daily supervisor Ray Hueting. Ray, thanks for being the bestsupervisor I could have asked for. It has always been comforting to knowthat whenever I decided to ’throw something across the wall’ I could trustthat you would be the first to catch it, that you would understand what Iwas trying to say, that your feedback would arrive astonishingly fast andthat it would be reliably in-depth. I would also like to thank my dailysupervisor at NXP Anco Heringa. Anco, it was an immense honor to havebeen able to work with someone as experienced as you as closely as I couldthroughout these years. Your approachable nature, guidance, knowledge,intuition, continuing genuine interest, critical comments and healthy doseof skepticism sowed the seeds for much of which is presented in this work.I would also like to thank Jurriaan Schmitz. Jurriaan, as my promotorthank you for (yet another) opportunity to conduct part of my researchabroad. I’m immensely grateful for your continued support and believe inme throughout these years, your group has truly been a great home-baseever since my years as a BSc student. And of course I’d like to thankAlessandro Ferrara. Alessandro, as a fellow ’power’ PhD those times whenour (research) paths converged, have always been simultaneously the mostfun and most productive. To those that have ever seen us together it is nosecret that without you and our endless discussions, this work would notexist as it is: thanks! Furthermore, I would like to thank Peter Steeneken,Gerhard Koops and Siddhartha Dhar for their in depth feedback, technicalassistance and hands-on help throughout the different phases of this work.
I’d also like to thank Erwin Hijzen, Radu Surdeanu, and others fromNXP research Leuven (IMEC) for welcoming me into the group and reallyincorporating me (and this work) in on going projects. Having this glimpseinto the inner workings of R&D and industry has truly been formative.
137
138
AC
KN
OW
LE
DG
ME
NT
S
Now moving around 300 km or 3.5 hours by car (trust me I know)from Leuven to Enschede, I’d like to thank: Cora, Tom, Sander, Alexey,Remke, Rob, (Prof.dr.zonder.ir.) Dirk, Bram, Anne-Johan, Gerard, Henk,Gerdien and of course, Annemiek. My fellow SC PhDs and ’ex’ PhDs withwhom I shared a room at some point or another: Giulia, Tom, Buket, Balaji,Marcin, Vidhu, Kazmi, Mengdi, Jiahui, Hao and Satadal (thank you PN). Ican’t forget the guys in the ICD PhD room (and sure why not, also Anna).Finally, as the last student remnant of a bygone era that still rememberswalking the actual 3th floor in Hogekamp, I would like to thank everybodypast an present who at some point or another was part of what collectivelyis still known as ’vloer 3’. Thanks for the many unforgettable moments inand outside of the office.
As one of those engineers that enjoys a good dance now and then, I’dlike to thank all of you countless individuals with whom I shared the dancefloor for providing me with the sometimes much needed distraction andendless entertainment. A special thanks to Els, Bregt, Nancy, Mary-Annand Ellen (pretty graphs!), it is no secret that I have a tendency to appearand disappear out of social existence but to me your support, friendshipand sometimes almost forceful ways to make me leave my (work) shellhelped me stay sane throughout these years.
Finally, I’d like to thank my parents. Thank you for teaching me that ifsomething is worth doing it is worth doing well. Without that core believethis work would likely never have existed.
With that it seems I have reached the end, thank you the reader mostof all for your interest. And now, as my mother used to say at the end ofevery (bedtime) story,
A la fin a la fan, e kuenta a kaba.(Papiamento for: And here the story ends)
Propositions accompanying the thesis
Field-plate assisted RESURF power devices:
Gradient based optimization, degradation and analysis Boni K. Boksteen
-------------------------------------------------------------------------------------------------
1. The semiconductor community values guidelines, such as Moore’s Law and the one-dimensional silicon limit, higher than physical laws. (Chapter 1 of this thesis)
2. Optimal device design requires perfect prior knowledge of its mission profile and is therefore an illusion. (Chapter 2 of this thesis)
3. You may have the strongest fishing rod but without the proper bait, you won’t catch your fish. Similarly, sound work without an appealing presentation won’t attract the desired audience.
4. Applying a potential to the field-plate can improve the off-state breakdown voltage or on-state resistance of RESURF optimized devices. (B.K. Boksteen et al., ISPSD, pp.237--240, 2013 and chapter 2 of this thesis)
5. The unique properties of the field-plate assisted RESURF power devices can be utilized to investigate the impact-ionization rates in detail. (Chapters 3&4 of this thesis)
6. Scientific writing leaves little room for literary creativity.
7. It is a humbling, yet essential part of any research to rediscover things that have been known for decades. (Interface depletion, Grove and Fitzgerald, SSE, pp. 783-806, 1966, and chapter 5 of this thesis)
8. Finding the correct accelerated stress conditions is like finding the right temperature to hatch an egg at an accelerated rate without ending up hard-boiling it. (J. McPherson, IRPS 2011 and Chapter 6 of this thesis)
9. You make less progress in one year than you expect but way more than you thought possible in five. (Chapter 7 of this thesis)
10. Grandiose promises are best made when problems aren’t fully understood. (Chapter 7.4 of this thesis)
Stellingen behorende bij het proefschrift
Field-plate assisted RESURF power devices:
Gradient based optimization, degradation and analysis Boni K. Boksteen
-------------------------------------------------------------------------------------------------
1. De halfgeleidergemeenschap waardeert richtlijnen zoals de wet van Moore en de één-dimensionale siliciumlimiet meer dan natuurkundige wetten. (Hoofdstuk 1 van dit proefschrift)
2. Optimaal vermogenstransistorontwerp vergt perfecte voorkennis van zijn taakprofiel en is daarom een illusie. (Hoofdstuk 2 van dit proefschrift)
3. Ook al heb je de beste hengel, zonder het juiste aas zul je je vis niet vangen. Zo zal ook gedegen werk zonder een aantrekkelijke presentatie niet het gewenste publiek aantrekken.
4. Het plaatsen van een potentiaal op de veld-plaat kan de doorslagspanning in de uit-stand en de aanweerstand van RESURF-geoptimaliseerde vermogenstransistors verbeteren. (B.K. Boksteen et al., ISPSD, pp.237--240, 2013 en hoofdstuk 2 van dit proefschrift)
5. De unieke eigenschappen van de veld-plaat ondersteunde RESURF vermogenstransistors kunnen worden gebruikt om de botsingsionisatie nader te bestuderen. (Hoofdstukken 3&4 van dit proefschrift)
6. Wetenschappelijk schrijven laat weinig ruimte voor literaire creativiteit.
7. Het is een nederigmakend, maar essentieel onderdeel van onderzoek om zaken die al tientallen jaren bekend zijn te herontdekken. (Oppervlaktedepletie, Grove en Fitzgerald, SSE, pp. 783-806, 1966 en hoofdstuk 5 van dit proefschrift)
8. Het vinden van de juiste versnelde stresscondities is vergelijkbaar met het vinden van de juiste temperatuur die versneld leidt tot het uitbroeden van een kuiken en niet leidt tot een hardgekookt ei. (J. McPherson, IRPS 2011 en hoofdstuk 6 van dit proefschrift)
9. Je boekt minder vooruitgang in één jaar dan je zou verwachten, maar veel meer dan je voor mogelijk had gehouden in vijf. (Hoofdstuk 7 van dit proefschrift)
10. Grootse beloften maak je het best als problemen niet volledig worden overzien of begrepen. (Hoofdstuk 7.4 van dit proefschrift)
