UDE 2.5 V NMOS Vt 7V UnCox_kn 10OµA

f WIL 32µm IMM

tooVp keepin E 3 2mA Ifi.VEIgMld

Assume Mi is in saturationI Oe law

Gs Rs Ip knvofVss z.su Design set Ip Hz DC

Triode satAmplifiergain

Vast FIBPower consumpt

t.as.f.outitist.IEGoal Ip V o.su Peak to peak

Ip EknVof 0.4mA f 6MAN2 oof

Uff Vor I 0.5 V Vas Ven

Vas 0.5 0.7 1.2 V VG Us

Vs 1.2 V

Rp VDD.IO tdo5o4a5mnV

5kRRsVsqYss jf 3oz5kR

Ups Vp Vs D 5 C l 2 1.7 Vow 0,56

Assumption is Valid

7-7

Example Circuit (2)The resistor divider is a common bias circuit.To solve the DC bias condition, it means to solveID,VDS,VGS

The NMOS has Vtn =1V, kn = µnCoxWL=1mA /V 2

First, solve VG =VDDRG2

RG1 + RG2

=10 55+ 5

= 5V

VGS = 5− IDRS = 5− 6ID (with ID in mA)Next, assume the transistor is in saturation:

ID =12knvOV

2 = 0.5 VGS −Vtn( )2= 0.5 5− 6ID −1( )2

18ID2 − 25ID +8 = 0 --> ID = 0.89mA or 0.5mA

If ID = 0.89mA, VGS = −0.34V, NMOS will be cut-off--> not a physical solution.If ID = 0.5mA, VGS = 2V, VOV = 2−1=1VVDS =VDD − ID (RD + RS ) =10− 6 = 4V >VOVSaturation assumption verified !

e

As a design problem NMOS Van IV kn lmAVbD l0V

Design goal Ip 0.5mARa

Td k 44 Assume M is saturationMi VDS

Ip Knoff Oe5mARG2 Rs Instar

E Vof I Vor 1

Vo VGs Vt n UGS Vor Ve n It I ZU

Vas Vout Vein Design rule of thumb43 voltage drop to each element

Vbs 3 V Vow IVverify Mi is indeed in saturation

RD m8 Kr

Rs 310.5mA 6 KR

Vg 3 2 5 V

RG RGz Vg RG2VDD a gRa tRaz

what do we choose Ron RGz0 Choose large RG to minimize power consumption

choose e'S RG RG2 1 MI or to Mr

r.gg iIfgIIz9ateE5Tanmdwiaeh

7-8

PMOS I-V Curves

VGS = −2V

VGS = −3V

VGS = −4V

VGS = −1V

!"#

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sis

airingse

O

O

7-9

Right Side Up!

VSG = 2V

VSG = 3V

VSG = 4V

VSG = 1V

!"# = !#"

%"# = %#"

IsD

O

7-10

PMOS I-V Equations

Saturation Region:

iD =12µpCox

WL

!

"#

$

%& vGS − Vtp( )

2

=12µpCox

WL

!

"#

$

%&vOV

2

Triode Region:

iD = µpCoxWL

vOV vDS −12vDS

2"

#$

%

&'

vOV = vSG − VtpUse same equation as NMOS butadd absolute sign on all voltagessince most voltages are negative:Vtp < 0, vDS < 0, vGS < 0

So either use vSD or vDS

O O

step

7-11

Example Circuit (3)Design Problem: Design the circuit such that ID = 0.5mA and VD = 3V. PMOS has Vtp = −1V, µpCox (W / L) =1mA /V 2.Also find the maximum RD for PMOS to remain in Saturation

Solution:

ID =12kpVOV

2 = 0.5mA --> VOV =1V

VGS = Vtp + VOV =1+1= 2V

VS = 5V --> VG = 3VWe can choose RG1 = 2MΩ and RG2 = 3MΩ

Saturation: VD ≤ 5− VOV = 4V

RD,max =VD,max

I D=

40.5

= 8kΩ

µMostpositive

D

Vss mostnegative

sDesign examplepolos Veep IV Kp LMANZ

RG I 2 1 Designa goal Ip Oo5VA M M in saturation

3T feeUpRGL RD ID tzk Vof 0.5 MA

o I ir

IVGst IVovl IVL.pl I 2V

considerchannellength modulation

choose VD tzVbD 2o5

Host Ilbo Vol 2o5V t.VN V

zkpTofCHNVpsD 0.5mA µ indeed Tn saturation

Solving Bias DD Rai Rar

Problem by hand choose Ra Mr RGz 3 Mr

Vg Upp 3Ignore R RaitRGa

7-12

Finite Output Resistance due to Channel Length Modulation

When vDS = vOV , the channel pinch of near the Drain. With further increase in vDS, the pinch off point moves slowly towards the source, effectively reducing the channel length from L to L −ΔL (this is called "channel length modulation") :

iD =12µnCox

WL −ΔL

vGS −Vtn( )2

The continual increase of iD with vDS is modeled by

iD =12µnCox

WL

vGS −Vtn( )2 1+λvDS( )

4champifchoes

Real devicea

µ_

Noltudep of Visas

ras

VDS

Ip UncoxWI Voi indep of Vps

Channel length modulation

Pinch off Vps Vov Vas Kun

a

asevostureher

Io EunCox IoT Vof tuncox E Voi q

Eez 4 ET THear take

consider channel length modulation

Ip tuncox E Vof Haros

7-13

Output Resistance of MOSFETiD =

12µnCox

WL

vGS −Vtn( )2 1+λvDS( )

ro =∂vDS∂iD

#

$%

&

'(vGS=VGS

=∂iD∂vDS

#

$%

&

'(

−1

vGS=VGS

=1

λ12µnCox

WLVGS −Vtn( )2#

$%

&

'(≈

1λID

ro =1λID

where ID =12µnCox

WLVGS −Vtn( )2 is the DC bias current at Drain.

D

6To_Vds

Roh Ignored42 0

roioTF.EE ro fa ao

FoEoox as EEnIIIb consider R

oooo

To find VA

Ip O EunCox E Off It REVA

I AVA _o Va L Early Voltaget

Ii V Name derive fromBJT terminology