fe boards test & production g. auriemma, d. fidanza & c. satriano

FE boards test & production

G. Auriemma, D. Fidanza & C. Satriano

Muon Meeting 06/04/2004 CERN

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Summary

• Requirements• Automatic chip testing• Test capabilities in Potenza• How can it be increased• A duplicate system• SPB production


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Schedule7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2

NRE productionNRE packagingNRE validation

Production runCARIOCA testsDIALOG testsSYNC tests

FE boards productionFE boards assemblingFE boards testsChamber assemblingFE IC packagingSYNC packaging

30k IC packaged

2004 2005 2006

Boundary assumptions:

• No MPW, but more time allowed for NRE preparation: NRE submission scheduled date is 30 th June 04 (start 15th July) • Chips’ turnarounds: we assume 3 months for NRE Run and 5 months for Prod. Run (could happen to be less)• Test rate for CARIOCA: ~ 2k chips/month for NRE (or less), ~ 4k chips/month for production (mandatory)• Test rate for DIALOG: ~ 1k chips/month for NRE (or less), ~ 2k chips/month for production (mandatory)• Test rate for SYNC: ~ 800 chips/month (allowed to be less)• Test rate for FE boards: the same as DIALOG rate (half the CARIOCA rate)• Deliveries from the various production stages are organized in bunches. • If the NRE Run fails, we loose ~ 5 months (depends on the entity of the problem)

5k SYNC pack’d

LabCompany

Min Max


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Requirements

• Test rate for chips: 800/week from 15/6/05 to

15/11/05• Test rate for boards: 400/week from 15/7/05-15/12/05

Chip testing


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Chip test protocol (mostly Werner’s comments)

• The system with counters and injectors that allows the measure of sensitivity and offset variations is already there (Rio-FEET)

• The question that still has to be settled is whether the injector rise time of about 10ns is good enough for our purposes.

• Since pulse-width is a very crucial number for the system performance we need a TDC measurement. The discriminator output pulsewidth for 1 or 2 injected charge is therefore a crucial test parameter.

New injector (Potenza)

a TDC in the chain (Rio)


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Goal of the chip test• First goal is obviously to reject bad chips • It seems not really necessary to

calibrate each chip and write the calibration data to a database.

• We can decide to select chips according to a quality classification.

• The rejection level will be decided after measuring the first 100 or 200 chips from the production run.


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Manual/automatic chip handling

• 800 chips/week -> STD (INFN) week -> 2m10s/chip• ZIF sockets have a limited

operational life 5,000-10,000 insertions (?)• CMOS technology is sensitive to

statics


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Gravity feed handler


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55 (w) x 50 (d) x 50(h) cm313 kg

Do we need an hot/cold test ?


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Capabilities• For testing 500 to 5,000 devices a week • Handles most electronic devices shipped in tubes

(DIP, SIP, SOIC, SSOIC, PLCC, LCC, QFN, MLF, XTALS & Custom Conventional and Plunge-to-Board RF contacts )

• 2 tube manual input • 8 tube output with any combination sorts • Table top operation; • Micro terminal for current status, set up and

diagnostics


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Contacts


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• Contact pressure 10 to 12 grams / contact

• Contact height under 0.001” • -70° C to +200° C temperature range • Long life: over 1,000,000 contacts on

rigid material;• No wiping action required • Same electrical characteristics as a

solder connection:• Contact resistance under 3 milliOhms • Negligible capacity• Negligible inductance• Tested to 40 GHz


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Build the new injector card using a template custom

card


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Boards testing


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Goal of the board test• Verify assembly:

– spot systematic errors with a fast feedback to the production

– spot random errors (bad soldering etc.)

• Spot chips dead after tests• Calibrate gains, offsets and pulse

width (?) • Create a data base (!)


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Test standPulserDAC

32 ch VME scalers

LabViewsoftware

The test bench in Potenza


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The injector card


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• The test system in Potenza has been modified with the insertion of a Service Board for the control of the DIALOG

• A new LabView code has been written, suitable for testing CARDIAC

• Main modification is scanning in injected charge at constant threshold, because DIALOG DAC has 10 mV resolution


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Service Board in the chain

Provided by Rome I

To be done


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Raw data (S-curve)

0

20

40

60

80

100

120

5,5

7,5

9,5

11,5

13,5

15,5

17,5

19,5

21,5

23,5

25,5

27,5

29,5

31,5

33,5

ch. 0

ch. 1

ch. 2

ch. 3

ch. 4

ch.5

ch. 6

ch. 7

Injected charge (fC)

Nco

un

ts/N

ref


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Method

-20

0

20

40

60

80

100

120

22,5 27,5 32,5

Serie1

90%

10%

Q

Vth

K N


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Capabilities• With the present system (1 board/test

cycle) 20 boards in a day can be tested• Expanding to a system with 4 boards we

think we can go up to 80 boards in a day (not every day).

• How many boards/week ?• With present manpower we estimate

160-200• With one more operator perhaps 300-400

(marginally sufficient)• Would be safer to duplicate the system

with a cheaper solution


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SPB production• Layout ok• 120 PCB pre-series from CMT• 10 SPB in production• 120 could be ready next month• After a first check we have decided to buy

directly the components• Some bids already got -> purchase will be

done soon • Goal: all components in our hand before

June. (about 25,000 euros)


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• PCB will be also ordered (bids asked) we estimate 25,000 euros

• Assembly can be contracted likely starting from July with additional funding

• Possible to have 50% in 2004 and the rest before June 2005 if funds are requested now

fe boards test & production g. auriemma, d. fidanza & c. satriano

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