2-1

FCC in HDLC Mode

What youwill learn

• What is an FCC?• What are the FCC pins?• How an FCC operates• What is FCC parameter RAM• What is FCC protocol specific parameter RAM• How to select and configure the clocks• How an FCC transmits and receives in HDLC• How to initialize an FCC for HDLC

2-2

HDLC is a synchronous protocol that transfers data in frames. Often usedto transmit and receive data.

Definition

Example

What is HDLC?

Flag Addr Cntrl Data CRC Flag

Flag: The opening and closing octet of a frame. Equal to 0x7EAddr: The destination address of the frame. 8 or 16 bits.Cntrl: The control field. Not used by the HDLC controller. 8 or 16 bits.CRC: Error calculation. 16 or 32 bits.

Stored in transmit buffer

Stored in receive buffer

FCC-HDLCFeatures

• Buffer descriptors in external memory• Transfers data up to T3 rate• Time stamp mode for receive frames• Nibble mode selectable

• Flag/abort/idle generation/detection• Zero insertion/deletion• 16 or 32 bit CRC generation and checking• Multiple buffers per frame possible• Separate interrupts for receive frame and receive buffer• Receive frames interrupt threshold• Four address comparison registers with mask• Maintains four 16-bit error counters:

- Number of frames discarded due to lack of buffers- Number of frames with CRC error- Number of frames aborted- Number of frames with non-matching address

• Programmable number of flags between frames, 0-15

SCC & FCCFeatures

2-3

FCCx

RequestPrioritizer

CPMRISC

RxFIFO

TxFIFO

BTMDPRAM3

SDMA

SDMA

An FCC is a high-speed communication device capable transferring datain HDLC, Ethernet or ATM.

Definition

Example

External Memory

What is an FCC?

1. Data is received in the Rx FIFO.2. FCCx requests service from CPM RISC.3. CPM RISC checks the address. If the address is for this FCC, the CPM RISCdirects the BTM to transfer the FIFO data to dual-port RAM.4. The SDMA transfers data from the dual port RAM to current buffer in memory.

ReceiveOperation

1. Space is available in the transmit FIFO.2. FCCx requests service from CPM RISC.3. CPM RISC directs the BTM to transfer data from dual-port RAM to the transmitFIFO.4. The SDMA transfers data from the current buffer in memory to dual-port RAM.

TransmitOperation

1. Buffer descriptors and buffers reside in external memory, either on 60x bus or localbus.2. The BTM (Block Transfer Module) moves data between dual-port RAM and FIFO.The BTM removes the burden from the CP of transferring datato/from the FIFOs3. The FIFOs are 192 bytes deep.

Description

2-4

What are the FCC pins?

FCC PinSummary

• FCCx:TXD - transmit pins• FCCx:RXD - receive pins• FCCx:CD - carrier detect pins• FCCx:CTS - clear-to-send pins• FCCx:RTS - request-to-send pins

PA[17]/FCC1:RxD[0]:RxD[7]:RxD[15]

Introduction The following diagram summarizes the FCC pins for HDLC and transparent.

PA[16]/FCC1:RxD[1]:RxD[6]:RxD[14]PA[15]/FCC1:RxD[2]:RxD[5]:RxD[13]PA[14]/FCC1:RxD[3]:RxD[4]:RxD[12]PA[18]/FCC1:TxD[0]:TxD[7]:TxD[15]PA[19]/FCC1:TxD[1]:TxD[6]:TxD[14]PA[20]/FCC1:TxD[2]:TxD[5]:TxD[13]PA[21]/FCC1:TxD[3]:TxD[4]:TxD[12]PA[30]/FCC1:RTS:TxClav:CRSPC[6]/FCC1:CD:RxAddr[2]:RxClav[1]/FCC2:RxAddr[2]/TDM_C1:L1CLKOPC[7]/FCC1:CTS:TxAddr[2]:TxClav[1]/FCC2:TxAddr[2]/TDM_C1:L1RQ

FCC1 PinExample

1. Each FCC has five pin types available in HDLC: transmit, receive, carrierdetect, clear-to-send, and request-to-send.2. If the FCC-HDLC controller is programmed for nibble mode, then 4 transmitand 4 receive pins are available. If nibble mode is not selected, then onlyRxD[0] and TxD[0] are available.

Description

2-5

Programming Model (1 of 5)GFMRx - General FCC Mode Register P. 28-30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

-CTSS

CDS

CTSP

CDP

TTX

TRXTCIDIAG

MODEENT

ENRTENCRE

VDRENC

TOD

SYNL TCRC

FDSRx - FCC Data Synchronization Register P. 28-70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SYN1SYN2

FTODRx - FCC Transmit-on-Demand Register P. 28-70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

-

RTSM

2-6

Programming Model (2 of 5)FPSMRx - HDLC Mode Register P. 31-70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

--MFF

FSENOF

-- CRC

TS

NIB

FCCEx/FCCMx - HDLC Event/Mask Register P. 31-140 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

-

--

GRA - TX

ERXF

BSY

TXB

RXB

IDL

FLG

FCCSx - FCC Status Register P. 31-160 1 2 3 4 5 6 7

FG- - ID

1. FPSMRx - TS enables the time stamp feature. When a frame is received, thetime stamp is the first 4 bytes copied to the receive buffer. NIB enables thenibble mode.2. FCCEx/FCCMx - FLG sets when the FG bit in SCCS changes state.3. FCCSx - FG sets when flags are detected.

Description

2-7

FCC Base + 00 RIPTR halfword FCC Base + 02 TIPTR halfword FCC Base + 04 halfword FCC Base + 06 MRBLR halfword FCC Base + 08 R(FCR)State word FCC Base + 0C RBASE word FCC Base + 10 RBDSTAT halfword FCC Base + 12 RBDLEN halfword FCC Base + 14 RDPTR word FCC Base + 18 T(FCR)State word FCC Base + 1C TBASE word FCC Base + 20 TBDSTAT halfword FCC Base + 22 TBDLEN halfword FCC Base + 24 TDPTR word FCC Base + 28 RBPTR word FCC Base + 2C TBPTR word FCC Base + 30 RCRC word FCC Base + 34 TCRC wordFCC Base + 38

Address Name Width DescriptionPointer to temp. Rx 32 byte bufferPointer to temp. Tx 32 byte bufferreservedMax. Rx Buffer LengthFunction codes & Rx Internal stateBase pointer to Buffer descriptorsRISC RxBD status & controlRxBD data length - down countnext Rx buffer Function codes & Tx Internal stateBase pointer to Buffer descriptorsRISC TxBD status & controlTxBD data length - down countnext Tx buffer next/current RxBD to usenext/current TxBD to useTemp Rx CRCTemp Tx CRC

First word of Protocol specific AreaFirst word of Protocol specific Area

FCCx Parameter RAM P. 28-11

Programming Model (3 of 5)

1. Bolded items must be initialized by the user.2. The function codes are the most significant byte in TSTATE and RSTATE.

Description

2-8

Programming Model (4 of 5)FCRx - Function Code Register P. 28-120 1 2 3 4 5 6 7

TC2

GBL BO- DT

BBDB

RxBD - HDLC Receive Buffer Descriptor P. 31-90 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

-FLE - W I CM LG NO AB CR OV CD

Data Length

Rx Data Buffer Pointer

TxBD - HDLC Transmit Buffer Descriptor P. 31-120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

-TCLR - W I CM UN CT

Data Length

Tx Data Buffer Pointer

1. GBL - global:if set, the GBL pin will be asserted to indicate to other busmasters that a shared area is being accessed.2. BO - byte order:indicates either big-endian or PPC little-endian.3. TC2 - transfer code pin 2 is driven with this value when this FCC is thesource of the access.4. DTB - indicates if the data buffers are on local or 60x bus.5. BDB - indicates if interrupt queues and free buffers are on local bus or 60xbus.

Descriptionof FCRx

2-9

FCCx HDLC Parameter RAM P. 31-4

Address Name Width Description

FCC Base + 0x44FCC Base + 0x48

C_MASKC_PRES words CRC constant

CRC presetFCC Base + 0x4CFCC Base + 0x4EFCC Base + 0x50FCC Base + 0x52FCC Base + 0x54

DISFCCRCECABTSCNMARCMAX_CNT

halfwords

word

Discarded frame countCRC error countAbort sequence countNonmatching address Rx countMax_length down counter

FCC Base + 0x58FCC Base + 0x5AFCC Base + 0x5C

MFLRRFTHRRFCNT

Max. frame lengthReceived frames thresholdReceived frames count (down)

FCC Base + 0x5EFCC Base + 0x60FCC Base + 0x62FCC Base + 0x64FCC Base + 0x66

HMASKHADDR1HADDR2HADDR3HADDR4

halfwords User-defined frame address maskUser-defined frame addressUser-defined frame addressUser-defined frame addressUser-defined frame address

Programming Model (5 of 5)

2-10

Restart Transmit

StopTransmit

Restart Transmit

The following state diagram shows the basic operation of the FCC-HDLCtransmitter.

Introduction

StateDiagram

How the FCC-HDLC Controller Transmits Data

xmitenabled

GFMRx[ENT]=1

TxBD[R]=1& CTS*=0

xmit Endframe

TxB sent &TxBD[L]=1

Flag appended & FCCEx[GRA]=0

Closebuffer

TxB sent &TxBD[L]=0

TxBD[R]=1

gracefulstop

Flag appended &FCCEx[GRA]=1

Abort

Descriptionof States

1. Xmit Enabled - transmits idles or flags depending on GFMRx[RTSM].2. Xmit - transmits additional flags if necessary to meet the minimum; then transmitsfrom the data buffer.3. Close Buffer - clears TxBD[R] (unless TxBD[CM] is set); if TxBD[I] is set,FCCEx[TxB] is set. FCCx[TBPTR] is incremented to the next buffer descriptor.4. End Frame - if TxBD[TC]=1, the CRC is appended. Clears TxBD[R] (unlessTxBD[CM] is set); if TxBD[I] is set, FCCEx[TxB] is set. FCCx[TBPTR] isincremented to the next buffer descriptor.5. Graceful Stop - transmits idles or flags depending on GFMRx[RTSM].6. Abort - transmits no more than 64 bits, flushes the transmit FIFO, and transmitsthe abort sequence, 0x7F. Then transmit flags or idles depending onGFMRx[RTSM].

CTS lost &Underrun

1. If CTS* becomes high or if a transmit underrun occurs, transmit will not beginagain until a restart transmit command is executed.

2-11

The following state diagram shows the basic operation of the FCC-HDLCreceiver.

Introduction

StateDiagram

How the FCC-HDLC Controller Receives Data

recvhunt

GFMRx[ENR]=1

Non-flagoccurs

addresscheck recv

Flag received

endframe

nomatch

Match &RxBD[E]=1

Flagreceived

Closebuffer

RxB fullRxBD[E]=1

frametoo long

Flagrecv’d1

1. Frame length > FCCx[MFLR]

Descriptionof States

1. Recv Hunt - waits for a flag followed by a non-flag.2. Address Check - determines if the address of the frame matches one of the fouraddress registers, FCCx[MASKy], combined with the mask, FCCx[HMASK].3. Recv - moves incoming data to the current receive buffer.4. Close Buffer - clears RxBD[E] (unless TxBD[CM] is set); if RxBD[I] is set,FCCEx[RxB] is set. FCCx[RBPTR] is incremented to the next buffer descriptor.5. End Frame - checks the CRC; if error, sets RxBD[CR] and increments CRCEC.Writes the frame length to the data length field. RxBD[L] is set. Clears RxBD[E](unless TxBD[CM] is set); if RxBD[I] is set, FCCEx[RxB] is set. FCCx[RBPTR] isincremented to the next buffer descriptor. Decrements FCCx[RFCNT]; if zero,FCCEx[RxF] is set. If frame was too long, RxBD[LG] is set.6. Frame Too Long - no more data is received, but the octet count continues.

Errors 1. If a non-octet aligned frame is received, RxBD[NO] is set.2. If the abort sequence, 0x7F, is received, RxBD[AB] is set, RxBD[E] is cleared,and FCCx[ABTSC] is incremented. The receiver then goes to recv hunt.3. If a CRC error occurs, RxBD[CR] is set, and FCCx[CRCEC] is incremented.4. If an overrun error occurs, RxBD[OV] is set, and the buffer is closed.5. If a CD lost error occurs, RxBD[CD] is set, and the buffer is closed.

2-12

The following diagram describes how to connect a clock source to anFCC.

Introduction

ProgrammingModel

How to Provide the FCC Clocks

CMXFCR - FCC Clock Route Register P. 15-120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

-

--

-

FC1

FC3

RF1CS RF2CS

RF3CS

TF1CS FC2 TF2CS

TF3CS

The FCCs on an 8260 are to have the following connections:

FCC123

NMSIYYN

Recv CLK Xmit CLKCLK9BRG8

-

BRG6CLK14

-

Write the initialization value for CMXFCR.

pimm->CMXFCR = 0x211D4000;

Example

1. Clock sources are connected to the FCCs by way of the CMXFCR.2. Each FCC has one byte to connect the clocks. Each byte has a field as follows:

- FCx - connects the FCC to either its NMSI pins or to the TSA.- RFxCS - connects the receiver to one of eight clock sources.- TFxCS - connects the transmitter to one of eight clock sources.

Description

2-13

The following diagram describes how to initialize a baud rate generatorfor a particular bit rate.

Introduction

ProgrammingModel

How to Initialize a Baud Rate Generator

BRGCx - BRG Configuration Register P. 16-20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

- EN

EXTC CD

BRG 4 is to be configured to generate 500Kbps bit rate. The input clock isCLK15 which is 33MHz. Write the initialization value for BRGC4.

pimm->BRGC4 = 1<<16 + 2<<14 + 65<<1;

Example

RST

AB DIV16

CD = (ClkFreq/(bit rate * DIV16)) - 1 = (33 * 106/(.5 * 106 * [1 or 16])) - 1 = (33/.5) - 1 = 66 -1 = 65

1. Eight baud rate generators are available to be used as internal clock sources tothe FCCs.2. The output bit rate of a BRG is determined by the clock input frequencydivided by BRGx[DIV16], 1 or 16, and divided by a count value in BRGx[CD].3. Also, a clock input must be selected in BRGx[EXTC] and the baud rategenerator must be enabled in BRGx[EN].

Description

2-14

How to Initialize an 8260 FCC for HDLC (1 of 6)

Step Action Example

1 Configure ports as required pimm->pdira=0x3C00;pimm->ppara=0xFC00;

2

If an internally generated clock isto be used, initialize Baud Rate Configuration Reg, BRGCn

pimm->BRGC4=0x14330;

CD:clock dividerDIV16: prescalarEXTC:clock source selectEN: enable BRGRST: reset BRG (16-2)

3

Initialize the FCC Clock RouteReg, CMXFCR

pimm->CMXFCR=0x211D00;

FCn:select NMSI or TDMRFnCS:recv clock selectTFnCS:xmit clock select

(15-12)

Assumption Hard reset conditions exist.

Stepsin the

InitializationProcedure

2-15

How to Initialize an 8260 FCC for HDLC (2 of 6)

Step Action ExampleStep Action Example

4

Initialize the General FCC ModeReg, GFMR

pimm->GFMR=0x2000;

DIAG:normal,loopback, or echoTCI:transmit clock invertCTSP:CTS pulse or envelopeCDS:CD sampl sync or asyncCTSS:CTS sampl sync or asyncRTSM:idles or flagsRENC:NRZ or NRZITENC:NRZ or NRZIMODE:select HDLC

(28-3)

Stepsin the

InitializationProcedure

2-16

How to Initialize an 8260 FCC for HDLC (3 of 6)

Step Action Example

5

Initialize the FCC HDLC ModeReg, FPSMR

pimm->FPSMR=0x10408000;

NOF:no. of flags between frmsFSE:flag sharing enableMFF:multiple frames in FIFOTS:time stampNBL:nibble modeCRC:16 or 32 bit CRC

(31-7)

Stepsin the

InitializationProcedure

6

Initialize the FCC ParameterRAM

pimm->FCC1.RSTATE= 0x10<<24;

RIPTR:recv DPRAM3 pointerTIPTR:xmit DPRAM3 pointerMRBLR:max recv buffer lngthRSTATE:recv internal stateRBASE:RxBD base addressTSTATE:xmit internal stateTBASE:TxBD base address

(28-10)

2-17

How to Initialize an 8260 FCC for HDLC (4 of 6)

Step Action Example

7

Initialize RxBDs pdsc->RxBD2.rxbdsac= 0x9000;rxbdptr:pointer to data buffer

rxbddl:data lengthrxbdsac:status and control

(31-9)

Stepsin the

InitializationProcedure

8

Initialize TxBDs pdsc->TxBD1.txbddl=50;

txbdptr:pointer to data buffertxbddl:data lengthtxbdsac:status and control

(31-12)

2-18

How to Initialize an 8260 FCC for HDLC (5 of 6)

Step Action Example

9

Initialize the FCC Mask Reg,FCCMn

pimm->FCCM2=0xA;

GRA:graceful stopTXE:xmit errorRxF:receive frameBSY:busyTxB:xmit buffer sentRxB:recv buffer closedFLG:flag statusIDL:idle status change (31-14)

Stepsin the

InitializationProcedure

10

Initialize FCC Priority, SCPRR_H

pimm->SCPRR_H = 0x21309770;

XCxP:priority order(4-19)

11

Initialize Interrupt Mask Reg,SIMR_L

pimm->SIMR_L |= 1<<30;

FCCn:interrupt mask bit(4-22)

2-19

How to Initialize an 8260 FCC for HDLC (6 of 6)

Step Action Example

12

Initialize Rx/Tx Parameters viaCommand Reg, CPCR

pimm->CPCR=0x16210002;

PAGE:page numberSBC:sub-block codeFLG:command semaphore flagMCN:protocol codeOPCODE:operation code

(13-12)

Stepsin the

InitializationProcedure

13

Enable transmitand/or receive inGFMR

pimm->GFMR |= 1<<4;

ENR:enable receiveENT:enable transmit (28-3)

2-20

HDLC Example (1 of 3)/* This is an example of receiving a buffer of data. The *//* receive buffer closes either if it is filled or if a *//* frame is completed. When the buffer is closed, an LED *//* counter is incremented. */

void *const stdout = 0; /* STANDARD OUTPUT DEVICE */#define hdlcf3 /* FCC3 IS TO BE HDLC */#include “mpc8260.h” /* INTNL MEMORY MAP EQUATES */extern struct immbase *pimm; /* POINTER TO INTNL MEMORY MAP*/struct descs { rxbdfh RxBD0; /* RECEIVE BUFFER 0 */ };struct descs *pdsc; /* POINTER TO DESCRIPTOR */

main(){ clrdpr(); /* CLEAR DUAL PORT RAM */ pimm->PDATD = 0; /* CLEAR PORT D DATA REG */ pimm->PDIRD = 0xFF; /* MAKE PORT D24-31 OUTPUT*/

2-21

HDLC Example (2 of 3) pimm->PPARB = 0x00F00000; /* PB8-11 ARE RxD0,1,2,3 */ pimm->BRGC6 = 1<<16 + 129<<1 + 1; /* 64Kbps AT 133 MHz */ pimm->CMXFCR = 0x800; /* ROUTE BRG6 TO FCC3 */ /* INIT GFMR3: FROM RESET GFMR IS ZERO WHICH IS REQ’D */ pimm->FPSMR3 = 0x10408080; /* 1 FLAG BETWEEN FRAMES */ /* ENABLE TIME STAMP, */ /* NIBBLE MODE,32-BIT CRC*/ pimm->FCC3.RIPTR = 0xB000 + 128; /* INIT TEMP RECV PNTR */ pimm->FCC3.MRBLR = 1000; /* MAX RECV BUFFER=1KBYTE*/ pimm->FCC3.RSTATE = 0x11<<24; /* BIG ENDIAN,BDS LOCAL */ pimm->FCC3.RBASE = 0x100000; /* RxBDS AT 0x100000 */ pdsc = (struct descs *) 0x100000; /* INIT PNTR TO RxBD */ pdsc->RxBD0.rxbdptr = 0x200000; /* Rx BUFFER AT 0x200000 */ pdsc->RxBD0.rxbdsac = 0xB000; /* INIT SAC EMPTY,WRAP, &*/ /* INTERRUPT */ /* NO TRANSMIT REQUIREMENT, THEREFORE NO TxBDS */ /* NO INTERRUPTS, THEREFORE FCCM3 IS NOT CHANGED */ /* DEFAULT PRIORITY ORDER OK, THEREFORE SCPRR_H NOT CHNGD*/ /* NO INTERRUPTS,THEREFORE SIMR_L IS NOT CHANGED */ pimm->CPCR = 0x1A410001; /* INIT Rx PARAMETERS */ while ((pimm->CPCR & (1<<16)) == 1<<16);

2-22

HDLC Example (3 of 3) pimm->GFMR3 |= 1<<5; /* ENABLE RECEIVE */ while ((pimm->FCCE3 & (9<<16)) == 0); /* WAIT FOR EVENT*/ pimm->PDATD += 1; /* INCREMENT PORT D */}

clrdpr(){ UWORD *pint; /* integer pointer */

pint = (UWORD *)(UWORD)pimm; for (i = 0; i < 0x1000; i++) /* CLEAR DPRAM1 */ *pint++ = 0; pint = (UWORD *)((UWORD)pimm + 0x8000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM2 */ *pint++ = 0; pint = (UWORD *)((UWORD)pimm + 0xB000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM3 */ *pint++ = 0;}

2-23

HDLC Exercise (1 of 3)/* This is an example of transmitting on FCC1 in HDLC. A *//* frame of data is transmitted using two buffers. When the*//* second buffer has been sent, the LED counter on Port D *//* is incremented. */

void *const stdout = 0; /* STANDARD OUTPUT DEVICE */#define hdlcf1 /* FCC1 IS TO BE HDLC */#include “mpc8260.h” /* INTNL MEMORY MAP EQUATES */extern struct immbase *pimm; /* POINTER TO INTNL MEMORY MAP*/struct descs { txbdfh TxBD0; /* TRANSMIT BUFFER 0 */ txbdfh TxBD1; /* TRANSMIT BUFFER 1 */ };struct descs *pdsc; /* POINTER TO DESCRIPTOR */

main(){ clrdpr(); /* CLEAR DUAL PORT RAM */ pimm->PDATD = 0; /* CLEAR PORT D DATA REG */ pimm->PDIRD = 0xFF; /* MAKE PORT D24-31 OUTPUT*/

2-24

HDLC Exercise (2 of 3) pimm->PPARB = 0x08000000; /* PB4 IS TxD */ pimm->BRGC7 = 1<<16 + __<<1 + 1; /* 256Kbps AT 133 MHz */ pimm->______ = 0x2000000; /* ROUTE BRG7 TO FCC1 */ pimm->GFMR1 = 0x____; /* FLAGS BETWEEN FRAMES */ pimm->______ = 0x20000000; /* 2 FLAGS BETWEEN FRAMES*/ /* NO TIME STAMP, NOT */ /* NIBBLE MODE,16-BIT CRC*/ pimm->FCC1.TIPTR = 0x____ + 32; /* INIT TEMP XMIT PNTR */ pimm->FCC1.______ = 0x12<<24; /* BIG ENDIAN,BUFS LOCAL */ pimm->FCC1._____ = 0x200000; /* TxBDS AT 0x200000 */ pdsc = (struct descs *) 0x200000; /* INIT PNTR TO TxBD */ pdsc->TxBD0.txbdptr = 0x400000; /* Tx BUFFER0 AT 0x400000*/ pdsc->TxBD0.txbddl = 100; /* INIT DATA LNGTH TO 100*/ pdsc->TxBD0.txbdsac = 0x____; /* INIT SAC READY */ pdsc->TxBD1.txbdptr = 0x400800; /* Tx BUFFER1 AT 0x400800*/ pdsc->TxBD1.txbddl = 100; /* INIT DATA LNGTH TO 100*/ pdsc->TxBD1.txbdsac = 0x____; /* INIT SAC READY,WRAP */ /* INTRPT,LAST,APPEND CRC*/ /* NO RECEIVE REQUIREMENT, THEREFORE NO RxBDS */ /* NO INTERRUPTS, THEREFORE FCCM1 IS NOT CHANGED */ /* DEFAULT PRIORITY ORDER OK, THEREFORE SCPRR_H NOT CHNGD*/

2-25

HDLC Exercise (3 of 3)/* NO INTERRUPTS,THEREFORE SIMR_L IS NOT CHANGED */ pimm->CPCR = 0x________; /* INIT Tx PARAMETERS */ while (pimm->CPCR & (1<<16)) == 1<<16); /*WAIT FLAG CLEAR */ pimm->_____ |= 1<<4; /* ENABLE TRANSMIT */ while ((pimm->FCCE1 & (_<<16)) == 0); /* WAIT FOR EVENT */ pimm->PDATD += 1; /* INCREMENT PORT D */}

clrdpr(){ UWORD *pint; /* integer pointer */

pint = (UWORD *)(UWORD)pimm; for (i = 0; i < 0x1000; i++) /* CLEAR DPRAM1 */ *pint++ = 0; pint = (UWORD *)((UWORD)pimm + 0x8000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM2 */ *pint++ = 0; pint = (UWORD *)((UWORD)pimm + 0xB000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM3 */ *pint++ = 0;}