TSINGHUA SCIENCE AND TECHNOLOGY ISSN 1007-0214 35/49 pp197-201 Volume 12, Number S1, July 2007

Fault-Tolerant Design and Testing of USB2.0 Peripheral Devices IP Core System

BAI Xiaoping (白晓平)1,2,**, WEI Yuanfeng (韦援丰)2

1. School of Management, Xi’an University of Architecture & Technology, Xi’an 710055, China; 2. School of Electronics & Information Engineering, Xi’an Jiaotong University, Xi’an 710049, China

Abstract: Universal serial bus 2.0 (USB2.0) is a kind of mainstream interface technology. The traditional

USB developing is only to develop USB peripheral devices. For the USB2.0 peripheral devices IP core sys-

tem that has wide application foreground, some interference inevitably exists in signal transmitting. Some

fault-tolerant design and test methods must be adopted in order to correctly transmit and receive data.

Combining with a project, this paper introduces in detail about measures, hardware implement, and test

methods of fault-tolerant design about USB2.0 peripheral devices IP core system. Fault-tolerant design

measures, noise reduction measures of signal processing, fault-tolerant methods about data encode and

decode, package identification (ID) field fault-tolerant methods, and cyclic redundancy checks fault-tolerant

methods are discussed. The paper also presents some hardware implement methods about fault-tolerant

design of data decode and test methods about fault-tolerant design of USB2.0 IP core system. These meth-

ods can offer the reference for development of USB2.0 system in all kinds of electronics instrumentations.

Key words: universal serial bus; fault-tolerant; diagnosis; testing; hardware; signal processing

Introduction

Universal serial bus (USB) is now a standard feature on all PCs and makes it much easier for users every-where to plug in everything from digital cameras to MP3 players to their PCs. USB offers several benefits such as low cost, expandability, auto-configuration, hot-plugging, and outstanding performance[1]. It also provides power to the bus, enabling many peripherals to operate without the added need for an AC power adapter[2]. As the newest version of USB, USB2.0 has become a kind of mainstream interface technology that has wide application foreground. USB2.0 system con-sists of USB host control chip and equipment interface control chip, i.e., peripheral device chip[3]. The host control chip was usually integrated in the chip groups

of personal computer, its function is single, and some large chip group manufacturers often control its tech-nologies. So the traditional USB developing is only to develop USB peripheral devices. USB2.0 peripheral devices intellectual property (IP) core is a block of logic or data that is used in making a field programma-ble gate array (FPGA) or application-specific inte-grated circuit (ASIC) for a USB2.0 product. It has wide application in VLSI design field. Typical USB2.0 peripheral devices IP consist of serial interface engine (SIE), USB2.0 transceiver macrocell interface (UTMI), endpoint controller, memory management unit (MMU), memory control unit (MCU), direct memory access (DMA), etc. For USB2.0 peripheral devices IP core system, some interference inevitably exists in signal transmitting. Some fault-tolerant design and test meth-ods must be adopted in order to transmit and receive data correctly. Combining with actual project, this pa-per introduces in detail these methods.

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Received: 2007-02-01 To whom correspondence should be addressed. E-mail: xxppbai@163.com; Tel: 86-29-82205277

Tsinghua Science and Technology, July 2007, 12(S1): 197-201 198

1 Fault-Tolerant Design Measures 1.1 Noise reduction measures for signal

processing

USB host and devices make use of difference input and output technology to improve the immunity of data transfers. On inputting data, the difference signals D+ and D− of USB are converted into single-port-coupled signal by differential amplifier, which can reduce effec-tively noise signal because of its big common-mode re-jection ratio[4,5]. Theoretically, data can be gotten cor-rectly so long as electric potential difference of D+ and D− is bigger than the least differentiate voltage of dif-ferential amplifier[6]. According to USB2.0 specification, data should be gotten on condition that electric potential difference of D+ and D− is bigger than 200 mV. On out-putting data, single-port-coupled signal needs to be con-verted into difference signal.

In USB2.0, data package is transmitted by difference signal. Start of package (SOP) of source port can be achieved by switching D+ and D− from idle state to its opposition logic level, this is called K state. The first bit of SYNC words expresses this switch. When the next sending time is less than 5 ns, the hub must re-strict its width of the first bit. Data matching can be achieved by hub with delay output enable; these meas-ures can reduce effectively data distortion.

1.2 Fault-tolerant methods about data encoding and decoding

1.2.1 Bit stuffing and none return zero invert (NRZI) encoding

On transmitting packages, USB2.0 employs NRZI en-coding method. In this encoding, a “1” (Fig. 1a) is rep-resented by no change (Fig. 1b) in level and a “0” (Fig. 1a) is represented by a change in level (Fig. 1b). Figure 1 shows a data stream and the NRZI equivalent. The high level represents the J state on the data lines in this and subsequent figures showing NRZI encoding. A string of zeros causes the NRZI data to toggle each bit time. A string of ones causes long periods with no tran-sitions in the data.

In order to ensure adequate signal transitions, bit stuffing is employed by the transmitting device on sending a packet on USB[7,8]. A zero is inserted after every six consecutive ones in the data stream before the data is NRZI encoded, to force a transition in the

Fig. 1 Data stream (a) and the NRZI encoding (b) diagram

NRZI data stream. This gives the receiver logic a data transition at least once every 7-bit time to guarantee the data and clock lock. Bit stuffing is enabled begin-ning with the Sync pattern. The data “one” that ends the Sync pattern is counted as the first one in a se-quence. Bit stuffing by the transmitter is always en-forced, except during high-speed end-of-packet (EOP). If required by the bit stuffing rules, a zero bit will be inserted even if it is the last bit before the EOP signal. 1.2.2 NRZI decoding On data encoding, the bit stuffing is first carried out, then NRZI encoding is achieved. However, on decod-ing, NRZI decoding is firstly carried, and then the bit stuffing is removed. The receiver must decode the NRZI data, recognize the stuffed bits, and discard them by this measure, if seven consecutive ones in the data stream in receiver are found, then a bit stuffing error will occur, and this data package will be ignored[9]. 1.2.3 Removing bit stuffing The goal of removing bit stuffing module is to discard the “0” behind six consecutive “1”. When the “0” is found behind six consecutive “1”, stuffing is high.

1.3 Package identification (ID) field fault-tolerant methods

A packet identifier (PID) immediately follows the SYNC field of every USB packet. A PID consists of a four-bit packet type field followed by a four-bit check field. The PID indicates the type of packet and, by in-ference, the format of the packet and the type of error detection applied to the packet. The four-bit check field of the PID ensures reliable decoding of the PID so that the remainder of the packet is interpreted correctly. Performing a one’s complement of the packet type field generates the PID check field. A PID error exists if the four PID check bits are not complements of their respective packet identifier bits.

The host and all functions must perform a complete decoding of all received PID fields. Any PID received

BAI Xiaoping (白晓平) et al：Fault-Tolerant Design and Testing of USB2.0 Peripheral … 199

with a failed check field or which decodes to a non-defined value is assumed to be corrupted, as well as the remainder of the packet, is ignored by the packet re-ceiver. If a function receives an otherwise valid PID for a transaction type or direction that it does not sup-port, the function must not respond.

1.4 Cyclic redundancy checks (CRC) fault-tolerant methods

Cyclic redundancy checks are used to protect all non-PID fields in token and data packets. In this context, these fields are considered to be protected fields. The PID is not included in the CRC check of a packet con-taining a CRC. All CRCs are generated over their re-spective fields in the transmitter before bit stuffing is performed. Similarly, CRCs are decoded in the re-ceiver after stuffed bits have been removed. Token and data packet CRCs provide 100% coverage for all sin-gle- and double-bit errors. A failed CRC is considered

to indicate that one or more of the protected fields is corrupted and causes the receiver to ignore those fields and, in most cases, the entire packet.

2 Hardware Implement Methods of Fault-Tolerant Design

2.1 Hardware implement for data decode

The clock produced in digital phase locked logic (DPLL) implements NRZI decoding. The principle can be described as follows. A variable t is set in module, the origin value of t is 1. When a value is sampled, it will be compared with t, if equal to t, then output 1. otherwise output 0, and t is changed into sampling value. The waveform diagram of designed hardware codes is shown in Fig. 2. The output of data via DPLL is data1, and the output of data1 via NRZI decoding is data2.

Fig. 2 Waveform diagram of NRZI decoding

2.2 Hardware implement for package ID field

On designing PID detection module, the working time sequence must be thought. PID consists of 8 data be-hind SYNC output because PID immediately follows the SYNC field of every USB packet. So SYNC can be thought as the ready signal of PID. If the former 4 bits of PID is contrary to the later 4 bits, then PID is correct,

then next detecting can be implemented by the type of PID; otherwise, PID is thought as being false, then pid_err is outputted, and simultaneously this package is ignored. The detection waveform diagram of de-signed hardware codes is shown in Fig. 3. When SYNC is high, the former 4 bits of parallel data is as-signed to PID; subsequent 4 bits is assigned to PIDT. The value of PID is 1001 while the value of PIDT is

Fig. 3 Waveform diagram of NRZI PID detection

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0110, that is, they are in reverse each other. So PID is correct, and this package can be identified as token package. The 16 bits data behind PID represents equipment address, endpoint ID, and CRC5 code. When next SYNC is high, the other package begins. At this time, the value of PID is 1101 while the value of PIDT is 1001. The former is not contrary to the later, and PID is thought as being false. So pid_err is high and cannot output data of this package.

2.3 Hardware implement for CRC

On starting CRC generator, 16’ffff is assigned to re-mainder register. If the NOR result of current transmit-ted or received data and the highest bit is “1”, right data of remainder register is shifted, then NOR opera-tion of it and divisor multinomial is executed. The re-sult is returned to remainder register. On the other hand, If the NOR result of current transmitted or received data and the highest bit is “0”, only right data of re-mainder register is shifted, then the result is returned to remainder register. When completing all bit operation, executing NOT operation for values of remainder reg-ister can get CRC.

The check processing of CRC is the same as above introduction. But on checking, detected data and CRC codes together should be thought as data of above processing. After all operation is completed, data of remainder register is fixed. For CRC5, this value is 01100, for CRC16, this value is 1000000000001101. If the result is the same as above value, then the package is thought to pass CRC check, or else, the package is false.

3 Testing

This paper uses utmi_fz Flexmodel in the SmartModel tools and additional tasks to design a simulation vali-dation system. utmi_fz Flexmodel has functions of USB2.0 host and UTMI, so it can be used for testing USB2.0 interface protocol control hardware circuit codes. The whole simulation process is achieved by nc-verilog language in SUN workstation[10-12].

3.1 The testing of transmitting data

The following transmit command is used to perform the following transaction:

(1) Send an OUT token;

(2) Send the DATA1 PID with data payload of 3 bytes, from a specified bank (DBANK1);

(3) Expect a handshake of type ACK from function utmi_transmit_data(UTMI_Inst_1_cmd, `OUT_PID, 7'b1010101, 4'b1100, `DATA1_PID, 3, `DATA_BANK_ EN, `DBANK1, 8’b11001010, `HS_EN, `ACK_HS, `FLEX_WAIT_F status).

3.2 Testing of receiving data

The following receive command is used to perform the followsing transaction:

(1) Send an IN token; (2) Receive DATA0 PID with data payload of 3

bytes; (3) Send a handshake to the function

utmi_receive_data(UTMI_Inst_1_cmd,7'b1010101,4'b1100,`DATA0_PID,3,`DATA_CMP_DS,`DATA_BANK_DS,`DBANK1,8'b11011010,`HS_EN,`FLEX_WAIT_F,status).

4 Conclusions

USB2.0 is a kind of mainstream interface technology that has many advantages. USB2.0 peripheral devices IP core has wide application in VLSI design field[13-15]. For USB2.0 core system, some interference inevitably exists in signal processing. So some fault-tolerant de-sign and test methods must be adopted in order to transmit and receive data correctly[16]. Combining with actual project, this paper introduces in detail fault-tolerant design measures, hardware implement, and test methods about USB2.0 peripheral devices IP core system. These methods can offer the reference for de-velopment of USB2.0 system in all kinds of electronics instrumentations.

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