fault isolation device - seminar · voltage breakdown test under vacuum • chamber maintained...

Fault Isolation Device - Seminar

1

Dr. Michael "Mischa" SteurerFREEDM FID and HILTB Thrust Leader

Technical Chair ESTS 2017Technical Committee Member ICDCM 2017

Associate Editor for the IEEE Journal of Emerging and Selected Topics in Power Electronics - JESTPE

Leader Power Systems Research Group Florida State University - Center for Advanced Power Systems - CAPS

2000 Levy Ave, Tallahassee, FL 32310, USA

2

1 1T Va

Vb

Vc

TfRL

RL

A

B

C

RL

1.4

6 [o

hm

]

TimedFaultLogic

A

B

C

A

B

C

A

B

C15.0 [kV]

#2#1

115[kV]

30.0 [MVA]

1.4

6 [o

hm

]

Ic_L

Ia_L

Ib_L

4

BB1

BB2

A

B

C

A

B

C0.4 [kV]

#2#1

15 [kV]

750 [kVA]

1.4

6 [o

hm

]

I_line

I_line_2

I_line_3

I_line_1

Vb1

Vc1

1.4

6 [o

hm

]

1.4

6 [o

hm

]

Ic_L1

Ia_L1

Ib_L1

A

B

C

A

B

C0.4 [kV]

#2#1

15 [kV]

750 [kVA]

1.4

6 [o

hm

]

Va1

1 1T

I_line_21

I_line_31

I_line_11

3-Phase Fault

0 0.1 0.2 0.3 0.4-2

-1

0

1

2

Time, (sec)

VL, (

pu)

0 0.1 0.2 0.3 0.4-2

-1

0

1

2

Time, (sec)

VL, (

pu)

0 0.1 0.2 0.3 0.4-1

0

1

2

3

Time, (sec)

I gri

d,

(pu)

In conventional distribution systems, a fault does not cause a significant voltage drop in the entire system

Fault Currents in Conventional Systems

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

-1

0

1

Time, (sec)

VL, (

pu

)

1 1T Va

Vb

Vc

TfRL

RL

A

B

C

RL

1.4

6 [o

hm

]

TimedFaultLogic

A

B

C

A

B

C

A

B

C15.0 [kV]

#2#1

115[kV]

30.0 [MVA]

1.4

6 [o

hm

]

Ic_L

Ia_L

Ib_L

4

BB1

BB2

A

B

C

A

B

C0.4 [kV]

#2#1

15 [kV]

750 [kVA]

1.4

6 [o

hm

]

I_line

I_line_2

I_line_3

I_line_1

Vb1

Vc1

1.4

6 [o

hm

]

1.4

6 [o

hm

]

Ic_L1

Ia_L1

Ib_L1

A

B

C

A

B

C0.4 [kV]

#2#1

15 [kV]

750 [kVA]

1.4

6 [o

hm

]

Va1

1 1T

I_line_21

I_line_31

I_line_11

SST

SST

SST

3-Phase Fault

The Fault Isolation Device (FID) has to provide ultra fast isolation of the fault to quickly restore system voltage for continuous operation

FID

FID

Fault Currents in FREEDM Systems

SST DESD activation

Fault

SST DESD activation

In FREEDM systems, the Distributed Energy Storage Device (DESD) of SST provide the power so the customers will not lose the power in case of fault

0 0.1 0.2 0.3 0.4-2

-1

0

1

2

Time, (sec)

VL,

(pu

)

The inherent fault current limitation causes a significant voltage drop in the entire system

0 0.1 0.2 0.3 0.4-2

-1

0

1

2

Time, (sec)

VL, (

pu)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

-1

0

1

Time, (sec)

VL, (

pu

)

Fault

0 0.1 0.2 0.3 0.4

-2

-1

0

1

2

Time, (sec)

Vgri

d;I

gri

d, (p

u)

IgridVgrid

FID Thrust Objectives

• Develop and

demonstrate FID

technology evolution

– Gen-1…Gen-3

• Target: 15 kV class

single-phase switch

– Carry 150Arms (3.2 MVA

@12.5kV, 3-phase)

– Interrupt 200Arms

– Open/close within

<1ms

– >99.99% efficient (total

3 phase losses 300 W)4

5

Gen-1 Solid-State FID

DGI

FID

RSC RSC

PSD (material and device)

Voltage Current

Control

Control

AC

Source

IGBT Module 6.5 kV

Gate Gate Gate

Load

IGBT Module 6.5 kV

5SNA 0400J650100 (IGBT)

TI F28335 DSPIGBTs

KEVAI / V

Sensor

TemperatureSensor(s)

Digital I/O

RSC

||

Fiber OpticARM TS-7800

Buffer Circuit

Power Stage

Onboard Computing Platform

Analog

Gen-I FID Controller and Communication

Analog

IFM Process “Pilot Protection”

IEM Process &Other Services FID

7

Testing Fault Isolation Device (FID)

4.16 kV utility bus

4.16 kV experimental bus

AC voltage

reference

from RTDS

AC current

feedback to

RTDS

„ “

Solid state switch3 x 6.5 kV IGBT modules

Real Time Simulator RTDS

Vsource=2.8 kV peak, Iinterrupted=50 A

Using active di/dt control with IGBTs to reduce magnitude of TRV

0.145 0.15 0.155 0.16 0.165 0.17-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

Voltage across FID

Interrupted current

Vo

ltag

e [

kV

]

0.14 0.145-10.5

0.16 0.170.15 0.155 0.165

-9.0

-7.5

-6.0

-4.5

-3.0

-1.5

0.0

1.5

3.0

4.5

Cu

rren

t [k

A]

-0.2

-0.175

-0.15

-0.125

-0.1

-0.05

-0.025

0.0

0.025

0.05

0.1

Interrupted current

Voltage across FID

Predicted very well by simulation

model

5 MW Converter “Amplifier”

HV Testing – MOV @ 7.2 kV

MOVs at the required 7.2kVrms Steady State Voltage

Notes:No current flowed at this voltage level

Conclusions:The FID was properly operational at required steady state voltage

HV Testing – MOV @ 10 kV

MOVs at 10kVrms Steady State Voltage

Conclusions:Current conduction began at 10kVrms

Power is still lower than the max dissipation spec of 2.5W

10kVrms is the Max Operational Steady State Voltage of the FID

HV Testing – – MOV @ 11 kV

MOVs at 11kVrms Steady State Voltage

Conclusions:Power is has risen above the max dissipation spec of the MOVs (2.5W)

MOVs began heating up

FID cannot be operated at Steady State voltages higher than 10kVrms

3 (and ½) Generations of FIDs

110 5 10 15 20 25 30 35 40 45 50 55

0

2

4

6

8

10

12

14

16

Load Current, (A)

Vo

ltag

e d

rop

, (V

)

534 Watt

736 Watt

317 Watt

134 Watt225 Watt

31 Watt

20 V, 4000 W

200 A

Fully utilized Gen-I Si IGBT baseline

6 x 3.3 V @ 200 A

4 Devices

in parallel

9.2 V

@ 50 A

Reducing on-state

voltage drop eases

commutation for hybrid

switch application

9.2 V , 1800 WOne Gen-II

SiC ETO

One Gen-III SiC

symmetric GTO

4.4 V

@ 50 A

4.4 V , 900 W

0.5 V , 10 WMechanical /Electrical hybrid 0.5 V - 100 W

One Gen-IIa SiC

symmetric GTO

Gen - III

Gate Gate Gate

Gen 3 FID

12

15 kV, 200 A,

SiC p-ETO, bi-

directional

2

200 (400) A, MOSFET

Rds(on) < 1mOhm

Vbr = 100

200A, 15 kV

mechanical

disconnect switch

Open in < 1ms

0.1 V, 20 W

0.1 V, 20 W

Main breaker (MB)

p-ETO p-ETO

DiodeDiode

Fast mechanical

switch (FMS)Auxiliary breaker

(AB)

MOV

Main breaker (MB)

p-ETO p-ETO

DiodeDiode

Fast mechanical


(AB)

MOV

Main breaker (MB)

p-ETO p-ETO

DiodeDiode

Fast mechanical


(AB)

MOV

Main breaker (MB)

p-ETO p-ETO

DiodeDiode

Fast mechanical


(AB)

MOV

Testing the ETO

D

ETOdcV

25mH

SiC PiN

Diode

dcC

pCL

sC

sR200Ω

30nF

sDCH4

Vak

CH1

Ig

CH3

IsnbM2

Iak

~3 us

Voltage

Current

Testing the MOSFET

14

Low loss:100 mV voltage drop at 280 A.

Low temperature rise:33 °C at 200 A rms.

Compact design:5”X 5”X2”, no fan required.

Demonstrating Operating Sequence

15

Voltage across FID

Total FID current

ETO/diode current

FMS current

MOS OFF ETO OFF

1.5 ms opening time

75 V

R1:15 Ω

+ Channel 1 -

Source

Ch2

Ch3

Ch4Main breaker

(MB)

Fast

mechanical


(AB)

MOV

p-ETO

Diode

Alternate

FMS

C-bank &

Thyristor

AB &

MB

5 A

Piezoelectric Actuated Fast Mechanical Disconnect Switch (FMS)

16

• 15 kVRMS, 200 A

• Opening in < 1 ms

• Losses in on-state: < 5 W

US Patent Application No. 15/214,015, filed 7/19/2016

Max Current Simulation

17

• Constrained maximum current simulation: (20K temperature increase)• Steady state: 300 A max• 1 minute transient: 730 A max• 1 second transient: 3050 A max

Project Y8.ET4.1 – FMSHeat run in low vacuum with constant 150 A

• for the 200A test

– Temperature not stabilized

– Still hotspot reaching 90 C

– All other sensors at 70 C

18

0 50 100 150 200 250 300 350 400 45020

25

30

35

40

45

50

55

60

65

70

Tem

pera

ture

(C

)

1

2

3

4

5

6

7

8

9

10

11

12

0 50 100 150 200 250 300 350 400 4500

0.02

0.04

0.06

0.08

0.1

Voltage D

rop (

V)

0 50 100 150 200 250 300 350 400 450-20

-15

-10

-5

0

Pie

zo v

oltage (

V)

Time (min)

Control of Piezo in reverse polarity

FMS Static Testing

Mechanical Compression Test

• Frame statically compressed to

total deflection of 1.2 mm

(expected 1.0 mm)

• Total Force ≈ 110 N• Comparison with COMSOL model

19

Contact Separation Test

• Measurement of physical distance

between contactors

• 150 V applied to piezo

• Total contact separation

4 x 0.4mm

Dynamic Response in Air and DSP Controller Validation

0.25 mm Contact

Separation

11

0.32 mm Contact

Separation

Ramp Speed: 600us

FMS Voltage Breakdown test under vacuum

• Chamber maintained

proper vacuum for 100 hrs,

without getter pump

• Voltage breakdown tested

with 4 x 0.5 mm contact

spacing

– ~22 kV max

– ~15 kV steady state

21

Voltage Withstand Test (1 atm) with Piezo Actuator

• AC Voltage Pulse applied across terminals of FID– RTDS -> Techron Amp -> 1:100 Xfmr -> FID terminals

– 10 Mohm resistor connected to Xfmr secondary terminals

– Xfmr Primary Voltage and Current Measured

– Voltage and Current measured at FID terminals

– Pulse = • 60 Hz, 10 cycles, starting at peak of AC waveform, 10 V/s down ramp, peak

magnitude is varied

Piezo Amplifier

XfmrAmplifier

Xfmr1:100

FID

• Piezo controlled with RTDS

amplified DC signal

– RTDS -> Techron Amp + 15 ohm

resistor -> Piezo

– Voltage measured across Piezo

– Contact separation – 4 x 0.35 mm

Voltage Breakdown Test Results

1.68 kVrms

3.33 kVrms

4.18 kVrms

4.83 kVrms

t [s]

In air, 1 bar

• Repeat in vacuum

• Measure at different gap

distances

• Confirm DC capability (using

voltage grading resistors)

Future Pathways for FID Technology

• Fault current limiter

– For legacy systems with high fault current levels

– Requires higher speed of FMS

• DC applications

– Growing trend towards MVDC

– Requires resistive voltage balancing between contacts in FMS

• Breaker free system architectures

– Fully utilize the fault current breaking capability of the SSTs

– Use FMS alone to isolate fault after complete system de-energization

24

Detect and

localize fault

Re-energize

systemDe-energize

system

Isolate

faulted

segment

M. Sloderbeck, D. Soto, H. Ravindra, M. Steurer, A. Challita, “Megawatt Scale

Demonstration of High Speed Fault Clearing and Power Restoration for MVDC Systems

Utilizing Fast Disconnect Switch”, in Proc. AMTS, Philadelphia, May 25-26, 2016

IEEE Std. C37.302™-2015, “IEEE Guide for Fault Current Limiter

(FCL) Testing of FCLs Rated above 1000 V AC”

Pilot Directional Protection

George G Karady

Qiushi Wang & Zhenmin Tang

Presently used radial distribution system

• The distribution system today is a radial network, which is protected by fuses and fast acting reclosing circuit breakers.

• The circuit breaker is activated by overcurrent protection

• The most fault is produced by lightning which causes a flashover of an insulator. This generates a short circuit

• The fast acting circuit breaker interrupts the current and recloses circuit with about 15-second delay.

• This means that the customer has only a very short outage, which dips the lights and slows down air-conditioners.

• In a distribution system with cables most fault is permanent and recloser is not used

Presently used radial

distribution system

Feeder 4Feeder 1

Feeder 2F

eed

er

3

Three-phase Four-wireMain Feeder

Neu

tral

Re-closing Circuit Breaker

Fuse

Single-phase Radial Feeder

Single-phase Radial Feeder

Sub-transmission Line

To Consumer Service Drop

Distribution (Step-down) Transfomer

The three-phase main feeders are

protected by a reclosing circuit breaker

This switches off the feeder in case of a

fault, and after a few cycles, the breaker

recloses and restores the energy supply.

This is an effective way of protection for

overhead distribution circuits because

most faults on an overhead line are

temporary.

The rest of the system is fuse protected

FREEDM System• In 2008, the National Science Foundation chose NC State to lead an effort to

create a modern power grid.

• At the FREEDM Systems Engineering Research Center, universities from the United States have joined forces with industry partners to develop a more secure, sustainable environmentally friendly electric grid.

• At the FREEDM Center, we’re building the internet of energy: a network of distributed energy resources that intelligently manages power using secure communications and advanced power electronics. Our research priorities include power electronics packaging, controls theory, solid state transformers, fault isolation devices, and power systems simulation and demonstration.

• For students, FREEDM offers research opportunities at five universities: NC State, Florida Agricultural and Mechanical, Florida State, Arizona State and the Missouri University of Science and Technology. On all these campuses, the next generation of energy-focused scientists and engineers can help develop the next-generation electric grid

FREEDM System Vision

• To develop an efficient and revolutionary new

distribution power grid

• Utilizing revolutionary power electronics technologyand information technology

• Integrating distributed and scalable alternative energysources and storage with existing power systems

• Automate the management of load, generation and storage

• Major components are: Solid state Transformer (SST) and Electronic circuit breaker (FID)

Slide is copy from: A.Huang: FREEDM System Vision, Grand challenges and Research Roadmap. Webinar 2010

Slide is copy from: A Huang: FREEDM System Vision, Grand challenges and Research Roadmap. Webinar 2010

• The FREED distribution

system is a loop system

• The loads are supplied by

Solid state Transformers

(SST)

• The loop is divided into

sections

• Each section is protected

by two Electronic circuit

breakers (FID)

Slide is copy from: A. Huang: FREEDM System Vision, Grand challenges and Research Roadmap. Webinar 2010

• The FREEDM distribution system is

built with interconnected loops

• The loop system requires the fast

identification and elimination of

the fault by FID’s.

• FID’s switch of only the section

where the fault occurred

• This calls for a selective differential

type protection

• ASU applied the pilot differential

protection

FREEDM Loop Protection Concept

• The FREEDM system is a loop with several sections, each of them is protected by two fast acting FID devices.

• The loop system requires differential or pilot protection to identify the fault location and only switch off the section with the fault.

• In case of overhead type transmission the reclosing can further improve the system reliability.

Pilot Directional Protection• Pilot Directional protection use Schweitzer

Laboratory produced SEL-351S relays witha wireless communication link.

• Each SEL relay is supplied by a currenttransformer and a voltage transformergenerated signals and configured tomeasure the current direction and thecurrent and voltage amplitude.

• The fault is detected by the sudden voltagereduction and increase of current.

• During the normal operation directionalelement of the SEL relay is in block state.But during faults, it produces F (forward) orR (reverse) signal depending up on thedirection of fault current.

D

D

Relay

An

ten

na

Transmitter

AC

DC

Pilot Directional Protection• The picture shows two of the Wireless Directional Protection system.

• Each relay is connected with the measurement device and at the top of therelay is the wireless communication unit supplied by the DC source.

DC power supplySEL Digital relay

Wireless Communication unit

Description of Pilot Directional Protection

Operation


Fault

D

D

R1

F

FID1

R5

F

R4

F

FID3

R6 F

FID

4

R2 F

R3 F

FID

2

Section 1

Section 2

Se

ction

3

Ac circuit breaker

I1 I2

• Figure shows that a fault in Section 2 produces two currents I1 and I2

• Relays R1,R2,R3 measure forward current and transmit F signal to the adjacent relays

• As an example R2 sends F signal to R1 and R3 only.

• Relays R4,R5,R6 measure revers current and transmit R signal to the adjacent relays.

• As an example R5 sends R signal to R4 and R6


• In Section 1 both relays R1 and R2

measures F signal and also

receive F signal, which prevents

trip signal generation.

• In Section 3 both R5 and R6

measures R signals which also

eliminates FID operation.

• In Section 2 relay R3 measures F and R4 measures R signal, which results

generation of trip signals by both relays.

• The trip signal opens both FID 2 and FID 3, which eliminates the fault, while

the rest of the system remain in operation.

Fault

D

D

R1

F

FID1

R5

F

R4

F

FID3

R6 F

FID

4

R2 F

R3 F

FID

2

Section 1

Section 2

Se

ction

3

Ac circuit breaker

I1 I2


Short circuit occurred Trip signal generatedCircuit breaker operated

• Upper part of the figure

shows three phase sort-

circuit current, which

initiate relay operation.

• The relay typical detects

the short circuit within a

half cycle, less than 8 ms.

• The relay generated DC trip

signal activates the FID

which interrupts the short

circuit current.

• This case a low voltage

magnetic relay was used,

which operated within 2.5

cycles

Demonstration of relay operation and short circuit

current interruption

Verification of Pilot Directional Protection

Operation

Verification of Pilot Directional Protection Operation

FSU-CAPS HIL Testbed

Diagram for ASU Protection

Hardware Testing

Pilot directional protection

The Pilot Directional Protection system was successfully tested in

Florida State University RTD system.


• In this test, the FREEDM loop system is simulated by real-time digital power simulator (RTDS), in the Center for Advanced Power Systems (CAPS) at Florida State University.

• ASU provided two SEL-351S directional protection systems are interfaced with RTDS to physically detect the fault location and send trip signal to FID’s.

• The input of the relays are small ac voltage signals representing secondary currents and voltages at different monitoring locations of the loop system from RTDS

• The output of the relay is connected to a function block called Fault Isolation Device (FID) in RTDS

• Once FID receives trip signal from SEL-351S relay, it will cut off the fault current within the protection zone in RTDS.

• SEL-351 relay builds wireless communication with other relays via SEL-3031 radios system; SEL-3031 radio provides 9MHz mirrored bits wireless connection.


Fault direction Fault direction Fault direction

Relay at FID 3 Forward Forward Reverse

Relay at FID 5 Forward Reverse Forward

Trip signal No trip Trip generated No trip

Trip logic for FID 3 and FID 5


Relay Event Report for FID 3, when the fault occurs between FID3 and FID 5

Back-up Pilot Directional Protection

Back-up protection

• The figure shows the FREEDM loop

with a fault in section FID4-FID5

• All relay measures the current

directions.

• Relays 1,2,3and 4 measures

current forward direction 1

• Relays 5,6 and 7 measures current

reverse direction 2

• The relays can communicate the

measured direction (1 or 2)

wirelessly to each others less than

few milliseconds.


• The relays send trip signal to the FID if in a section one relay measures current direction 1 and the other 2

• This give us the idea that we can use the system for provide back up protection

• Example: trip signal generated in case of fault in the section terminated by FID4 and FID 5 when Relay 4 measures direction 1 and Relay 5 direction 2 or vice-versa

• Simultaneously Relay 3 also measures direction 2 and Relay 6 measures direction 1.

• These signals are sent to each other results trip signals for FID 3 and FID 6

• The sufficient delay of these trip signals provide back up protection when FID 4 and 5 is not tripped.

• ASU programed the relays to perform the described process.

• The logic diagram for the back up protection is in the next slide


Fault location Back up protection Time delay

FID 1 & 2 Relay 3 & 7 5ms






Backup Pilot Directional Protection

This figure demonstrates the operation of the primary and backup protection

• Figure shoes that both

protection sensed the

fault in the same time

(dotted vertical line)

• FID operated around after

2.5 cycle in case of

primary protection

• FID operated after 4.5

cycle in case of Backup

protection

Primary protection

Back-up protection

Integration of Pilot Directional Protection in

the FID Electronic Circuit breaker

Integration of Pilot Directional Protection in the FID

• The presently built protection system use large and expensive digital relays, which can not be integrated into the FID device.

• ASU started the development of a small protection computer that can be incorporated in the FID.

• The work began with the elaboration of an algorithm to measure the current direction.

• The current direction can be measured by calculating the FREEDM loop positive and negative sequence impedances.

• In case of unsymmetrical fault the negative sequence impedance can be used for detection of current direction.

• If the calculated Z2

is smaller than forward threshold impedance, the fault is in forward direction to a relay.

• If the calculated Z2

is greater than reverse threshold impedance, the fault is in reverse direction to a relay.


• The negative sequence impedance is negligible in case of symmetrical three phase fault and the voltage is also close to zero.

• The developed method compares with the present positive sequence impedance with the corresponding positive sequence components a few cycles before.

• The difference in the positive voltage and positive current is used to determine the direction of fault current in the system.

• The current direction is determined by combining both positive sequence and negative sequence component method.

• In the FREEDM loop, each section is protected by two FID’s. Each of them will be equipped by a small computer which determines the current direction and communicates to the other.


• The fault is in the loop when the measurement current directions are opposite.

• In this case, both relays will send a trip signal to the corresponding FID and to isolate the fault

• ASU developed a MATLAB program to perform this operation

• The program is installed on two laptop computers equipped with a data acquisition device

• The system was successfully tested using the ASU’s Analog protection unit

fault isolation device - seminar · voltage breakdown test under vacuum • chamber maintained...

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