Fast Transient Power Converter Using Switched

Current Conversion

Laurence McGarry

Advanced Engineering Technology ManagerHong Kong & China

Astec Power

A Division of Emerson Network Power.

Abstract: Next generation microprocessors continue to require power supplies capable of supporting fast transient loading. Conventional approaches to solving the fast transient issue focus on the use of interleaved buck converters. This approach is fundamentally limited due to the presence of the output inductance, limiting the converter response to a load transient. This paper introduces a novel switched current converter. The converter will switch current to the load or to ground depending on the load transient requirement, providing a theoretically infinite transient response. The research investigates the practical limitations of the converter topology, using simulation to evaluate and optimize the system design. Finally, simulation models and results are presented and suggestions for further design improvements are discussed.

Common Industry Trends

• Intel CPU requirement for VRM

Intel CPU voltage and Current Roadmap

Processor trends well documented :Higher Current RequirementsLower Voltage Processors, tighter regulation rangeHigher FrequenciesFaster Transient Response

Conventional Industry ApproachesStandard approach to resolving the challenge is to use interleaved Buck

converters Response time inherently limited by the presence of the output inductorProblem compounded by interconnect and PCB parasiticsContinued silicon integration, drive to higher frequencies and possibly an

increased number of phases will continue to be a trend regardless of the architecture utilized

Switched Current Techniques offer an alternative approachAn infinite transient response possible, in theory at least

Volterra 300A/uS Module 369mm2

2

Conventional Buck Converter

Switched Current ConceptsCurrents are switched to the load or to the return pathParallel switching Current Paths are utilizedTransient can be supported in the time that it takes to turn the FET On/OffWhen output current follows processor demand current, significant

reduction in output capacitance can be observedThe constant current source is derived from a Buck Converter driving a

matrix Transformer configuration

2

Constant Current Source Front end Buck converter provides the constant current source Push Pull Converter operating at 100% duty using a ‘Matrix transformer’

provides the input to the current switches at the load sideMatrix Transformer: series (primary), parallel (secondary) ferrite cells

forming individual isolation for each phase

2

LHS source is constant current and could be remote from the end application.

RHS Switches could be co-located with the processor to reduce interconnect parasitics and enhance transient response

System Overview and Simulation ModelFront End Buck Converter providing constant current sourcePush-Pull Converter with Matrix Transformer provides constant current

parallel pathsOutput Current switches; switching current to the load in response to

transients or to groundSimulation model: 3 Stage Conversion

-12V input to 1V, 100A output- 10 parallel switching paths

Constant Current Source Buck ConverterBuck Constant Current ConverterSimple Hysteretic Control Implemented

No Output Capacitance2 level Threshold Control 10A-11ASynch Rectification is used to reduce power lossSwitching Frequency Varies according to the Buck Output voltage, reaching maximum while Voutput Buck=0.5VinVoltage on the output of the Buck is n X Vo

- Where n is the number of switches turned to the load

Vref Low

+5Vcc10kR2

U18max961

GND

NQ

Q

LE

IN+

SHDN

IN-

Vcc

X1

MAX473

3.3k

R13

10k

R8

1KR14

10mR15

Ireturn

DRV1s

U19max961

GND

NQ

Q

LE

IN+

SHDN

IN-

Vcc10kR1

+5Vcc

Vref H igh

Q4

irf 7822

Q3irf 7822

U17HC74D

QN

Q D

RST

SET

L2

5.6u IC=10.5

12V15

E3

1

E4

1

Iout

Constant Current Source Buck Converter(cont)Simulation Results light load

Simulation Results Light load• Buck output voltage=0.5V• Output current =10.87A• Switching Duty cycle=5.55%• Switching Frequency=110kHz• Current ripple =694mA

Simulation Results Full load

Simulation Results Full load• Buck output voltage=11V• Output current =10.69A• Switching Duty cycle=93%• Switching Frequency=133kHz• Current ripple =760mA

Constant Current Source Buck Converter(cont)

0 5 100

2 .10 5

4 .10 5

6 .10 5

fs Vo( )

Vo

fs vs Vo CurveL=5.6uH, ∆I=1A

Simulation Results Dynamic load• Output voltage slew rate=46V/us• Output current =10.8A• Current ripple =828mA

Input Buck Frequency Variation• The highest frequency =518kHz

(output voltage =5.5V)• All components are ideal

Simulation result on dynamic load

Push Pull ConverterB ranch 1

L5

2n

L4

2n

L3

2n

Q2irf6603

TX1 Q1irf6603L2

2n

10.5I1

Q4

irf540ns

D3IDEA L

4.7nC3

2kR7

2kR1

4.7nC1

D1IDEA L

Q3

irf540ns

Fixed Duty Cycle of 50%Leakage Inductance causes

increased voltage stress on Primary FETs

Gate Drive Timing for Primary FETs and secondary Synchronous Rectification FETs is critical

Push Pull Converter – Matrix TransformerMatrix Transformer Structure:

Core Size 11.8 X 6 X 4 mm

Coupling Coefficients: Pri-Sec 0.996, Pri-Pri 0.994, Sec-Sec 0.994

Important for the Matrix Transformer cells and SRs to be in close proximityStaggered placement of the Matrix Cells on either side of the PCB

facilitates optimum layout

Matrix Transformer Modeling

Standalone With Primary TerminationIn The Middle 0.5mm 4.5mm

Magnetising Inductance 2.07uH 2.07uHLeakage S-P 2.72nH 3.27nH 8.04nHLeakage S-S 7.11nH 7.79nHLeakage P-P 10.94nH 11.61nHEquivalent R 1.38mOhm 1.41mOhm 2.08mOhm

Primary R 0.476mOhmSecondary R 0.934mOhmMagnetising Current 1.063ACore Loss 0.375W

Push Pull Converter – Drive Signal TimingPrimary Gate Drive Overlapping

First, overlapping drive is considered to avoid breaking current source path

Two primary windings are shorted during the period of overlapping and a current gap occurs

Spike across the drain source is caused by the energy stored in leakage inductor

G1G2

Primary Gate Drive Non-OverlappingNon-overlapping avoids shorting the

primary windingSpike on drain is caused by the current

transientCurrent gap occurs during this period as

the two primary FETs are off

Non-overlapping gate drive is used. Adjusting dead time optimizes the current gapDevice capacitance is sufficient to provide current continuity during commutation

Push Pull Converter – Drive Signal Timing (cont)Reverse Recovery of Synch Rect. for non-overlapping

Simulation waveform under 100mOhm Load. 100nS primarydeadtime, 150nS leading SR delay. 60nS SR trailing edge delay.

Note reverse recover current during SR off time

The spike due to reverse recover current depends on the parasitic inductance of trace on PCB

Switched Current Converter

Vo

4.7uC1

1m

I1

Vref1

VccU1

max962

VSnGnd

VSpQout_pQout_n

VINpVINn

D2IDEAL

10 R3

ARB1

N1OUT ARB2

N1OUTQ2

irf6601_1

D3IDEAL

10 R2

Q1irf6601_1

Output Capacitance is necessary but smallerVoltage feedback Current supplied to the load is determined by voltage drop on the capacitor Delay of control loop requires a larger capacitance ESR and ESL of Output Capacitance is critical to the step controlGate drive timing stops current to load before short current to ground

Switched Current Converter(cont)Simulation on dynamic load = 400A/us

Simulation condition:Load current is changed from 5A to 95A (blue)Load current slew rate = 400A/us

Simulation result:Load voltage is varied from 1.022V to 0.975V (light green)

The red line Ic is the current waveform before output capacitanceThe light green line is the buck output current waveform

Switched Current Converter(cont)Simulation on dynamic load = 1000A/us

Simulation condition:Load current is changed from 5A to 95A (blue)Load current slew rate = 1000A/us

Simulation result:Load voltage is varied from 1.022V to 0.975V (light green)

Switched Current Converter(cont)Simulation on dynamic load = 2000A/us

Simulation condition:Load current is changed from 5A to 95A (blue)Load current slew rate = 2000A/us

Simulation result:Load voltage is varied from 1.022V to 0.975V (light green)

The Slew Rate has no obvious effect on the Output Voltage Deviation

Switched Current Converter(cont)Modeling The Interconnect:

All the previous simulations include the parasitics associated with the a representative system interconnectThe simulations do not include PCB parasitics and depend on component simulation accuracy

decouplingcapacitors

output cap

560uC5

300uR6

FutureProcessorModelcurrent output

40u

R5L1

100p

300uR3

180uC1

VRM

VRM

inter-connection

System Measurements – Actual results

Load changed from 0-50%, 5 phases switchingEarly results indicate that the 927A/uS can be achieved on rise timeOptimisation continues…..

System Power Budgetfull load 100A 1V light load 10A 1V

item components power losses(W) power losses(W)output choke EE18 0.281 0.281Mosfet High side IRF7822 2.463 1.693Mosfet low side IRF7822 0.127 0.744sense Resistance 0.01OHM 1 1Driver IC ISL6605 0.04 0.04total power losses 3.911 3.758

output power 114.754 23.154Efficiency 96.70% 86.04%

RCD 2.5 0.9transformer Martrix 5.3 5.3PP Mosfet STP75NF75 1.804 1.804SYN Mosfet IRF6618 2.81 2.81Switch current Mosfe IRF6618 2.34 2.34total power losses 14.754 13.154

power loss 18.665 16.912load power 100 10total input power 118.665 26.912Efficiency 84.27% 37.16%

Total

Buck Converter

Push Pull andSwitch Current

System Power Budget indicates that the overall efficiency ~ 84%~2-3% Lower than a conventional VRM due to the 3-Stage Topology

System Assembly6 layer PCB 75mm X 25 mmAssembly height 13.6mmMatrix transformer divided between the top and bottom sidesRectifier FETs close to Matrix Transformer

Summary and Conclusions:This paper introduces the concepts of switched current conversion as a

possible alternative to common industry approaches to Fast transient requirements

The converter consists of 3 Stages: Buck Current source, Push Pull converter employing a matrix transformer and the switched current output

Simulation results indicate that the topology can meet very fast transient requirements limited only by parasitics and sensing delays

Reduces overall system capacitance Transient response could be further enhanced by moving the switched

current section to the load applicationSilicon integration to reduce complexity and component countAdvent of flexible Digital control systems to reduce the number of phases,

reduce complexity and improve efficiency

Reference Material1) Edward Herbert, “ Switched-current Power Converter”, 2003

2) Edward Herbert, “ Voltage Control for Switched-current Power Converter”,

3) Edward Herbert, “ Fast Transition Power Control for Processors Using Switched Current and Switched Charge ”

4) Edward Herbert, “ Input Characteristics and Waveforms for Switched-Current Power Converters”