fan-out and embedded die: technologies & market trends 2015 report by yole developpement
TRANSCRIPT
February © 2015
From Technologies
to Market
Fan-Out and Embedded Die: Technologies & Market Trends
Sample
2
REPORT OUTLINES
• Report scope & definitions • Embedded Die in substrates
o Scope of the report o Motivations and drivers
o Companies cited in this report o Products and technologies
o Glossary • Products available
• Executive summary • Roadmaps
• Advanced packaging growth o Supply chain
• Fan-Out platform • Players and positioning within the supply chain
o Motivations and drivers o Embedded Die Package commercialization status
o Products and technologies o Market forecasts
• Products available o Equipment & materials
• Roadmaps • Challenges related to yield & supply chain
o Supply chain for FOWLP • Cost considerations
• Players and positioning within the supply chain • Conclusions & perspectives
o FOWLP commercialization status • Company presentation
o Market forecasts
o Equipment & materials
• Improvement of materials
• Panel for FOWLP status
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
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REPORT SCOPE
The main objectives of this report are the following:
o To update the business status of both embedded wafer level package technologies (FOWLP and Embedded DiePackage) markets
o To provide a market forecast for the coming years, and estimate future trends
o To analyze key market drivers, benefits and challenges of embedded wafer level packages by application
o To describe the different existing technologies, their trends and the roadmaps
The FOWLP and Embedded Die Package markets are studied from the following angles
o State-of-the-art technology and trends
o End-user applications and drivers
o Market value
o Industrial supply chain & value chain
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
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THE EVOLUTION OF SEMICONDUCTOR PACKAGING
A bridging technology between ICs and PCBs
Packaging fillsthe gap in between ICsand PCBsimprovementspeeds
Feature sizes CMOS
transistors: 28nm
Feature sizes of PCBs
1970
Through
hole
technology
1980
Surface mount
devices
Deve
lopm
ent
in C
MO
S pro
cess
ing
capab
ilities
Deve
lopm
ent
in P
CB
pro
cess
ing
capab
ilities
1990
CSPs/BGAs
SiPs
2000
WLCSP
more SiPs
Flip Chip BGA
PoP
2010
3DIC
TSV
Fan-out WLCSP
Cu pillars
Silicon interposers
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
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PACKAGING ADDEDVALUE:
More Moore and More than Moore
3D approachallows to getall the benefitfrom chip miniaturizationand package integration
More Moore : miniaturization
130nm 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Anal
og
+
RF
Pas
sive
sPow
er
Senso
rsEnerg
y
Sourc
es
Bio
chip
s
More
Than
Moore
: div
ers
ific
atio
n
SoC
SiP
IPD
RF CMOS
SMOS
Analog
Power
Low Power
CMOS
High Perf.
SOI
Non
Volatile
Memory
GaAS RF
MEMS
…
3D integration is seen today as a
new paradigm for the future of the
semiconductor industry, as it will
enable several more decades of
chip evolution at ever lower cost,
higher performance and smaller-
size features.
…
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
6
WAFER-LEVEL-PACKAGING MARKET DRIVERS
WLP
•Lower packaging cost
•Lower test cost
I/Os density
•Lower pitches
•No standard
•Smaller dies
•Higher density of I/Os
Integration
• IPD
•SiP
•3D
Thermal performance•Lower power consumption
•Higher package density
Electrical performance
•Smaller Interconnect lines
•Higher frequencies
•Higher ackage speed
•Lower parasitics
Form-factor
•Smaller thickness
•Lower footprint
• Improve chip-to-board coupling
• New materials
• Batch processing
• Panel capability
• Lower thickness
• Multiple RDL
• Interconnect optimization
• Smallest thickness of the market
• Integration capability
• Low pitch capability
Cost
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
Numerousmarketdrivers lead to a WLP solution
7
TWO TYPES OF EMBEDDED WAFER-LEVEL-PACKAGES
• A different approach depending onsubstrate type:
• FOWLP is based on areconfigured molded waferinfrastructure
• Embedded die in package isbased on a PCB type of panelinfrastructure
There are two main substratetypes for embeddingtechnologies
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
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FAN-OUT WLP PRINCIPLE
Embeddingin a moldingcompound allow thinpackaging
Pick and place
Wafer level
Molding
Carrier removal / de-bonding
Tape lamination
Standard WLB process
(Passivation, pattern, RDL,
bonding)
Dicing
Source: Infineon
Carrier (Metal)
Carrier with foil and chips
Molding with liquid moldcompound
WLP Fan-Out wafer
After singulation
Reconstituted wafer
after molding
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
9
FAN-OUT WLP KEY DIFFERENTIATORS
Numerousadvantagesposition FOWLP as a promisingsolution
Simplified supply chain and
manufacturing
infrastructureNo restriction in
bump pitch
No laminate
substrate
required
Shorter
interconnections
Fan-out zone
adaptable to
customer needs
High degree of
package design
freedom
Reliable, miniaturized high
performance package
Smaller footprint and thinner
package than Flip-Chip BGA
Better board level
reliability compared to
WL-CSP
RoHS and REACH
compliant package
Excellent electrical
performance
Lower thermal
resistance compared to
Flip-Chip BGA
Mold Chip
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
10
FAN-OUT WLP DRIVERS:WHERE IS THE THRESHOLD?
• A lot of products are already packaged using Fan-in solution which is cheaper than Fan-Out
• With die size reduction and higher pins count manufacturers will have two options:
• Reducing ball pitch in order to have more connections within the die surface
• Going Fan-Out and allowing an easier redistribution
• Since pitch reduction is very challenging, Fan-Out approach is offering a good opportunity
FOWLP has a sweet spot area whereFan-In cannot fit
Die
siz
e (
mm
/sid
e)
P i n s - c o u n t
Fan-out
Fan-in
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
11
FAN-OUT POTENTIAL APPLICATIONS
Opportunities for FOWLP in mobile phones
FOWLP has the potentialto fit in manyapplications
Orange: Devices that can be found in
FOWLP packages today
Discrete passives
Green: Devices that could be found
in the future in FOWLP
Grey: Devices that will likely remain
on WLCSP or flip-chip package or
move to 3DIC
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
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FOWLP ACTIVITIES: GLOBAL MAP OF MAIN PLAYERS
FOWLP catches the interest of manycompanies
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
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FAN-OUT WLP: TECHNICAL CHALLENGES
FOWLP technicalchallenges to overcome
IC 1IC 2Mold
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
Chip-to-mold non-
planarity
Die shiftReliability
Warpage
Topography
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TECHNOLOGY ROADMAP FOR FOWLP
Key parameters
Roadmap of FOWLP
follows the high
demandingexpectations
from the market
2013 2014 2015 2016
Line/Space
Package minimum
thickness (with BGA)
Max level of RDL
Minimum die-to-die
distance
Minimum die side size
Minimum mold
clearance distance
Minimum bump pitch
Maximum package
size
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
15
FOWLP ACTIVITY MARKET FORECAST
A high growth isexpected
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
CAGR ~ 10%
Transition phase
Ramp-up with fab-less wireless
IC players and wide FOWLP
infrastructure/supply-chain
$0M
$300M
$600M
$900M
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
FO
-WL
P r
even
ues
(M $
)
FOWLP activity revenues (M$)Overall evolution since eWLB technology introduction
Yole Developpement ©
16
EMBEDDED DIE PACKAGING PROCESS FLOW
Example with “chip-first – face-up” approach
Principle of embeddeddie package in substrate
1) Die Bonding
2) Lamination
3) Laser drilling
Adhesive on
copper foil
Pick & place on
copper foil
Relamination
process
Copper plating, imaging and etching
3) Structuring
Source:AT&S
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
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EMBEDDED DIE PACKAGE KEY DIFFERENTIATORS
Embedded Die package advantages
Good for copy protection
New suppliers Low manufacturing
cots thanks to very
mature products
High potential for
reducing I/Os thanks to
design (wire-bond layout)
High potential for
components
integration
Small footprint thanks to
more space given to surface
components
High mechanical reliability
Improved thermal
performance thanks to
proximity with active
High design flexibility since
chip can be positioned
wherever we want
Reduced parasitics
thanks to short
interconnections
Chip
Laminated PCB
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
18
EMBEDDED DIE PACKAGING
Technical challenges
Embedded Die Package technicalchallenges to overcome
Embedded SiP
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
Warpage
Yield
Die positionning
Resolution
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EMBEDDED DIE PACKAGING: A NEW SUPPLY CHAIN
• Supply chain and responsibilities can be defined case by case upon players will of implication
• Embedded die packaging
opens the door for
substrate suppliers to
realize the whole packaging,
assembly and test
themselves Good
opportunity for substrate
suppliers to create new
business and potential
threat for OSATs market
PCB manufacturers can create a new supply chain in semiconductor industry
Wafer thinningEmbedded Die
Customization
Wafer sort / Die
preparation
PCB Core
Fabrication
Component
placementMulti-layer build up
fabrication
Embedded Die PCB
sort
Solder paste
Component
placement and
reflow
Product level
assembly and
test
1) Die Customization (IDM or Wafer Level Technology Provider)
2)Embedded Die Substrate Fabrication (PCB manufacturer)
3) Product level assembly and final testing
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
20
TECHNOLOGY ROADMAP FOR EMBEDDED DIE
Key parameters
• Today, Embedded Die Packaging technology only targets low-cost, low I/O pin-count applications (mainly power and analog ICs)
• However, to enter the digital space and more complex SiPmodule realization, embedded die technologies are set to evolve
Roadmap of Embedded Die package shows the targets to achievebefore beingfullycompetitivein mobile market
2013 2014 2015 2016
Line/Space
Package minimum
thickness
Chip layer stacking
Pad Pitch on die
Chip thickness
(min-max)
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
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EMBEDDED DIE ACTIVITY MARKET FORECAST
Embedded Die package market isstill a niche
$0M
$100M
$200M
$300M
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Embedded die package revenues forecast (M$)Overall evolution since technology introduction
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends
23©2015 | www.yole.fr | Name of the report
MEMS &
Sensors
LED/OLED
Compound
Semi.
Imaging Photonics
MedTech
Manufacturing
Advanced
PackagingPV
Power
Electronics
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Korea
40% of our business is in
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Email: [email protected]
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