false path

LEC-22 Preliminaries 1

LEC-22: Critical Paths and FalsePaths

University of Waterloo

Dept of Electrical and Computer Engineering

E&CE 427 Digital Systems Engineering2004t3–Fall


Schedule

wk-01 – 02 VHDLwk-03 – 04 RTL Design Techniqueswk-05 – 06 Functional Verificationwk-06 – 07 Performance Analysis and Optimizationwk-08 – 09 Timing Analysis

lec-21 Timing analysis for storagelec-22 Critical pathslec-23 Elmore timing model

wk-09 Power Analysis and Reductionwk-10 – 11 Faults and Testingwk-11 – 12 Reliability and Fault Tolerancewk-13 Review

Today Find the path through the circuit that limits the clock speed. Distinguishbetween real critical paths and false critical paths.


Announcements

� Midterm marking

� Vol II of Course Notes available

LEC-22: 5.4.1 Critical Paths (Page 243) 4

5.4 Critical Paths and False Paths

Definition critical path: The slowest path on the chip between flops orflops and pins. The critical path limits the maximum clock speed.

5.4.1 Critical Paths

LEC-22: 5.4.1 Critical Paths (43) 5

Example: Full Adder

Find the critical path through the full-adder circuit shown below.

gate delayNOT 2AND 4OR 4XOR 6

ci a b

co

s


Karnaugh Maps

Test another set of input values along the same path.

The “427” way of writing Karnaugh maps and the “old-fashioned” way of writingKarnaugh maps:

a b

ci

ab

ci10 11 01 00

1

0

Karnaugh map showing transition that exercised critical path:

a b

ci 1 1 1 0

1 000

a b ci10


Alternative Excitation

Karnaugh map showing a possible alternative excitation of critical path:a b

ci 1 1 1 0

1 000

a b ci1 0

Test if alternative input exercises the critical path.ci a b

co

s


Outline of Algorithm to Find Critical Path1. Start at source node and traverse through fanout to destination node, annotating

intermediate nodes with maximum delay to the intermediate nodes.

2. The delay to the destination node is the delay of the critical path.

3. The critical path is found by starting at the destination path and working back-wards, choosing node with maximum delay at each step.

LEC-22: 5.5 False Paths (Page 243) 9

5.5 False Paths

Sometimes the path that appears to be the critical path is actually a false path.

ya

b

c

ya

b

c

ya

b

c

LEC-22: 5.5 FALSE PATHS (Page 243) 10

False Path Trickery

Sometimes a path that appears to be a false path is actually the critical path.

ya

b

ya

b

ya

b

LEC-22: 5.5 False Paths (Page 243) 11

Revised Algorithm to Find Critical Path1. Find candidate critical path using previous algorithm

2. Test if candidate path is really the critical path

3. If candidate is not critical, then update delay information and return to step 1.

4. If candidate is critical, then done.

Lec-22: 5.5.1.1 (pp 246) Preliminaries 12

5.5.1 Testing a Critical Path

5.5.1.1 Preliminaries

Definitions delay data disclosure....


Controlling ValueThe controlling value of a gate is the value such that if one of the inputs has thisvalue, the output can be determined independent of the other inputs.

For an AND gate, the controlling value is ’0’, because when one of the inputs isa ’0’, we know that the output will be ’0’ regardless of the values of the otherinputs.

The controlled output value of a gate is the value produced by the controlling inputvalue.

Gate Controlling Value Controlled Output

AND

OR

NAND

NOR

XOR


Reconvergent Fanout

Most of the difficulties with critical paths and testing circuits are caused by recon-vergent fanout.

The wires that fanout from a gate reconverge at another gate.

ya

b

c

z


Critical Input, Side Input

For a gate on a path (either a candidate critical path, or a real critical path), thecritical input is the input signal that is on the path.

For a gate on a path (either a candidate critical path, or a real critical path), the sideinputs are the input signals that are not on the path.


5.5.1.2 Algorithm to Determine if a Path isthe Critical Path

To determine if a path through a circuit is a false path:

1. Start at the destination node of path, try to push a 1 � 0 or 0 � 1 backwardsalong the candidate critical path. Hint, pick the edge whose final value is thecontrolled output of the gate.

2. Follow the critical path backwards through each gate.� For the critical input, assign the value needed to produce the current value on

the output (figure??).

� For the side inputs, assign non-controlling values or edges that end in non-controlling values.

3. If different values are assigned to the same signal, then try to push anotheredge or glitch backwards through the circuit.

4. If have tried both rising and falling edges and both low and high glitches, and allfour options have produced contradictory assignments, then the candidate pathis a false path.


Ending Conditions for Algorithm� To be precise: a candidate path is a false path iff, for every vector of input values

to the circuit, there is a gate along the path such that a side input with a controllingvalue has a shorter path to the inputs.

� If don’t assign different values to same signal, then assignments calculated alongpath give values that will exercise critical path.

� Push values on non-critical nodes to primary inputs to give assignment that willexercise the critical path.


Rules for Pushing Edges and Glitches

1 1

0 0

1 1

0 0


Missing Rules?

Question: Why do the rules not have falling edges for AND gates or risingedge for OR gates?


Real Example of False Paths

Find the longest path in the circuit below and determine if the longest path is thecritical path.

a

b

c

z

y

b

c

de

f

g

h

i

LEC-22: 5.5.2 Finding the Next Candidate Path (Page 251) 21

5.5.2 Finding the Next Candidate Path

To find the next candidate critical path, recompute delay values along the false path.Leave all other delays the same as before.

For each node along the false path, maintain two delay values. One delay is thevalue already calculated. The other delay value is the maximum delay to that node,ignoring the prefix of false path. The prefix of a false path is the set of nodes whosefanin comes only from false paths.

As a shortcut, you do not need to maintain two delay values for nodes in the suffixof the false path. The suffix is the set of nodes who fanout only to the false path.The nodes in the suffix do not need to maintain their old delay value. They onlyneed their new delay value.

LEC-22: 5.5.2 Finding the Next Candidate Path (Page 251) 22

a

b

c

z

y16

2 4 40

0 22

2 28

1212

8 8 10

a

b

c

z

y16

2 4 40

0 22

2 28

1212

8 8 10

LEC-22: 5.5.3 More False Path Examples (Page 251) 23

5.5.3 More False Path Examples

Ex: Need to Test Both Rising and Falling

Edges

ac

bed

f

ac

bed

f


Ex: Need to Test Glitches

ac

b

e

d

f

ac

b

e

d

f

ac

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d

f


Ex: A Simple False Path

a

a

a


Ex: Xors in Example

Question: Find the false critical path in the circuit below.

a b c

d e

f

gh

ik

j

LEC-22: 5.5.4 High-Level Analysis of False Paths (Page 254) 27

5.5.4 High-Level Analysis of False PathsSometimes the delay through a component is dependent upon the values on sig-nals. This is because different paths in the circuit have different delays and someinput values will prevent some paths from being exercised. Here are two simpleexamples:

� In a ripple-carry adder, if a carry out of the MSB is generated from the leastsignificant bit, then it will take longer for the output to stabilize than if no carriesgenerated at all.

� In a state machine using a one-hot state encoding, false paths might exist whenmore than one state bit is a ’1’.

Because of these effects, static timing analysis might be overly conservative andpredict a delay that is greater than you will experience in practice. The most ac-curate delay analysis requires looking at the actual data values that will occur inpractice.

Conversely, a timing simulation may not demonstrate the actual slowest behaviourof your circuit: if you don’t ever generate a carry from LSB to MSB, then you’ll neverexercise the critical path in your adder.

false path

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