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Failure mechanisms in MOS

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LOUGHBOROUGH UNIVERSITY OF TECHNOLOGY

LIBRARY

AUTHOR/FILING TITLE

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F AlLURE MECHANISMS

IN

MOS DEVICES

EKANA Y AKE AJITH AMERASEKERA BSc.(Hons), DIS.

A Doctoral Thesis

Subrmtted in partial fulfillment of the requirements for the award of Doctor of Philosophy of the Loughborough Umversity of Technology.

8th August 1986

Research Supervzsor: Professor D.S. Camp bell

© by E.A. AMERASEKERA 1986

:- o ,:t6G-8'7o1.-•

One must have a meditative quality of the mznd, not

occaszonally, but all day long And this something that !S

sacred, affects our lives not only dunng waking hours but

dunng sleep.

J. KRISHNAMURTI

Truth and Actuality

ABSTRACT

Continuous and pulsed voltage stressmg of metal oxide semiconductor (MOS)

transistors and capacitors has been mvestigated. The expenmental work followed a

survey of failure mechanisms in semiconductor devices which Identified Electrical

Overstress Damage (EOS)/Electrostatic Discharge (ESD) damage as the most

frequent cause of failure, accounting for over 50% of all damage observed. The

survey itself, covered all aspects of semiconductor reliability including reliability

modelling and quality assurance.

A qualitative model of oxide breakdown in MOS structures was developed as a

result of the experimental work. Two different mechanisms have been proposed for

continuous and pulsed voltage breakdown.

Continuous voltage breakdown simulating EOS conditions, was temperature and

voltage dependent. The long time-scales involved, lead to a model whereby

breakdown IS the result of conduction of charge earners through the oxide, via

electron traps and impunty Sites with energies m the forbidden gap. Pulsed voltage

breakdown simulating ESD, was voltage dependent but not temperature dependent.

The very short time-scales involved indicate that breakdown is the direct result of

electron transport m the oxide conduction band. Electrons are inJected into the

conduction band via quantum-mecharucal tunnelling from the cathode.

Both mechanisms were found to be dependent on the surface charge concentratiOn

of the Silicon and, therefore, polanty dependent. The models explain this effect by

analysing the charge injection process under high electric fields.

ACKNOWLEDGEMENTS

During the course of any research studentship there are many people who would have

helped in some manner, towards the fmal success of the thesis. I wish to thank all my

friends for their encouragement and support (usually over the glass of an intoxicating

liquid) during the numerous dark (and bright) days encountered over the last three

years.

I owe my thanks to colleagues m the Electronic Component Technology Group and in

the Physics Department at Loughborough Umverslty for the many rewardmg

dJ.scuss10ns I have had with them. In particular I would hke to express my gratitude to

my supervisor Professor David Camp bell, for his willingness to discuss this research

and provide advice, as well as for his tremendous moral support during the course of

my studentship. Dr. Vaughan Williams, who has since departed to conduct research

in the warm Cambean, gave me much assistance and encouragement during the early

days of my studentship. I am indebted to Roger Tomlinson for his electromc Wizardry

in producmg some of the more complex circuits needed for the expenments. My

thanks to Andy Frankhn for h1s help w1th the preparanon of this manuscript, the

coffee and the goss1p. To Jeff Jones for providing the computation for working out

the numencal values of the integrals used in the course of this work, and to Sana, Ian,

Danny, Ratne and Joe for being there.

Plessey Research (Caswell) Ltd. prov1ded the wafers used in th1s study and my thanks

to them, particularly Nick Annstrong, Ray Oakley, Bill Holt and John Cutter for the1r

help. The work has been carried with the support of the Procurement Executive,

Mimstry of Defence, and I am grateful to them for the opportunity. Abstracts of the

three reports associated with this contract are presented in Appendix 3.

I would like to thank Ramani for helping me out with the typing when most needed.

Thanks also to Chnstine for her help in preparing the papers and manuscripts

associated with this project, to Yasmm for her typing, and to Eileen for some of the

diagrams. I am indebted to Dileepa for his unselfish assistance in putting together the

final version of this thesis.

A special 'thank you' to Anoma for her help with this work and for being such a

special person.

These acknowledgements would be incomplete if I did not express my eternal

gratitude and love to my mother, Aloma, and my sister, Rosharni, for their continued

affection and lovmg support, across the rmles, over the past seven years. I dedicate

this work to the two of them.

A

As

B

c

cm

CMOS

Cox

c.

Csp

CT

c-v

•c

D

NOMENCLATURE AND SYMBOLS

- Amperes

- Arsenic

- Boron

- Capacitance

- centimeter

- Complementary Metal-Oxide-SemLconductor

- Capacitance of gate oxide

Total Capacitance across an MOS capacitor

Capacitance of MOS space-charge region

- Curve Tracer

- Capacitance -Voltage

- degrees Celsius

- Transmission Coefficient

D.C.jd.c. - direct current

D-mode/ type - Depletion - mode/type

e

E

Ea

EFi

EFn

EFp

EG

Ei ( 1<)

- Diffusion Constant for Electrons

-Diffusion Constant for Holes.

- Device Under Tests

- electronic charge (1.6 x 10- 1~ Coulombs)

- Energy

- Activat1on Energy

- Intrinsic Fermi level

- electron quasi-Fermi level

- hole quasi-Ferml level

- bandgap energy

- Ionization Energy

EOS - Electrical Overstress

ESD -Electrostatic Discharge

E - mode/type - Enhancement-mode/type

eV - electron volts

FET - Field Effect Transistor

FIT Failures-in-Time (1 failure in 109 device hours)

G - Generation rate

GaAs -Gallium Arsenide

gds(sat) - drain-source conductance (saturated)

gm - mutual transconductance

HTRB - high temperature reverse bias

hrs - hours

Hz - Hertz (cycles per second)

I - current

Io(sat) - dratn current (saturated)

Ios - drain-source current

IG leak - gate leakage current

IGFET - Insulated Gate FET

I-V - current - voltage

j p J - current density

Jn - electron current density

Jp -hole current density

k

K

k

L

Lo

LSI

m

m*

mh

MESFET

MOS

rmn

ms

MTBF

MV

MO

n

n•

nF

nm

NMOS

- Boltzmann's constant (1.38 x lo-23 J/K)

- Kelvin

- kil a-ohm ( 103 Q)

- length

- Debye length

-Large Scale Integration

- mass

- effective mass

- electron mass

- hole mass

- metal-semiconductor FET

- metal-oxide-semiconductor

- mill imeter

- millisecond

- Mean Time Between Fatlures

- Megavolt

- Mega Ohm (lo6 g)

- electron-doped

- excessively electron-doped

- nanofarad

- acceptor doping concentration

- donor doping concentration

- nanometer

- n-channel MOS

- electron concentration 1n bulk of p-type material

ns

0

p

p

p•

pF

PMOS

polyS i

Ppo

ps

Px

Q

Os

Oss

Oeff

OA

q

s

s

- nanosecond

- supply function

- Oxygen

- Phosphon.1s

- hole-doped

- excessively hole-doped

- pico Farad

- p-channel MOS

- polys il icon

- hole concentratton in bulk of p-type material

- picosecond

- momentum in x direction

- Coulombic charge density per unit area

- surface charge density per unit area

- interface states charge denstty per unit area

effective char~e denstty per unit area

- quality assurance

-electron/hole charge (1.6 x lo-19 Coulombs)

- Recombination rate~ ResLstance

- Gate-drain reststance

- Gate-source resistance

- seconds

- Siemens

secs.

T

t

trise

tdecay

TTFF

V

Vappl

Vc

V os

V os eff

VG

VLSI

VSD

V sub

vT

- seconds

-silicon

-silicon dioxide

- temperature

- time

- rise time

- decay time

- Time To First Failure

- volts

- applied voltage

- capacttor voltage

- drain source voltage

- effective dratn source voltage

- gate voltage

- very large scale integratton

-very small dimension

- substrate voltage

- threshold voltage

'il - width

A - Angstrom (lo-8cm)

~(F) - Ionizatton coefficient

B = qjkT : 39 v-1

B8 - Shottky coefficient

BpF - Poole-Frenkel coefficient

E • 1

X

ft

~ms

l'n

l'h

b

p

lT

Tmin

p (x)

'fls

- change in voltage

- change in time

- change in current

- permittivity of free space (8.854 x lo-14 F cm-')

- permittivity of insulator

- permitttvity of silicon (1.04 x lo-12 F cm-')

- electron affinity

- h/2lT, adjusted Plank's constant (1.055 x lo-34 Js)

- Fermi potential

- metal-semiconductor work function

- mobility

- electron mobility

- hole mobility

- mtcroseconds (lo-6 s)

- base failure rate

- Failure rate

- 3.1411<.

- minority carrter response time

- majority carrier response time

- charge density

- Band-bending at surface.

CONTENTS

ABSTRACT

ACKNOWLEDGEMENTS

NOMENCLATURE AND SYMBOLS

1. INTRODUCTION

1.1. Historical background 1.2. The present and the future 1.3. Failure mechanisms in semiconductor devices 1.4. Chapter synopses 1.5. References

2. SURVEY ON FAILURE MECHANISMS IN SEMICONDUCTOR DEVICES

2.1. Introduction 2.2. Event-related failures 2.3. Intnns1c frulure mechan1sms 2.4. Extnnsic failure mecharusms 2.5. Improvmg reliabihty 2.6. The phys1cs of degradation mechanisms 2. 7. Review of published work on MOS breakdown 2.8. Summary 2.9. References

3. EXPERIMENTS 3.1. Introduction 3.2. The MOS structures 3.3. Apparatus 3.4. Measurements 3.5. Experimental procedure 3 6. Summary 3.7. References

4. RESULTS 4.1 IntrOduction 4.2. Pulsed voltage stress expenments 4 3. Sequential pulsmg 4.4. Continuous voltage stress experiments 4.5. Summary

5. DISCUSSION 5.1. Introduction

Page No.

1

1 4 5 5 6

8 8 8 10 10 15 19 20 24 25

36 36 36 40 42 46 55 56

58 58 58 62 63 64

66 66

5.2. Damage in MOS strucrures 5.3. Pulsed voltage stress experiments 5.4. Sequential pulsing 5.5. Continuous voltage stress experiments 5.6. General 5.7. Summary 5.8. References

6. MODELLING OXIDE BREAKDOWN MECHANISMS IN MOS STRUCTURES

6.1 Introduction 6.2. The MOS structure 6.3. Properues of the silicon dioxide dielectric 6.4. Electroruc conducnon processes m silicon dioXIde 6.5. Charge injecnon mechamsms 6.6. The oxide breakdown model 6.7. Summary 6.8. References

7. DISCUSSION AND CONCLUSIONS 7 .1. Introduction 7 .2. Survey on failure mechamsms in seiDiconductor devices 7.3. Expenments on contmuous and pulsed voltage stressmg

of MOS strucrures 7.4. Oxide breakdown models 7.5. Future work 7.6. Summary 7.7. References

APPENDICES

1. Principal physical properties of wafer types 1 and 2.

2. Solution of SchrOdinger's equation for a potential barrier

3. Degradation mechanisms in silicon submicron MOSFETs

4. Abstracts of reports associated w1th th1s work

66 67 73 74 76 76 77

80 80 81 86 88 92 97 104 107

114 114 114 116

120 124 127 128

130

135

140

166

Report No. 1- MOD Contract No. A5a/1265, LUT Contract No. RXB 211W Report No. 2- MOD Contract No. A5a/1265, LUT Contract No. ELB 211W Report No. 3- MOD Contract No. A5a/1412, LUT Contract No. ELB 247L

5. Abstract of book: Failure mechanisms in semiconductor devices 172 -accepted for publicanon by W!ley (London), 1986

6. Electrostatic pulse breakdown in NMOS deVIces. 173 - QRE Int., 2, pp. 107-116, 1986

7. Oxide breakdown m MOS structures under ESD and connnuous 17 4 voltage stress conditions. - Proc. RELCON, pp. 325-330, Copenhagen, 1986.

8. A comparison between GaAs MESFET and Si NMOS ESD behaVIour. 175 - Proc. ERA Seminar on ESD in Electronics, pp. 4.3.1.-4.3.14, London, 1986.

9. ESD pulse and continuous voltage breakdown in MOS capacuor strucrures. 176 -8th Ann. Proc. EOS/ESD Symp., Las Vegas, 1986.

CHAPTER 1

INTRODUCTION

1.1. HISTORICAL BACKGROUND

The ongins of research into semiconducting matenals can be traced back as far as 1833

[1 ]. Michael Faraday probably made the first experimental observation in the

sermconductor field around this time, when he found that silver sulfide had a negative

temperatl!re coefficient of resistance [2]. Other conductors known at the time, all had

resistances which increased with temperature. The next significant discovery was m

1874, when Braun found that the resistance of contacts between certain metals did not

obey Ohm's law, and depended on the magnitude and polariry of the applied voltage (3].

Schuster (1874), made the same observation for contacts between tarnished and

untarmshed copper wrres [ 4].

It was not, however, until the 1930's and the advent of quantum mechanics, that a real

understanding of sermconductor properties began to evolve. The development of solid

state physics based on the concepts of energy levels with one electron per level, electron

spm, the Pauli exclusiOn pnnciple, and Fermi-Dirac statistics, enabled great strides to be

made in interpreting the behaviour of electrons atoms and molecules. Sommerfeld [5]

presented his free-electron model of metallic conduction based on quantum mechamcs m

1928, while perhaps the most Important contribution to the theory of semiconductor

physics was made by Wilson m 1936 [6]. He presented a quantum mechanical model of

a solid sermconductor, m which he showed that the movement of electrons as waves

throughout the solid set up interference patterns. Hence, certain energy levels were

excluded (forbidden), leading to the concept of energy bands m solids.

I

In 1925, the first known transistor was designed by Lillienfeld who ftled patents for it in

Canada and the U.S.A. [7][8]. Current flowed between two gold electrodes, through a

copper sulfide channel and was controlled by a potential on a third electrode (aluminium).

The pnnciple was ~imtlar to that of a MESFET. He later filed a patent in 1928 for an

improved FET biased on the insulated gate electrode, as m the MOSFET. Aluminium

ox1de was used as the insulator with copper sulfide again bemg used as the

semtconductmg material. In 1928, Ltllienfeld also patented a metal-base b1polar transistor

wh1ch consisted of several layers of metals and semiconductors with rectifying properties.

While it seems certain that Ltllienfeld was aware of the empincal theory of the operation

of transistors 1t is not known whether any of these devices was actually constructed.

However, it is believed that if manufactured using fabncation techniques available today,

those devices would have worked.

Shockley, Bardeen and Brattain, m 1947, constructed the first operational transistor. It

was a bipolar device based on germanium and was known as the point contact transistor.

They also made a vast contnbutlon to the development of the present theoretical

understanding of semiconductors [9]-[11][19]. For this work the three of them received

the Nobel Prize for physics in 1956.

Theoretically, the FET was still the most logical structure to form an amplifying device.

Experimentally it was Impossible to obtam efficient devices, the amphfymg effect

observed bemg much less than predicted. It was not until the Importance of surface

energy states was realised, that an FET was finally constructed and descnbed by

Shockley in 1952 [12]. Majonty earners formed the current m these devices making them

umpolar transistors.

2

Insulated gate transistors (IGFETs) had to wait unnl the advances 10 semiconductor

fabricanon techniques had been made. In particular, the development of planar diffusion

and the growing of passivation (Si02) layers, in 1959. The first metal oxide

semiconductor FET (MOSFET) was proposed by Kahng and Atalla 10 1960 [7].

Hofstein and Heimann, in the early 1960's, further developed this device to include

enhancement and depletion mode transistors, capable of operanng with different polarity

gate voltages [13]. MOSFETs 10 the 1980's, form the backbone of the semiconductor

industry, comprising a major portiOn of every piece of electronic equipment

manufactured.

Looking back over the years, it is perhaps possible to identify three Important aspects of

the developments in semiconductor technology which enabled the rapid advancement

towards todays devices.

1) The potential difference between p-doped and n-doped semiconductors, which IS 0.3

V at a typical silicon p-n Junction. The formation of a single-phase mterface between

p and n-type regions of the same material is Important to the semiconducting

properties of the devices.

2) The development of single crystal growth techniques which can provide long (> 15

ems.), large diameter (>7.5 ems.) crystals, with Impurities of =l:J09 has been VItal to

the advancement of senuconductor device technology.

3) The ability to grow a natural amorphous oxide on silicon, with good dielectric and

passivating properties, has made it possible to produce high quality, high performance

devices.

3

1.2. THE PRESENT AND THE FUTURE

The shnnkmg of the sennconductor device has been one of the great phenomena of recent

times. Very Large Scale Integration (VLSI) has made it posstble to pack large numbers of

active devtces mto very small areas of silicon. Today, commercially avatlable VLSI

circuits can have >800 deVlces per rnm2. Such crrcuits are capable of perfornnng a host

of complex functions, rangmg from htgh speed computation to automated control

systems.

Research m sennconductors is snll concentrating on making the transistor even smaller

[14][16]. The reasons behind this are basically economic. Since the cost of the stltcon

itself makes up the maJor portion of a manufacturer's financial burden, it stands to reason,

that, by increasing the number of transistors per unit area of silicon, the cost of each

tranststor is effecnvely reduced. Large packing denstnes as found in VLSI crrcuits, have

the added advantage of enabltng complex circmtry to be designed wtth a minimum of

external connections. Internal interconnections are more reliable and hence VLSI destgn

can increase the reliability of complex circuits. The number of pms as a function of the

number of gates for stlicon microprocessors and random logic i c.'s, is shown in Figure

1.1 [36]. It can be seen that 50 gates would have 10 pins in an i.e., whtle, if the number

of gates is increased to =106, the number of pins mcreases by only a factor of 10.

Silicon IS currently the prenner sennconductor material and is believed that it wtll remam

so unttl well into the 21st century. Recently, a great deal of attention has been focussed

on gallium arsenide (GaAs), a compound sennconductor wtth certain properties whtch

can prove to be an rmprovement on those of stltcon [16]. The higher mobtlity of earners

in GaAs and their lower effective mass means that GaAs devices would be more smtable

m very fast SWitching systems. Improvements in modern fabncanon techruques have also

4

No. of Pins

t 104

103

10 10

No. of Gates

FIGURE 1.1. The relationship between the number of pins and the number of gates found for silicon microprocessors and random logic LSI and VLSI chips (after ref. 36)

made it possrble to consrder new device strucmres which can take advantage of the

properties of GaAs to produce VLSI crrcuits capable of operating at very high speeds.

Advances in semiconductor fabrication techniques, means that it is now possrble to

manufacture very small dlmension (VSD) sllicon deVlces With operational sizes m the

subnncron region [16]-[18]. MOSFETs incorporating submicron channel dimens10ns

would introduce several new physrcal effects whrch must be considered m any analysis.

1.3. FAILURE MECHANISMS IN SEMICONDUCTOR DEVICES

The survey described m thrs thesis explored the available literature on frulure mechruusms

and combined it with several discussions with quahty and reliability personnel in the

semiconductor and equipment manufacmring industry. A shonlist of the most common

mechanisms was, therefore, obtained. Analysis of the quality assurance side of the

manufacmring mdustry also showed that the understanding of failure mechanisms was

important in achlevmg hrgher quality deVlces.

1.4 CHAPTER SYNOPSES

The survey on frulure mechanrsms is described m Chapter 2. The chapter concludes with

a revrew of published work on MOS oxide breakdown.

Chapter 3 descnbes the expenmental work on MOSFETs and MOS capacitors. Results

of pulsed and contmuous voltage stressmg are m Chapter 4. These are discussed m

Chapter 5.

5

Models of the breakdown processes are qualltatively developed in Chapter 6. A

description of the theories used is given, although only the important mathematical

equations are presented in the text.

Chapter 7 discusses the major points made in each of the preceding chapters and presents

an overall VIew of the whole project.

1.5 REFERENCES

1. PEARS ON G.L., BRA TT AIN W.H., History of semiconductor research.­

Proc. IRE, 43, pp. 1794-1806, 1955.

2. FARADAY M., Experimental researches in electriczty, Vol 1. - Bernard Quaritch,

London 1839.

3. BRA UN F., Uber die Stromleztung durch Schwefelmetall. - Ann. Phys1k. Chem.,

153, pp. 556-563, 1874.

4. SCHUSTER A., On umlateral conductivzty.- Phi!. Mag.,48, pp. 251-257, 1874.

5. SOMMERFELD A., Zur Elektronentheone der M eta/le aufGrunde der Fennischen

Statzstzk.- Z. fiir Phys., 47, pp. 1-32, 43-60, 1928.

6. WILSON A.H., The theory of electronic semzconductors. -Proc Roy. Soc. Lon,

A133, pp. 458-491, 1931. A134, pp. 277-287, 1931.

7. CO BB OLD R.S.C., Theory and applicatzons of field effect transzstors. - John

Wiley and Sons (New York), 1970.

8. GOSLING W., TOWNSEND W.G., WATSON J., Fzeld effect transistors.

- Butterworth (London), 1971.

9. BARDEEN J., BRATTAIN W.H., The transzstor - a semzconductor trzode. -

Phys. Rev., 74, pp. 230-231, 1948.

10. BRAITAIN W.H., BARDEEN J.,Nature of the forward current zn gennanium

point contacts. - Phys. Rev., 74, pp. 231-232, 1948.

6

11. SCHOCK.LEY W., PEARS ON G.L., Modulation of conductance ofthm-films

of semiconductors by surface charges.- Phys. Rev., 74, pp. 232-233, 1948.

12. SCHOCKLEY W., A unipolar field effect transistor. - Proc. IRE, 40, pp. 1365-

1376, 1952.

13. HOFSTEIN S.R., HEIMAN F.P., The s1licon insulated gate field effect

transistor - Proc. IEEE, 51, pp. 1190-1202, 1963.

14. SINGER P.H., Linewidth measurement: approaching the submicron dimenswn.

- Sem. Int., 6, pp. 48-54, March 1983.

15. DILORENZO J.V., KHANDELWAL D.D., GaAs FET pnnciples and

technology.- Artech House Inc. (Massachusetts), 1982.

16. BARKER J.R., FERRY D.K., On the phys1cs and modellmg of small

semiconductor devices- I. -Sol. St. Elec., 23, pp. 519-530, 1980.

17. BARKER J.R., FERRY D.K., On the physics and modelling of small

semiconductor dev1ces- Il. -Sol. St. Elec., 23, pp. 531-544, 1980.

18. BARKER J.R., FERRY D.K., On the phys1cs and modelling of small

semiconductor dev1ces- Ill. -Sol. St. Elec., 23, pp. 545-549, 1980.

19. SHOCKLEY W., The theory ofp-njunct!Ons in semiconductors and p-njunctwn

transistors. -Bell Sys. Tech. J., 28, pp. 465-489, 1949.

20. FERRY D.K., Interconnection lengths and VLSI. - IEEE Ccts. Dev. Mag.,l, pp.

39-42, 1985.

7

CHAPTER 2

SURVEY ON FAILURE MECHANISMS IN

SEMICONDUCTOR DEVICES

2.1 INTRODUCTION

This chapter begins with a study of the literature on failure mechanisms in

semiconductor devices. The work has been coupled to discussions with reliability and

quality engineers in the semiconductor and equipment manufacturing mdustries.

Hence, it has been possible to evaluate the dominant failure mechanisms and also to

evaluate the methods used to improve device reliability.

The next part of the chapter reVIews the published work on oxide breakdown m MOS

devices. Investigations into the breakdown of oxides is the focus of the work in this

thesis.

2.2. EVENT-RELATED FAILURES

Event-related failures are due to influences external to the actual deVIce. They can be

caused by Improper applicanon of equipment, careless handling of components or

operanons outside the component specificanons.

Manufacturers of semiconductor devices, as well as equipment manufacturers and

users claim that electncal stress damage accounts for over 50% of therr m-circuit

failures. This makes these failure mechanisms the largest contributors to reliabilty

degradation m the electromcs industry [I] -[5].

8

FIGURE 2 . 1 . Photomicr ograph of a GaAs MESFET , showing t he effect o f EOS . Burnou t has occurred in the channel region be cween the ga t e and the source . ( 125oox)

Inpu t

FIGURE 2.2

Resistor

~--------.----------· '------....J

Diode

Schematic of an input protection circuit.

To Trans istor

Electrical stress can be defined in two categories, namely, Electrical Overstress (EOS)

and Electrostatic Discharge (ESD). Figure 2.1. shows a photomicrograph of a typical

EOS/ESD damaged area on a GaAs MESFET. The hole in the semiconductor material

is due to the localised heating caused by the high electrical stress between the gate

contact and the source/drain contact of the transistor.

EOS failures are associated with hot-spot development in bipolar devices [6]. In MOS

devices the stress causes the oxide (field or gate) to breakdown [7].

These failures can be prevented by incorporating protection circuitry capable of

dissipating the excess electrical stress. A schematic of an input protection circuit is

shown in Figure 2.2.. The diode is in reverse bias and is designed to turn on at a

voltage below the breakdown threshold of the transistor. More complex structurs are

used to obtain the high levels of protection required under ESD conditions (up to 4kV)

[8][9].

ESD is the result of the discharge of static through a semiconductor device. Voltages

may range from lOOV to 20kV depending on the environment. The discharge could

take place by touching the device after accumulating static on oneself. It is also

possible to transfer static charge onto a device. In this case discharge takes place

when the device is placed in contact with a ground plane [3][4][10][11][18].

9

2.3. INTRINSIC F AlLURE MECHANISMS

Failures which can be traced to the fabrication stages of device manufacture are termed

intrinsic. It is here that inherent flaws such as crystal defects and low quality thermal

oxide growth can lead to failure during the worlcing life. Contamination can also be

introduced at this stage which will eventually limit the device lifetime as discussed by

Lange [12] and Schmidt [13].

Edwards [14] in a review paper on MOS failure mechanisms identifies defective gate

oxides, the trapping of charge in the oxide at impurity sites, and the presence of

contaminating ions as being the major problems. Partridge [15] in a review paper on

bipolar failure mechanisms shows crystal defects to be important. Diffusion of dopant

ions along these crystal defects may result in parametric shifts of the electrical

characteristics. Low frequency noise has been traced to the presence of crystal defects

(17]. In extreme cases devices may short-circuit across a junction resulting in

catastrophic failure [16]. Stojadinovic [64] looks at the principal failure mechanisms

in bipolar and MOS devices in a review paper published in 1983.

As technologies marure and fabrication processes improve, intrinsic fail ures are

reduced. Instead, device reliability is more influenced by extrinsic failure

mechanisms.

2A. EXTRINSIC F AlLURE MECHANISMS

Extrinsic failure mechanisms are introduced by the packaging and the

interconnections. The term packaging describes the die attach, the lead frame and the

10

ceramic or plastic encapsulation of the device. The rnetallisarion deposited on the chip,

the bonds and the attached leads are considered to be the interconnections.

2.4.1. The packaging

Semiconductor devices can be packaged either hermetically in ceramic or completely in

a solid epoxy [20]. The former are known as Ceramic Dual-in-Line Packages

(CERDIPs), while the latter are Plastic Encapsulated Devices (PEDs).

The critical element in the CERDIP structure is the leaded "sealing" glass which must

provide a reliable hermetic seal against corrosive elements. In addition, moisture

ingress along the lead frame causes corrosion of the metallisation on the die with the

occurrence of eventual failure [20].

PEDs are prone to moisture ingress through the porous plastic which means low

reliability can be expected in high humidity environmentS. Also, the epoxy introduces

contaminants which, because of the direct contact between the plastic and the silicon,

will be a reliability hazard [23][24]. However, the introduction of inhibitors against

moisture and contamination has improved the reliability of PEDs to the extent that they

are found to be comparable to that of the CERDIPs in benign environments [25][26].

This is supponed by data obtained from both laboratory lifetests [20][21], and from

field failures [22][25].

2.4.2. The die attach

Two main failure mechanisms are associated with the die attach. The first is the

integrity of the contact made between the die and the lead frame. Voids in the die

attach lead to eventual detachment or thermal/electrical failure due to bad contact

1 1

[27][28]. Secondly, there is the problem of contaminants and moisture introduced by

the epoxy die attach system or the lead frame. These are discussed by Manchester

[29] and Powell [30]. PEDs are found to be inferior to CERDIPs in this respect

because of the problems associated with the eutectics. The use of side-brazed hermetic

packaging as opposed to the dual-in-line lead frame is found to reduce moisture

ingress [20]. This is because, unlike the CERDIPs, the lead frame in side-brazed

packages is not in direct contact with the interconnects. These devices, therefore, tend

to be less prone to contamination and more highly resistant to moisture.

2.4.3. The meta llisation

Mechanisms affecting the metallisation are a) corrosion, b) electromigration, c) contact

migration, d) stress relief migration. In addition, problems related to oxide steps on

the die surface can lead to cracks forming in the metal film at those points. This is

illustrated in Figure 2.3. along with the fabrication technique used as a solution.

Aluminium is the most extensively used element for metallisation and interconnections

in i.c's.

Corrosion: A survey of corrosion failure mechanisms in microelectronic devices has

been conducted by Schnable et al [31]. Corrosion is an electrochemical mechanism

which occurs in the presence of moisture and a d.c. operating potential. Chlorine or

sodium ions act as catalysts to the process [32].

Electromigration : When the current density in the metal is greater than 106 A

cm-2, electromigration takes place. The continuous impact of electrons causes the

aluminium grains to move in the direction of the electron flow. A void is created at

one end of the track while the metal is piled up at the other end [33]. The AI grain size

12

Aluminium We ak spot in Al film with potential to form

microcrac k

Figure 2.3 . (a) Metal deposited over a steep step .

Aluminium Microc r ack

.:..luminium

Fi gure 2.3. (b) Formulation of a microcrack .

Aluminium ape r to ob cain

metallisat1.o n ac st.ep

fieure 2.3 . (c) Tapering of steps to elimina t e microcracks

Figure 2 .3 . Schematic illustration of microcracks in Aluminium me tallisation.

Wire (Au)

Loop - if too tight, tension in wire is high and tends to f r acture; if too loose then t:.he wire is f r ee to move and may short ci rcuit with adjacent

wires .

Lag (as

- tens1on is important described for the loop)

- weak point in hi cjh

tension ~qc~~~~----~~~~~

attaching wire t:.o met:.allization on the die

formation

Wire attached to lead frame by \·Jedge l:>on<i

Figure 2 .~ . Diagram of a bond wire showing potential weak points .

is important in this process; smaller grain sizes lead to an increase in mass transport.

As a result of work by researchers such as Black [33][34] and D'Heurle [35] into the

physics of electrornigration methods have been developed to minimise the problem.

These methods centre on the use of Al alloys incorporating small percentages of Cu or

Si [77].

Contact migration: Migration can also take place at the Al or Si interface of the

metal contacts [36]. The migrating species could be either Al in Si or Si in Al. Failure

may manifest itself as either a short-circuited junction or an open contact [36][37].

Inhibiting the diffusion of Al and Si is accomplished using Al alloyed with Si or Cu.

Complex alloys such as PtSi-Ti/W-Al is found to greatly enhance contact integrity [2].

Stress relief migration: Deformation of the metallisation occurs as a result of the

movement of atoms from areas of high stress. Failures occur due to whisker growth

[38][39] under cornpressive stress, or by the formation of hillocks and voids [15][40].

Again, the us~oys can prevent this mechanism.

2.4.4. Bonding

The bond can be considered to be one of the weakest areas of the package and

interconnects, although improvements in the manufacturing processes and tighter

quality controls are reducing the number of inferior products reaching the consumer

[41][45]. Figure 2.4. illustrates the areas in a wire bond where failures are commonly

observed.

At the interface between the gold bond and the Al rnetallisation, the formation of

Au2Al in excess is a serious problem. The quality of the contact at the base of the

bond is undermined by the intermetallic and results in failure [ 42]. Adjacent bond

13

wires may short-circuit if the loop between the die and the lead frame has too much

sag. If the loop is too tight, the tension created at the heel of the bond and in the wire

itself can cause fracturing of the bond metal [43].

Moisture aided migration at the base of the bond and the presence of contaminants in

the metallisation can expedite voiding and bond detachment [44][45]. Whisker growth

as a result of excessive bonding pressure has already been discussed. If the bond

pressure is too low, fractures can result at the bonding interface.

In the moulding process used for PEDs, the backwash of the plastic compounds could

force the bond wires to shon-circuit. The moulding process can also cause high stress

in the bond wires [46][47].

Process improvements and design optimisation have reduced failures due to

intermetallic formation. Careful monitoring of the bonding pressure and the loop

formation has improved the quality of the bonds.

2.4.5. Alpha particle radiation

Trace impurities of radioactive elements (e.g. Thorium, Uranium) in the packaging

material can emit alpha particles with energies upto 8 Me V [48] - [51]. Interaction of

these panicles with ions in the bulk material results in the generation of hole-electron

pairs. The charges move by diffusion through the bulk of the device and significantly

affect the operation of a device such as a dynamic RAM. The alteration of the stored

charge in a memory cell due to the radiation causes the stored data to be changed.

14

Prevention techniques are focused on limiting the collection efficiency of electrOns at

the storage nodes [48]. A trade-off between device parametric degradation and soft

error rates is recommended [52].

Other forms of radiation, e.g. gamma-rays and X-rays can also result in similar

degradation [53] - [56] . One of the major problems encountered with external

radiation is that of CMOS latch-up [55][57]. The radiation causes a parasitic bipolar

transistor in the CMOS structure to turn on, and the output of the device latches to one

of the supply rails, rendering the device useless.

2.5. IMPROVING RELIABILITY

2.5.1. Screening

Screening is the process by which defective devices are identified and removed from a

production patch. A study of the device physics and its failure mechanisms would

enable a good screening procedure to be developed based on the activation of the

relevant defect mechanisms. For example, Crook [7] shows how a high voltage

prestress across an oxide dielectric can be used to cause premature failure of weak

oxides. Therefore, the reliability of the screened batch of devices is improved. In

Figure 2.5., the failure rate of a batch is plotted as a function of time. An electric field

of 2.5 MV /cm is applied to the device for one second. The dotted line shows the

increased failure rate due to the stress. Infant monalities due to weak oxides have,

therefore, been eliminated.

The standard tests for microelectronic devices are given in the MIL-STD-883C [58],

BS 9300 [59] and BS 9400 [60]. An example of the screening processes used by a

semiconductor manufacturer is given in INTELs reliability repon on the 2164 A 0-

15

12

10

8

LOG FAILURE

RATE

(:!/1000 hr~)

4

2

0

- 6

1 sec Pres~reen ac 2.5 MV cm-1

MOS Capac i cor

c ox 100 A

Concinuous scress ac 2 MV cm- 1

Long cerm scress ac 2 MV cm- 1 afce r prescreen

-4 - - 2 0 2

LOG TI ME (SECONDS)

Effeccive Aging Time of Prcscreen

4 6 8

FIGURE 2. 5 . An example of screening. A high voltage pr estress across an oxide dielectric is shown to e liminate defective oxides.

RAM [63]. Ryerson [61] presents a comprehensive review paper on reliability testing

and screening methods upto 1978.

Principal tests used in screens are:

1. High temperature burn-in; devices are typically subjected to 125 °C for 48 hours.

This is considered to be more a process monitor than a screen since it is intended to

remove devices which fail as a result of manufacturing defects, rather than to

address a specific failure mechanism [ 62].

2. High temperature storage test; devices are baked at around 250 °C for hermetic

devices and 150 °C for PEDs. The intention being to detect any instability

mechanisms in the devices [63].

3. High temperature reverse bias test; overvoltages (50% above the maximum

specified voltage) are combined with high temperatures ( 150 °C) to make an

effective screen against mobile ion contamination, particularly in MOS devices

[64].

4. Thermal shock; a technique to evaluate the integrity of the package. The device is

alternately subjected to temperatures between -65 °C and +125 °C for about 10

seconds at each level. Bad thermal matching, for example between the passivation

layer and the die, would be detected by this test. Crystal defects are also sensitive

to this screen.

5. Temperature cycling; structural defects are aggravated by temperature cycling.

Devices are placed in hot/cold air-to-air cycling chambers for 10 cycles of -65 °C to

+150 °C and held for approximately 10 minutes at each extreme.

6. Humidity tests; usually at 85 °C/85% Relative Humidity (RH) or 120 °C/2

atmospheres at l 00% RH. These rests indicate the resistance of the packaged

device to failure mechanisms associated with moisture ingress, e.g. corrosion.

16

The above list is not exhaustive and other tests are also carried out depending on the

level of screening specified. These would test for hermettcl!y, loose debris in hermetic

packages, and the quality of the bonds. All screens must be followed by electrical

funcnonal tests [ 65].

2.5.2. QUALITY ASSURANCE

Generating quality specifications, control of quality conformance with specifications

through incoming inspection, and quality inspection of the fimshed products are all

parts of the QA system [66] - [68].

Wernik [67] and Hutchins [68] recommended the policy of "getting-it-right-first­

time", as opposed to testing-in quality. In order to achieve this goal, the physics of

the device and the mechanism of degradation must be understood. Hutchins shows

that the failure rate of microprocessors was halved as a result of making improvements

to fabrication techmques and converting to improved matenal. This is an example of

progress along the learning curve. Reduction of flaws generated by poor quality

workmanship was observed after the workforce was made aware of reqwred product

quality levels.

Qual!ty is measured m terms of acceptable quality levels (AQLs) where sample

numbers of a batch are tested to a g~ven speclficanon. The batch IS passed dependmg

on the percentage number of defects present [66]. H1gh nsk samples, where the

sample size IS too small for the volume of production, results in low confidence levels

m the reliability estimates. Procurement specifications dictate the levels of sampling

and screemng required for a defined application.

2.5.3. Reliability Estimations

17

Reliability estimates proVIde a yardstick by which the quality of a component can be

evaluated. The pnnc1pal reliability model which comes closest to universal usage is

that presented in the U.S. Department of Defense publication MIL-HDBK-217D [69].

The model Is based on data covering 1010 deVIce hours collected from accelerated

lifetests, screemng, bum-in and field expenence [70].

Objecnons to the MIL-HDBK model are based on the variance between the calculated

and observed failure rates. Blanks [71] and O'Connor [72] point out that the high

values given to the quality factors are unjustified. These quality factors are assigned

values depending on the level of screening used and are, " ... .intended to represent the

nsk associated with inadequate screening and the reliab!lty enhancement which can be

realized through an effecnve screening program." [70]. Hence, although a disparity is

observed in failure rates, the estimates can be considered to be safe.

Reliability estimates are also made by accelerated tesnng of devices; I.e. prematurely

inducing failures by exposing the devices to elevated temperature ambients. The

failure rates are then extrapolated to standard operating conditions usmg the Arrhemus

Equaoon [16][73]. One Important requirement before accelerated tesnng, IS to ensure

that expected failure mechamsms are governed by this equation. Typical accelerated

tests use temperatures between 75 °C and 225 °C, although lower or higher

temperatures are used for specific mechanisms. The device may be operated dunng

the test. Additionally, an ambient of humidity or pressure can be included [74].

Sample sizes vary according to expected failure rates. Low failure rates require large

sample Sizes to provide a high degree of confidence in the results.

Objecnons to the valichty of accelerated test results are based on the pomt that the die

surface may not be at the ambient temperature and humidity [75][76]. Stanley [75]

18

has also found that temperature excursions about the mean die temperature ranged

from -16 °C to +17 °C. Herr et al [76] have shown that a device exposed for over a

week to an ambient of 85% RH, shows only 12% RH at the die. However, if careful

controlts maintained over experimental cond;iions, valid estimates of device fatlure

rates can be made from accelerated IJfelests.

2.6. THE PHYSICS OF DEGRADATION MECHANISMS

A study of the physics of degradauon processes and failure mechanisms enables a

better understanding to be gained. From the work described m this chapter, four areas

of research, significant to the next generation of semiconductor devices, can be

identified. The results of the research, when applied to the development of such

devices, would then mean that the co=erctal manufacture of these devices begins

further along the leammg curve discussed by Hutchins [68] and Brambilla [78].

The four areas are:

1) Electrical Overstress (EOS)/Electrostatic Discharge (ESD) damage. A high

proportion of failures are attnbuted to thts mechanism. Research would foster a

better understanding of the effects of the fabrication techniques and device

structures on the sensttivlty of components to overstress effects.

2) Subtmcron Technology. Devtces based on this technology are expected toform the

backbone of the next generauon of semiconductor devices. Studies into posstble

degradation mechantsms or the extent to whtch existing mechanisms would effect

such devtces will enable potenual problem areas m the development to be

antictpated.

19

3) GaAs. Integrated circuits using GaAs are still very much at the initial stages of

development. As with submicron technology, studies on GaAs would aid this

development

4) Radiation. The effects of radiation become more imponant as device dimensions

get smaller. Research in this area will help to improve the quality of radiation­

hardened devices.

Of the above four areas, the effects of electrical overstress voltages, both continuous

(simulating EOS) and pulsed (simulating ESD) has been investigated by the author. It

has also been attempted to use these results to predict the effects of electrical overstress

m subnucron s1licon MOSFETs.

2.7. REVIEW OF PUBLISHED WORK ON MOS BREAKDOWN

Elecmcal conducnon and breakdown in solid dielectrics has been a subject of research

since the mid 1920's. Wagner [lOO] investigated dielectric breakdown related to weak

spots in the insulator. Fowler and Nordheim in 1928 [79], proposed their theory of

quantum tunnelling through a potential barrier at a metal-vacuum interface. This was

adapted for dielecmcs by Frohlich in 1937 [80]. Frenkel [81] looked at the effect of

electric fields on the conduction band in a dielectric or a semiconductor in the presence

of lffipurity sites. Frohlich later expanded on his work in the light of discovenes by

other researchers, to develop an empirical model for the breakdown of ionic crystals

based on avalanche multiplication by collis1on ionization [82][83]. Se1tz [84] correlated

the breakdown field strength to the number of collisions requrred for breakdown.

Whitehead [85] presents an extensive survey on existing work upto 1951 as well as

expanding upon dtelectnc breakdown theories. O'Dwyer presented a modification of

the simple avalanche model, to take into account the field distortion as a result of the

space charge build up due to the avalanche [101]. His book [86] on d1electric

20

breakdown is a comprehensive work on the subject (upto 1972) covering expenmental

data and existing theories on breakdown.

Most of the early work on dielectric breakdown concentrated on ionic crystals. Klem

[87] investigated the breakdown properties of I03A to I04A silicon oxide films on

glass substrates using AI electrodes. The samples were subjected to continuous voltage

stress and the analysis of breakdown fields was made on the principle of electromc

avalanche in the dielectric. Further work by Klein [88], and work by Osbum and

Ormond [89], and Osbourn and Weitzmann [91] have looked at dielectric breakdown,

particularly, in amorphous Silicon dioxide, in terms of the electron avalanche effect.

Osbum et a! observed different breakdown thresholds with different Si dopant

concentrations, but do not qualitatively analyse this effect

Silicon dioxide IS a wide bandgap insulator. DiStefano and Shatzkes [92] present a >l!

theoretical breakdown model based on impact IOnization. Their model considers the

behaviOur of the electrons only after they have entered the silicon dioxide. The

influence of the electrodes on the injected charge has not been smdied by them.

However, the role of the silicon surface in the InJection process cannot be neglected.

Weinberg [93][94] shows that under lugh electric fields, the band-bending at the silicon

surface leads to quantisation of charge in the Si conduction band. This, in mm, can

effect the mnnelling current. Smdies on surface quantisation have been conducted by

Stem et a! [95][96] and Nakamura et a! [97], who have evaluated the separation

between the quantised energy levels at high fields.

Oxide breakdown as a result of trap generation m silicon dioXlde was first proposed by

Harari [98] to explain the non-samrating behaviour of the applied voltage in constant

current expenments. Others have observed snrular behaviour [99] in the form of slufts

in capacitance-voltage curves as a function of the injected charge. They have also

21

regarded the non-saturating behaviour as an indication of the generation of traps in the

oxide layer. The generating of new electron traps under high-field stress has been

inferred by Badihi et al [102] and Heyns et al [103]. Heyns observes a large number

of electron traps at the p-Si-Si02 interface when the p-Si surface is in strong

accumulation, while Badihi concludes that the injection of charge into the OXIde at high

fields is the cause of damage. Wolters et al [104]- [106] present a model for dielectric

breakdown in MOS devices based on charge injection. They conclude that with

continuous current mJectlon (d.c. voltage stresses) the energy gained by the injected

charge IS not sufficient to support Impact ionization. On the other hand, The1s et al

[107] show that with the same constant electric fields (5MV/cm to 12 MV/cm) electrons

have sufficient energy to tunnel into the Si02 conduction band. They calculate that this

energy (3 to 4 e V above the Si conduction band) is sufficient to sustain impact

ionization. Welter's has based h1s model of the discharge pattern of the oxide

breakdown on Budenstem's tree model of breakdown in insulators [108].

Budenstein's work, based on KBr single crystal dielectrics, Alz03 and Si02, showed

that the discharge patterns in the dielectrics were tree shaped. The trunk of the tree 1s at

the anode, and the branches are formed by the movement of electrons, from traps

dJ.stnbuted throughout the sample, towards the anode. Budenstein was able to observe

and photograph the discharge patterns because his samples were very thick, ranging

from 0.6 Jlill to 3.1 mm. Further evidence of trap generation and its precedence to

breakdown IS presented in a very recent paper (1986) by LeBlanc et al [109]. The

effect of traps on the internal fields m the oxide has been quantitatively modelled by

Chen et al [115]. Nissan-Cohen et al [110] have studied the effect of continuous

charge injection on the physical properties of the Si02. They found that the trap

generation rate is proportional to the flux of the injected charge and increases

exponentlally with the electnc field m the oxide (between 4 and 10 MV/cm). Traps are

believed to be formed by broken Si-0 bonds. Olive et al [111] have presented a model

for electron trapping m thm Si02 films. The model is based on the presence of

22

defective Si-0 bonds in the oxide region which can form traps, in constant electric

fields.

Klem [112] discusses the difference between impact ionisation and charge injection

models of breakdown in solid dielectrics. He reviews breakdown data taken from

numerous sources regard!ng different types of dielectric materials, ranging from single

crystal alkali halides to amorphous Si02.

It becomes apparent that the one constant parameter in dielectric breakdown

experiments is the breakdown field strength. This is of the order of 5 - 10 MV /cm,

irrespective of the material. Therefore, It seems that the breakdown strength IS less

affected by the matenal composition than by weaknesses which may exist in the

dielectric. Cohen [113] has shown that the electric field strength of SI02 can be

improved by considering the intrinsic defect density in the film. Balk et al [114] show

a reduction in the density of electron traps after post-oXIdation high temperature

annealing. One may conclude that a completely defect-free oxide will have an electric

field breakdown strength, which could be orders of magnitude higher than those

obtained at present.

All the work reviewed in this section has dealt with the breakdown of dielectncs under

the influence of constant applied voltages or constant charge injection. The breakdown

voltages of the d!electrics used, have been between 5 - 10 MV /cm, thereby lirmting the

extent of the voltage stress that can be applied. No literature on pulsed voltage

breakdown experiments was found with regard to MOS structures. None of the

extensive works discussed here [106][110][112][115] refer to any work on very high

voltage tnmsients. Klein [ 112] men nons that expenments using pulsed voltages would

help to develop a more definitive model of the oxide breakdown mechanism. In this

thesis, the expenmental work on pulsed voltages, has looked at the effects of electric

23

fields in excess of 100 MV /cm. A model has been developed for the breakdown

mechanism, which draws on both the impact iomzation and the charge injection

theones.

2.8. SUMMARY

1. A descnption of the major failure mechanisms in semiconductor deVIces has been

presented, with reference to published work on the subject. The author has dealt

with the topic m greater detrul in a book which IS to be published later this year

[116].

2. Methods of obtaining higher reliability have been discussed. It is believed that the

focus should be on the policy of "getnng·it·right·frrst·time", rather than attempnng

to screen out defective devices after the manufacrunng process has been completed.

3. Reliability estimates obtruned VIa modelling and accelerated test methods can only be

looked upon as indicators of component lifetimes. In order to perform valid

accelerated tests, it is necessary to conduct a detailed study of the failure

mechanisms involved and the effects of accelerated stress factors on expected

degradation mechanisms.

4. A study of the physics of frulure processes IS therefore seen as bemg important in

the development of high reliability components. Four areas of research were

proposed. This thesis investigates the effects of high electric fields on MOS

devices.

5. A review has been made of published work on MOS oxide breakdown. It shows

that models of breakdown have been based on, either, the theones of trap

24

generation in the Si02 or impact ionization. Experimental work on very h1gh

voltage pulses, with the intention of studying the physics of the breakdown

process, has not been found. The work presented in this thesis intends to fulfil!

this void.

2.9. REFERENCES

1. SMITH J.S., Analysis of electrical overstress fazlures-- 11th Ann. Proc. IRPS,

pp.106-109, 1973.

2. CANALI C., FANTINI F., GAVIRAGHI S., SENIN A., Reliability

problems zn TTL-LS devices - Microelec. and Rei., 21, pp. 637-651, 1981.

3. MOSS R.Y., Caution- electrostatic dzscharge at work-- IEEE Trans. Comp. Hyb.

Man. Tech., 5, pp. 512-515, 1982.

4. SCHREIER L.A., Electrostatic damage susceptibility of semiconductor devices -

16th Ann. Proc. IRPS, pp. 151-153, 1978.

5. TURNER T., Static in a wafer fabricatzon facility: Causes and solutions -

Semicon. Int., 6, pp. 78-84, May 1983.

6. ALEXANDER D.R., An electrical overstress failure model for bzpolar

semiconductor components. -IEEE Trans. Comp. Hyb. Man. Tech., 1, pp. 345-

353, 1978.

7. CROOK D.L.,Method of determining reliabzlity screens for tzme dependent

dielectric breakdown -17th Ann. Proc. IRPS, pp. 1-7, 1979.

8. BHATTI I., FULLER E., JENNE F.B., VMOS electrostatic protection -

16th Ann. Proc. IRPS, pp. 140-145, 1978.

9. FISCH D.E., A new technique for input protection testzng. - 19th Ann. Proc.

IRPS, pp. 212-217, 1981.

10. DENT ON D.L., Guzdelznesfor establishing an effective ESD program.- Sol. St.

Tech., 23, pp. 127-134, Jan. 1984.

25

11. HART.,SMYTH J., GORSKI S., Predicting ESD related reliability effects -

20th Ann. Proc. IRPS, pp. 233-237, 1982.

12. LANGE J.A., Sources of semiconductor wafer contamznation.- Semicon. Int.,

6, pp. 124-128, Apnll983.

13. SCHMIDT P.F., Furnace contamination and remedies -Sol. St. Tech., 26, pp.

6-12, June 1983.

14. EDWARDS D.G., Testing for MOS !Cfmlure modes. -IEEE Trans. Rel., 31,

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15. PARTRIDGE J., Testing for bipolar integrated circuztfailure modes.- IEEE Test

Conference, Digest of Papers (TESTCON), pp. 397-407, 1980.

16. CASEY J., LEE J., REDMAN D.J., ZIMMERMAN D., Soft pipes cause

rel!abil!ty problems in bipolar integrated circuits.- 21st Ann. Proc. IRPS, pp. 191-

197. 1983.

17. MIHAILA A., AMBERIADAS K., Nozse phenomenon associated with

dislocations in bipolar transistors -Sol. St. E1ec., 26, pp. 109-113, 1983.

18. UNGER B.A., Electrostatic discharge fazlures of semiconductor devices - 19th

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19. LYCOUDES N., CHILDERS C.G., Semiconductor instability failure

mechanisms review.- IEEE Trans. Rel., 29, pp. 237-247, 1980.

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USA, 1982.

21. FOX M.J., Companson of the performance of plastic and ceramzc

encapsulations based on evaluatiOn ofCMOS integrated circuits.- Microelec. and

Rel., 16, pp. 251-254,1977.

22. HAKIM E.B., U.S. Army field test of plastic encapsulated devices - Microelec.

and Rel., 17, pp. 387-392, 1978.

26

23. REICH B., Reliability of plastic encapsulated semiconductor dev1ces and

integrated Circuits.· Sol. St. Tech., pp. 82·88, Sept. 1978.

24. FEDERICI F., MAMMUCARI F., TURCONI G., Influence of plastic

encapsulated i.e.'s on TLC equipment. - Proc. Eur. Conf. on Rel.(EUROCON), pp.

243-248, 1982.

25. SINNADURAI N., ROBERTS D.,Assessmentofmicropackagedintegrated

circuits in high reliability appl1cations.- Microelec. Journ., 14, pp. 5-24, 1983.

26. GOOSEY M.T., Reliability improvements of plastic encapsulated devices. -

CVD Bulletin of abstracts, 30, Item 152, Annual Research Report, RP9-2220,

Nov.1979-0ct.1980.

27. KITCHEN D.R., Physics of die attach znterfaces - 18th Ann. Proc. IRPS, pp.

138-141, 1983.

28. CARLSON R.O., YERMAN A.J., BURGESS J.F., NEUGEBAUER

C.A., Voids, cracks and hot spots in die attach. - 21st Ann. Proc. IRPS, pp. 138-

141,1983.

29. MANCHESTER K.E., BIRD D.W., CHAREST H., A contribution of

polymer die attach systems to the reliability of plastic encapsulated integrated

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27

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67. WURNIK F.M., Qualzty assurance system and reliabzlity testing of LSI circuits.

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31

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32

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33

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34

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35

CHAPTER 3

EXPERIMENTS

3.1. INTRODUCTION

Expenmental work was focused on the influence of high electric fields on thm MOS

gate oxides. Continuous and pulsed voltages were used, simulating EOS and ESD

conditions respectively.

The devices were small dimension, discrete n-channel and p-channel MOS transistors

with no input protection at the gate. The gate dimensions ranged from l~m x !~m to

1 00~ x lOO~m. Separate gate oxide capacitors with the same structural properties as

the transistors were also available on the same chips. These devices provided an ideal

base for an investigation mto the physics of the breakdown mechanisms of MOS

devices.

3.2. THE MOS STRUCTURES

3.2.1. Introduction

The MOS devices were resident on two types of Silicon wafers. Both wafer types

were manufactured by Plessey Research (Caswell) Ltd., as part of therr NMOS and

CMOS small geometry process charactensauon [2]. The use of process

characterisation wafers enables the study to be based on possible production

situations. This is an advantage over workmg with Idealised wafers manufactured

especially for the purposes of this research.

36

FIELD OXIDE

FIGURE 3 1

SILOX

p - substrate

Cross sect1on of trans1stor on wafer no: 1.

POt YSILI(ON n .. flELO OXIDE

FIELD OXIDE

__ ! Boron 1mplant I P~ 4><l)t.$cm- 3 \'-----

p type S1

(a)

• An E-Mode p-51. MOS Capac1.tor, 1.ndtcat1ng the p -type Boron-Lmplant at the Semtconductor Surface

,p ! H& ! ! ~ CJRJiJ Dllllllllll .p R 0 510 ggg~tQ .ogg ... ·P CJ o 9 o Q OauOJJ Q .[JOOCJQ~l " ~~==

Q 11

7[] [J y 51 %1 g p g ~ 011111111

Fig.3,3 _ A map of a block of transtst.ors on 1nrcr no 1 The pattern LS repeated about lOO ttmes throur,h the wa[et

FIGURE 3 . 4 . A map of a block of trans is t or s on wafer no : 2 .

FIGURE 3 . 5 . (a) Photogr aph of Wafer No : l.

D . [ 0 ( WO. r y = 3 i ..... c.hes LO.I"ne1ev t ~

FIGURE 3 . 5 . (b) Pho t ograph of ~.Jafer No : 2 .

3.2.2. The NMOS process characterisation wafers (Wafer type No.l)

The 3-inch wafers consisted of both enhancement-mode (E-mode) and depletion-mode

(D-mode) transistors of varying dimensions. A schematic cross-secnonal view of an

E-mode transistor is shown in Figure 3.1.. MOS gate oxide capacitors were

fabricated on the same ch1ps as the transistors. A cross-sectional view of a capacitor

simulating the gate oxide structure of an E-mode NMOS transistor is schematically

represented in Figure 3.2 ..

The devices were manufactured on 3-inch p-type wafers, of resistivity 20 n-cm,

associated with a substrate dopant concentration of 6.6 x 1014 cm·3 [3]. Preferential

doping in the channel was obtained by ion implantanon of boron to a density of 4 x

JQ15 cm-3 holes, forE-mode devices. D-mode devices had a further phosphorus

implant to giVe a net charge density of 4 x 1015 cm-3 electrons. Source/drain dopmg

was by arsenic rmplantation to a charge density of 2 x 1Q20 cm·3 electrons.

The gate oXIde was thermally grown at 950 °C, to a thickness of 425 A (42.5 nm), and

is umform throughout the wafer. The field ox1de was 0.6J.l.Ill thick.

Wafer passivanon was provided by a l.5J.lm thick layer of silicon glass. Electrical

isolation was provided by the implant of boron ions.

The NMOS transistors were hud out as shown in Flgure•3.3. Rows 1 to 11 shown

here, represent 88 E-mode devices on the ch1p. Rows 12 to 22 repeated the pattern, to

proVIde 176 E-mode transistors altogether. Rows 23 to 33 consisted of D-mode

NMOS transistors. The layout of these transistors IS idenncal to those in rows 1 to

11. In addition, one E-mode capacitor and one D-mode capacitor were on each ch1p.

37

The capacitors had a gate area of 49 x 103 J.l.lll2 with a peripheral length of 9l0J.I.lll. n+

polysllicon gates were deposited usmg chemical vapour deposition (CVD) techniques

and doped with arsenic ions to a density of approximately 1 x 1Q21 cm·3.

The surface state density at the Si-Si02 interface was estimated by the manufacturers

to be of the order of 1 x 1011 cm·2 [4].

The mask described for this chip covered a surface area of 6 mm2 and was repeated

about 100 times across each wafer. 4 wafers of this type were provided for the

expenmentatlon.

Appendix llists the principal specificanons of this wafer.

3.2.3. The CMOS process characterisation wafers (Wafer type No.2)

E-mode PMOS transistors were fabricated on a 3-inch wafer. The n-type substrate

was doped to a concentranon of 2 x 1 Ql4 cm· 3, associated with a resiStiVIty of 25 Q.

cm [4].

The E-mode PMOS transistors consist of boron source/drain diffusions with dopant

densities of 5 x 1Ql9 cm·3 holes. The channel was preferentially doped to a

concentration of 1 x 1Ql6 cm·3 with n+ (As) ions. E-mode transistors were fabncated

in a p-well which was doped to approximately 2 x 1Ql5 cm·3. The channel was

preferentially doped usmg boron to a concentration of 1 x 1Ql6 cm·3.

The gate ox1de thickness was uniform throughout the wafer at 320 A (32nm). The

field made was 720 nm thick.

38

The PMOS transistors were laid out as shown in Figure 3.4.. Each chip contained

four rows of transistors with eight deVlces per row. NMOS transistors on the same

chip had the identical layout. In addition, one E-mode NMOS capacitor (p+-Si

surface) and one E- mode PMOS capacitor (n+-Si surface) were available on each

chip. The capacitors had gate areas of 4.9 x 1 Q3 Jlii12 with a peripheral length of 280

Jliii. Schematic cross-sectional views of the transistors and capacitors are the same as

those presented in Figures 3.1. and 3 2 ..

All devices had n+ polysilicon gates doped to approximately 1 x IQ21 cm-3. The

surface state density at the Si-Si02 mterface was estimated to be of the order of I x

1011 cm-2 [4].

The mask described for this chip covered a surface area of 6 mm2 and was repeated

about I 00 times across the wafer. Two wafers of th1s type were provided for

experiments.

Appendix 1 lists the principal specifications of this wafer.

3.2.4. Past history of the samples

The wafers had not been subjected to any post-manufacture lifetesting before bemg

used in the experiments. Electrical functional tests, however, had been carried out to

evaluate the process employed in fabncauon. These tests measured the threshold

voltages, gam and the drain-source currents under specified b1as conditions. The

electrical dimensiOns of the channel were calculated, g:tvmg values for the change m

channel length (M.) and the change in channel width (!:> W) caused by the fabncanon

process. t:J.L was the result of lateral diffusiOn of source/dram dopants, while !:> W was

due to undercutting of the field oxide.

39

The tests were non-destructive and did not stress the deVIces in any way.

Figures 3.5 a) and 3.5 b) are photographs of wafer type no.l and wafer type no.2,

respectively.

3.3. APPARATUS

3.3.1. Introduction

A schematic diagram of the apparatus used in the pulsed voltage expenments is shown

in Figure 3.6 .. Figure 3.7. shows a schematic of the apparatus used in the continuous

voltage expenments.

3.3.2. The wafer microprober

The wafer rmcroprober IS shown in photographs in Figure 3.8.. The wafer was

placed on a smooth metal chuck and held m place by vacuum suction. The chuck

could be electrically grounded if reqwred. Contact with the deVIces was made using a

set of adjustable probes with 20J.lm diameter tips. Electncal connections to and from

the probes were made using low-capacitance screened leads. A stereo optical

rmcroscope incorporated in the microprober enabled visual analysis to be made. The

magmfication capabilities of the microscope range from 50X to 3000X. Illurmnanon

was available through the lens itself and could be turned-off when not required.

In addition to the chuck incorporated in the rmcroprober, a heater chuck was bUilt.

This chuck used the heat generated by four 1 Q resistors, each capable of dissipating

4W. A current of lA was provided to these resistors usmg the mains voltage supply

40

ESD

POl.JER CIRCUI ~ --, AND SUPPLY

RELAY I I I I I I I I

~]:E=J ~=====il=jlll rHeated

Chuck

CURRENT THERMO-SOURCE STAT TIIERMOCOUPLE

FIGURE 3 6 Schemat 1 c of the apparatus used 1n the pulsed voltage expertments

RAMPED D.C. VOLTAGE SUPPLY

ELECTROMETER

MICROSCOPE

PROBE

SILIC ON WAFER

~

MOS

j_

Figure 3. 7. Diagram of the circuit used in continuous voltage stress investigations

FIGURE 3.8. Pho t ographs of the wafer rnicroprober

DC Power Supply

Rl 1 M Q R2 1.s k n Cl lOO pF

Rl

S - Two-pole relay DUT - nevtce Under Test

s R2

FIGURE 3 q Ctrcutt dtagram of~ pulse generator (after MIL-STD-883 C).

t 0 >

>

t sec ---

FIGURE 3.10. Schemat1.c tllustratton of the ~t voltage pulse

Applied voltage

o < .c::,. V 4;. 1 V

.c::,. t > 60 secs

.c::,.vl .~~-~~t~------------~--------

t (secs}

i9 3.11- Form of the continuous voltage stress as applied to

MOS structures.

and a step-down transformer. Temperature control was achieved through a

thermocouple and a ready-made thermostat. The thermostat was calibrated for the

heated chuck using a Noronix digital thermometer.

3.3.3. The pulsed voltage generator

Voltage pulses were generated using the circuit shown in Figure 3.9 .. This circuit is

based on the "human body" model pulse generatordescnbed by MIL-STD-883C [1].

A 100 pF capacitor was charged to the required voltage from a d.c. power supply. It

was then discharged through a 1.5 kQ resistor into the device under test (OUT). A

two-pole mercury-wetted relay was used to perform the change-over. This relay had

negligible contact bounce which was essential in the discharge crrcmt. All the

components were required to operate at high voltages (upto 1 kV). Hence the

capacitor (Cl) and resistor (R2) were designed and constructed in the laboratory usmg

thick-film techniques. The actual capacitance and resistance values measured for Cl

and R2 were 101.7 pF and 1.55 ill, respectively, (at a measuring frequency of 1 kHz

on the LCR meter described in section 3.4.5.). R2 has a parallel capacitance of less

than lQ-14 pF and a series inductance of less than l0-9 H. The parallel resistance of

C2 was in excess of 1015 n.

The pulse shape obtamed IS shown m Figure 3.10, for a discharge mto a low

capacitance oscilloscope probe. The resistance of the probe was 10 MQ, wh1le the

capacitance was 2 pF. The decay time of the pulse was governed by the impedance of

the probe. The risenme obtained is shown in the figure as being less than 500 ns.

More detailed analysis of the pulse nsetime has shown it to be less than 100 ns.

Limitations m accurately defimng the nsetime, were due to the madequacies of the

available oscilloscopes.

41

3.3.4. Continuous voltage generation

Continuous voltages were generated using a Ketthley 230 Programmable Voltage

Source. The instrument was programmed to generate a d.c. voltage for a fixed time

period (~t) after which the voltage was rrused by a fixed step value (~V). A ramped

voltage as shown in Figure 3.11 was obtained. The voltage source had a built in

current lirniter which was set to 2 mA, ehmmatmg the need to provide short-crrcuit

protection.

3.4. MEASUREMENTS

3.4.1. Introduction

Transistor propernes were measured using a curve-tracer (C-T) to monitor the current­

voltage characteristics of the deVIces. Capacitance and resistance propertres were

measured usmg a Wayne-Kerr 4210 LCR meter. I-V charactensncs were also studied

usmg the Kerthley 230 Voltage Source in circuit with the Keithley 617 Programmable

Electrometer. By mdividually ploning the I-V characteristics of selected transistors, 1t

was possible to confirm that the C-T technique and the manual techmques gave the

same results.

3.4.2. The curve-tracer

A Telequipment CT71 curve-tracer was used. Dram-source current (Ios)

measurements could be made down to 10 ~cm with 12 gate-source voltage (V as)

steps. Step amplitudes ranged from ±0.1 V to ±2 V. Drain-source voltages (V os)

down to a minimum of 0.1 V/cm, m both posrnve and negauve directions, could be

42

-- ------------------------------------,

made. An output power Iimiter was provided to protect sensitive deVIces from being

accidentally overstressed.

3.4.3. Voltage measurements

The Keithley 230 Voltage Source had a digital readout accurate to 4 decimal places at

±0.05%. For other voltage measurements the Keithley 617 Electrometer was used.

This instrument had a bmlt- in voltage source with an output ranging from -100 V to

+100 V in 50 m V steps. Agam, a digital readoutindicated voltage magmtudes.

The electrometer had a voltage measuring capability from 1 OJ.i V to 200 V on four

voltage ranges, with an accuracy of ±0 05%.

3.4.4. Current measurements

The Keithley 617 electrometer was used for all current measurements. Resolution

ranged from lQ-15 A to 20 mA over 11 voltage ranges. An accuracy of ±0.25% is

quoted for the 2 nA range.

Although a lQ-15 A resolution is claimed, measurements below J0-12 A levels were

not considered reliable because of problems with background nmse. The instrument

mcluded a "suppress" facility which enabled any steady background noise to be zeroed

before measurements were taken. This facility was also used to eliminate any self­

generated currents caused by fleXIng of the coaXIal cables.

3.4.5. The Wayne-Kerr LCR meter

43

Resistance and capacitance measurements were made usmg the Wayne-Kerr 4210

LCR meter. Resistance could be measured down to 0.01 n, with an accuracy of

±1.0%. The maximum resistance which could be measured was 109 n. Capacltance

could be measured down to 0.1 pF With a quoted accuracy of ±1.0%.

The LCR meter also mclude a "tnm" facility, Similar to the "suppress" factlity of the

electrometer. This enabled any stray resistances or capacitances to be eliminated from

the measurements. All experimental readings were taken at the 1 kHz measurement

frequency at a voltage level of250 m V.

3.4.6. Temperature

A Noronix N1D30 electronic thermometer With an accuracy of ±1 °C was used.

3.4.7. Capacitance-voltage (C-V) measurements

A useful parameter of an MOS capacitor is the variation of capacitance With applied

gate voltage. Measurements, in these experiments, were focussed on the relative shift

in the C-V curve caused by applied voltage stress. A stmple C-V meter, capable of

fulfilling these functions, was destgned and constructed.

A crrcuit diagram of the C-V meter is shown m Figure 3.12 .. The core of the crrcuit

was a Burr-Brown 3430 Electrometer Amphfier [5]. The amplifier had an open loop

gain of 100 dB and an input btas current of ±0.01 pA. The input impedance of the

device was 1014 n. Supply voltages of +15V and -15V were required. A 100 kQ

variable resistor between V+ and V-, connected to the trim input of the amphfier,

enabled the offset to be adjusted. The warm-up dnft for the 3430 was specified as 75

IJ.V over 15 minutes, and needed to be offset for very small voltage measurements. The

44

_/ VOLTAGE RAMP

I I I I

MOS

R

~

.---f:':- '--X ....

E~~c;~~~TER y

0

RECORDER

FIGURE J IZ,"' Cuc.u1t d1a.gram of the Capac1tance-Voltage meter.

R1 R2

R3

FIGURE 3 13 ~ Reststor network used m C-V meter

resistor R was required to be of the order of 1012 Q to obtain output voltages of the

order of 1 V, With input currents of about 10-12 A. Metal film resistors have the best

temperature stability and are accurate to 0.1 %, but were only avrulable m values upto

107 Q. Carbon resistors were available in values upto 1014 Q but have relanvely large

temperature coefficients (1000 to 5000 ppmt'C compared with 100 ppmt'C) and

tolerances of 1% to 10%. They also have comparatively poor long term stability. The

problem was overcome by using a resistor network for R, as shown in Figure 3.13.

R1 and R2 were metal film resistors where R1=100 MQ, and R2 = 10 MQ. R3 was a

1 OkQ carbon resistor. The overall resistance is given by,

[ R2 R2J R=Rl 1 +-+- 1011 n R3 RI "'

Unfortunately, R2 and R3 amplified the voltage noise and increased the offset by the

factor {(R2 + R3)/R3} = 103. Also, the loop gain of the crrcmt was reduced by the

factor {R3/(R2 + R3) = I0-3. However, the gain was sufficiently high to be able to

tolerate these factors.

1 mF decoupling capacitors were used at the pos!Ove and negative supply rruls.

A Burr-Brown 2800 MC connector was used to mount the amplifier because of the

high insulating properties of the teflon insulate pm-jacks. Winng in the crrcuit was

kept rigid and as short as possible to prevent extraneous voltage generation or stray

capacitance. Shielded coaxial cables were used for the input and output connections.

In order to rninilTilse self-generated cable nmse, a special low-noise cable was used.

Shielding for the circmt was provided by encasmg It in a grounded alulTilmum box.

45

The MOS gate oxide capaCitor was supplied With a slowly varying ramped input s1gnal

of the order of lQ-2 Hz. The current through the capacitor was converted to a voltage

and amplified by the electrometer. The output from the electrometer was fed into the

Y-axis of an X-Y plotter. The X-axis of the plotter was fed directly from the low

frequency signal source. Since the capacitance was directly proportional to the current

flowing through the MOS capacitor, a C-V plot was obtained.

Tests on the C-V meter showed that relative shifts and vanauons m C-V curves could

be satisfactonly observed. However, because of the input noise levels and the gam

factors of both the electrometer and the X-Y plotter, absolute values of capacitance

could not be determined.

3.5 EXPERIMENTAL PROCEDURE

3.5.1 Tests on the wafers

3.5.1.1. Homogeneity

The wafers were tested for variauons between device properties from chip-to-chip and

wafer-to-wafer. Transistor I-V charactenstics of two sets of devices on different chips

on a wafer were compared. The ch1ps were selected at different geographicallocauons

on the wafer. Compansons were then made between these chips and ch1ps on another

wafer. The gate leakage currents of MOS gate oxide capacitors were also compared

between the devices on these same chips.

Possible variauons in oxide breakdown strengths, w1th respect to the position of the

ch1p on the wafer and between wafers, were investigated. The on-chip gate oxide

capacitors were used m these tests.

46

The homogeneity tests showed that the variation of electrical characterisncs between

identical devices was not more than 5%. The oxide breakdown strength was found to

be consistent from chip-to-chip and between wafers.

It was concluded that the wafers in each process characterisation type were

homogeneous.

3.5.1.2. The effects of heat on the device properties

Wafers were tested to invesngate the affect of temperature on the devices. The 1-V

characteristics of devices situated at different posinons on the wafer were recorded.

The wafer was then heated to 70°C, 110°C, 150°C and 200°C and maintained at each

temperature for approximately 15 minutes. After each temperature stress, the deVIce

charactenstics were recorded at room temperature. Compansons with the 1-V

characteristics made before the wafer was heated, showed no changes.

This set of tests also showed that repeated heatmg and cooling did not affect the

electrical properties of the devices.

The oxide breakdown strengths of capacitors which had only been subJected to

thermal stress, were unaffected.

3 5.1.3. High temperature reverse bias (IITRB) screemng

A voltage of -12 V was applied to the gates of the devices at a temperature of 150°C,

for approximately 5 minutes. This had the effect of sweepmg ionic impurities ( e.g.

Na+, K+) out of the oxide.

47

The screen did not affect the I-V characteristics of the transistors or the R and C

properties of the capacitors. However, capacitors used in both the pulsed and the

continuous voltage experiments were liTRB screened in order to minimise any effects

due to ionic impurities.

3.5.2. Pulsed voltage stress experiments on E-mode NMOS

transistors

3.5.2.1. Prelinunary experiments

A number of E-mode NMOS transistors on wafer type no.!, were subJected to smgle

voltage pulses ranging from 50 V to 3 kV. The purpose of thts expenment was to

determine a suitable voltage range for a study of the oxtde breakdown mechanisms

under pulsed condittons. The tdeal voltage range was considered to be one in whtch a

steady increase m catastrophic failures would be observed as the applied voltage was

mcreased, without incurring 100% failures. The pulses were applied to the gate,

wh!le the substrate was grounded.

Voltages ranging between 50 V and 300 V were found to be most smtable for the

investigation. Beyond 300 V, more devtces showed catastrophic failures. Almost all

the devices tested were found to have been destroyed after application of a pulse of 1

kV.

The I-V characteristics of all the devices to be used in the expenments were then

recorded. It was necessary to ensure that devices damaged acctdentally, either in the

measuring process or by spunous voltage spikes ( ESD or otherwise ), were

identtfied. Therefore, any devtces which showed Ios vs. V os characteristics which

48

differed by more than 5% from that of known good device were excluded from the

experiments.

3.5.2.2. Temperature range

The selected temperature range was required to encompass the standard maximum

operating temperature for commercial devices (70°C) and military devices (!25°C).

Addinonal measurements at room temperature acted as a control group, while high

temperature effects were monitored with a group at 200°C. The five selected

temperatures were therefore, 25°C, 70°C, 110°C, 150°C and 200°C.

3.5.2.3. The number of devices

Each chip consists of devices of assorted dimensiOns and only 2 devices on any one

chip had the same dimensiOns. Therefore, It was decided to subject all devices on a

clup to the same voltage pulse for a given temperature. Hence, at 70°C, 176 devices

were subjected to 50 V, 176 to 100 V and so on. The number of devices used in the

experiment was 176 x 5 x 5 for the 5 voltages and the 5 temperatures. This amounted

to a total of approximately 4400 devices.

3.5.2.4. Experimental method

1. The charactensncs of all the transistors on 25 chips were recorded.

2. The wafer (No.1) was brought to room temperature (25°C).

3. All devices on a single clup were subjected to a smgle pulse of 50 V.

4. The experiment was repeated at lOO V, !50 V, 200 V and 250 V, on four different

chrps, all on the same wafer.

5. Steps 3 and 4 were repeated at 70°C, 110°C, 150°C and 200°C on different clups.

49

6. The wafer was returned to room temperature.

7. The device I-V characteristics were agrun recorded, emphasis bemg laid on those

devices which showed deVIations from their origmal charactenstics.

3.5.2.5. General

The experiments covered both the voltage and temperature sensitivity of E-mode

NMOS transistors to high voltage pulse condinons.

3.5.3. Pulsed voltage stress experiments on D-mode NMOS

transistors

Due to the large runount of data collected from the expenments on E-mode NMOS

transistors, the experiments on D-mode devices could be limited to the effects of high

voltage pulses.

28 devices were used in this expenment. They were subjected to single pulses of 50

V, 100 V, 150 V and 250 V. The 200 V stress was ommed after prelimmary

expenments, on devices selected at random, indJ.cated the trend of the voltage

dependence.

3.5.4. Pulsed voltage stress experiments on E-mode PMOS transistors

Invesngations into the pulsed voltage sensitivity of PMOS transistors also drew on the

data accumulated m E-mode NMOS transistor experiments. As with the D-mode

NMOS devices, expenments were limited to the voltage effects. A total of 42

transistors of various dimensions were used. All the devices were on the CMOS

process charactensanon wafer (type No.2).

50

Preliminary experiments on devices selected at random, showed that degradation

occurred with single pulses rangtng between 50 V and 1 k V. In order to mvestigate in

more detail the effect of the voltage pulse on I-V charactensncs, one group of 21

deVIces was subjected to 250 V, and a second group of 21 devices was subjected to

350 V pulses.

3.5.5. Pulsed voltage stress experiments on p-Si capacitors

p-Si (Enhancement-type) MOS capacitors on the NMOS process characterisation

wafers, were subjected to single positive and negative voltage pulses. Only one

capacitor was available on each chip. This meant that the numbers available for

experimentation were limited.

The capacitance and resistance of each MOS capacitor used in the experiment was

recorded, using the LCR meter. Groups of 10 devices were subjected to single

positive voltage pulses of 75 V, 150 V, 175 V and 200 V. Therr capacitances and

resistances were then remeasured.

Another 3 groups, each containing 10 devices, were subJected to single negative

polarity pulses of -50 V, -75 V and -100 V.

C-V curves of the devices were made after applicanon of the pulses.

Capacitors which had not been fiTRB screened were used for the bulk of the

experimentation. However, a small group of 30 capacitors which had been HTRB

screened were subjected to positive pulses.

51

3.5.6. Pulsed voltage stress experiments on n-Si capacitors

n-Si (D-type) MOS capacitors from wafer type No.l, were subjected to smgle voltage

pulses of both positive and neganve polanties. The pattern of the experiments was

similar to that for the p-Si capaCitors. All the capacitors were on the same wafer; none

of them had been subjected to HTRB screens.

3.5.7. Pulsed voltage stress experiments on n+-Si capacitors

n+-Si (E-type) MOS capacitors from the CMOS process characterisation wafers, were

subjected to single, positive and negative voltage pulses. The pattern of the

expenments was similar to that descnbed above for the other capacitor structures.

However, the voltage range was different. Positive pulses were at +30 V, +50 V and

+ 70 V; negative pulses were at- 30 V, -50 V and -60 V. The capacitors were selected

from both avrulable wafers of this type, and had not been HTRB screened.

3.5.8. Sequential pulsing of E-mode NMOS transistors

168 transistors from the wafer type No. I, were subjected to pulse sequences. The

pulses were applied at about 60 second intervals, by manually operanng the relay

control switch of the pulse generator.

The first experiment investigated the effect of increasing the number of pulses at

different stress voltages. Groups of 24 devices were each subjected to sequences of

25, 50 and 100 pulses. In each group, 8 devices were subjected to 50 V pulses, 8

devices to 150 V pulses, and 8 devices to 250 V pulses. The device I-V characteristics

were recorded at the end of each complete sequence. The group subjected to 25

52

pulses, had device charactenstics monitored after 8 pulses, 10 pulses, 15 pulses and

20 pulses in order to observe trends.

A second experiment was carried on 4 groups of 24 transistors. These devices were

subjected to a constant number of pulses, while the applied voltage was varied from

group to group. 25 pulses were apphed at 350 V, 525 V, 700 V and 1 kV. The

device I-V charactenstics were recorded at the end of each sequence.

3.5.9. Sequential pulsing of p-Si capacitors

2 groups of 10 p-Si capacitors from wafer type no.1, were subjected to pulse

sequences. All the capacitors had been subjected to HTRB screens. The purpose of

the expenment was to invesngate the variations in capacitance and resistance after each

set of pulses. One group of devices was stressed at 150 V and a second group at 200

V. The capacitance and resistance values were measured before application of the

pulse. A single pulse was applied and the C and R values were measured again. After

that, C and R values were measured after each set 5 pulses.

The group stressed at 150 V was subjected to 3 sets of 5 pulses, totalling 15 pulses in

all. The group at 200 V was subjected to 5 sets of 5 pulses, totalling 25 pulses.

3.5.10. Continuous voltage stress experiments on p-Si capacitors

3 5.10.1. Temperature sensitivity of the oxide breakdown voltages

The oxide breakdown threshold as a functiOn of the applied temperature, was

mvestigated at 25°C, 75°C, l25°C, 150°C and 200°C, under continuous voltage

conditions.

53

25 capac1tors from wafer type No.1, were used in th1s experiment, in 5 groups of 5.

Each group was subjected to a d.c. voltage, which was gradually increased from zero

volts unnl breakdown, at a specific temperature. The voltages were raised in 1 V steps

of 180 seconds duration each. Breakdown was defined at the voltage at which an

extremely rapid increase in leakage current was observed. This was confirmed by C

and R measurements made after completton of the experiment.

All the capacitors had been HTRB screened.

3.5.10.2. Gate leakage current experiments

2 groups of 5 devices from wafer type No.1, were subjected to both pos1tive and

negative polanty voltage stress. The gate leakage current was measured using the

Keithley 617 Electrometer. One group of devices was stressed from zero volts to the

posltlve voltage breakdown threshold m steps of 1 V. Leakage current measurements

were made at each voltage step. The second group of deV1ces was stressed from zero

volts to the negauve breakdown threshold in steps of 1 V. Leakage current

measurements were made as before.

The C-V curves of deVlces subjected to constant voltage stress in the vicinity of the

breakdown threshold were recorded. The curves were made after application of

conunuous voltages of 28 V to SOY in the pos1tive direction, and 26 V to 38 V in the

negauve direcuon. The stress levels were at 2 V intervals (e.g. 26 V, 28 V, 30 V, 32

V etc.) on different capacitors.

All the capacitors had been subJected to HTRB screens.

54

3.5.11. Continuous voltage stress experiments on n-Si capacitors

2 groups of 5 devices from wafer type No. I, were subjected to constant apphed

voltages. The two groups were stressed from zero volts to the positive and negative

breakdown thresholds as descnbed m the previous section. All devices had been

HTRB screened.

3.5.12. Continuous stress experiments on n+-Si capacitors

The experiments used 2 groups of 5 devices each from wafer type No.2. All devices

had been HTRB screened. The devices were stressed from zero volts in both the

pos!tlve and negative directions as described in secnon 3.5.10 ..

3.6. SUMMARY

1. Two wafer types were used in these experiments. One wafer type charactensed an

NMOS fabncauon process, and the other characterised a CMOS fabrication

process. Each wafer contained MOS transistors and MOS gate oxide capacitors.

2. The wafers were tested for consistency and homogeneity from chip-to-chip and

wafer-to-wafer.

3. The apparatus and the expenmental procedure has been descnbed. Table 3.1

summarises the experiments, and the associated sections m this chapter.

55

Table 3.1

Summary of experiments described in this chapter. V indicates experiments on voltage dependence, T indicates experunents on temperature dependence.

Device Type Single Pulsed Sequennal Pulsed Contmuous Voltages Voltages Voltages

V T V T V T

E-mode NMOST 3.5.2 3 5.2 3.5.8

D-mode NMOST 3.5.3

E-mode PMOST 3.5.4

p-Si Capacitors 3.5.5 3.5.9 3.5.10.2 3.5.10.

n-S1 Capaotors 3 5.6 3.5 11

n+-S1 Capacitors 3.5.7 3.5.12

3.7. REFERENCES

1. Military Standard. Test metlwds and procedures for microelectronics; MIL-STD-

883C- U.S. Department ofDefense, August 1983.

2. GREENWOOD C.J., M102 -Small geometry process characterzsanon wafer -

Techmcal report A11/97/80, Plessey Research (Caswell) Ltd., 1980.

3. ARMSTRONG N.,przvate communication, 1984.

4. ARMSTRONG N.,przvate communication, 1985.

56

5. Product Data Book.- Burr-Brown Research Corporanon, 1982.

57

CHAPTER 4

RESULTS

4.1. INTRODUCTION

The three main sections in this chapter present the results of the expenments

conducted. Single pulse conditions, pulse sequences and continuous voltage

conditions make up the main sections. Experiments on different device structures are

described in subsections

4.2 PULSED VOLT AGE STRESS EXPERIMENTS

4.2.1 E-mode NMOS transistors

4.2.1.1. Characteristics

A companson was made of the Ios vs. Vos characteristics before and after

application of a single high voltage pulse. It was determined that these characteristics

could be classified rnto one of the following five categones.

1) Category 1 - no change. All parameters remain unaffected. The transistor

charactensncs shown in Figure 4.1 was observed.

Ii) Category 2 - degradation. The charactensocs of a degraded deVIce with the same

dimensions as the one used m F1gure 4.1., IS shown in Figure 4.2.. A

compmson between the two charactenstics shows that Significant degradation has

58

Ios f 40 (mAl

35

30

25

20

1·5

1 0 ~

Vcs=2V

05 \{; -1V ./'s-

Vcs=OV

2 3 4 5 6 7 8 9

\bs(Vl

FIGURE4;.1.Category 1, 'No Change' Ios VS V05 characterostoc

40

I os I (mAl 35

30

25

20

1 5

10

05

-Vos(V)

' . FIGURE+..l. Category 2 Oegradatoon

t BO V ~4V

!"" Vcs="N Ios 70

()J A l 60 VGs=SV I

50 -----.._ VGS =2 V

40

30 /is =1V

20 VGs =7V \l;s=01

10

0 -Vr,s=8V

2 3 4 5 6 8 9 - Vos(V)

FIGURE +.3 .Category 3. Degradatoon woth negatove gm at hogh Vgs.

Ios (mAl

i Ios

(mAl

1 20

1 5 V65 =1V per step

10

os 0

- 0 5

-1 0

-1 5

FIGURl4- 4- Category 4, ResJstJve character~stJcs

1 0

08

06

04

0·2

0 1

23456789

-Vos (VI

FIGURE +S ,Category s; Catastrophic FoJ!ure

,.. "' 0

" ~ u J: u < w ;; V> w u > w 0

"'

FIG4.6 VOLTAGE DEPENDENCE OF DEVICE CHARACTERISTICS

90~-----------------------------------------------,

80

" 60

" I

•o I I

JO I .;

20

" --- -fl -· G---- -----a------- --o-------""'-1?==------<> 0 '

•o 60 80 100 120 140 160 180 200 220 240 260 VOLTS

Legend !:J. •0 CMU't

X~'!.!.!!!"--0 ~·.!'!"·~·[

FIG 4 7 TEMPERATURE DEPENDENCE OF DEVICE CHARACTERISTICS

'0~------------------------------------------------, "-~-

60 --~--

~ so 0

~ u J: "

j ;;

--""----'*"------

Vl 30 _!:-______ _,__ __ _

~ -~----~r-----------r w 0 X 20

" !3-------- --9----- --"3·-------G-----------

o,~,----.-,----~,,~--~.-,----.~,o~--~,~,----~ .. o~---.. -,----~ .. ~0--~200 TEMPERATURE, DEG C

Legend !:J. •o c~••tc X 1!.!.£!.·~---0 ~·.!'~-·~·-(~

FIG.4. 8 DIMENSIONAL DEPENDENCE OF 'NO CHANGE' CATEGORY, w=102 9 f-'m

»r---------------------------------------------,

w

" z 25 < r u 0

~ 20 z 'i 0 J: V> " V> w u > w 0 "

"

0 20 40 50 60 70

CHANNEL LENGTH J.Jm 90 '"

Legend !::. AT 150 VOLTS

A ~00 VOLTS

occurred. Measurements of the gate-drain resistance <Roo = 65 ill) and the gate­

source resistance (Ros = 56 ill), indicate a small leakage current through the

oxide. Both the saturation and the non-saturation values of the dram-source

conductance, gds(sat) and gds(non-sat) have decreased. The extent of these changes

may vary from a few% to almost 75%.

iii) Category 3 - degradation with negauve gm at htgh V GS· The characteristics

shown in Figure 4.3. exhibit a degradation with a drain-source current whtch

begms to decrease as V GS is increased beyond 3 V.

tv) Category 4 - resistive characteristics. These charactenstics as shown in Figure

4.4., are another form of degradation. When the drain and source contacts are

mterchanged, the characterisucs resume degradation type effects as m Category 2

(Figure 4.2.). R00 = 0.31 ill and is very much lower than Ros = 16.3 ill. The

gate-drain current, Ioo• measured with the gate at +4 V and the dram at 0 V, was

12.5 mA. The gate-source current, I, under mmlar conditions was 1.0 mA.

v) Category 5 - catastrophic failure. The charactensucs are shown in Figure 4.5 ..

I os is approximately zero, for all values of V GS• and for all V DS• up to avalanche

breakdown.

4.2.1.2. Device sensmvay to the magnitude of the pulsed voltage

Ftgure 4.6. shows the percentage distrtbuuons of devtces showing "no change",

"degradauon" and "catastrophic fatlure" charactenstics, as a function of the applied

voltage. It is seen, that at 50 V, over 70% of the devtces were not affected by the

stress. This number steadily decreased, unttl at 250 V, only about 7% of the devices

showed no changes. The degradation characteristics increases over the same range,

59

from just over 20% at 50 V, to about 80% at 250 V. The percentage number of

deVIces exhibiting catastrophic failures increase very gradually, from 5% at 50 V, to

around 12% at 250 V.

4.2.1.3. Temperature sensitivity of pulsed voltage damage

The results of the temperature experiments on E-mode NMOS transistors are

summansed in Figure 4.7 .. The curves rndicate the percentage number of devtces

showing damage as a function of temperature.

4.2.1.4. The affect of the transistor gate dimensions on the degradation

charactensncs

The E-mode transistors were of many different dimensions. It was , therefore,

possible to make an analysis of the relatiOnship between the gate size and the

sensitivity of the deVIces to the stress. However, at very small dimensions ( < 5 J.llil

), factors extraneous to the size of the gate may influence the results. Lateral diffusion

of the dram/source and field oxide undercutting of the gate area, will affect the

electrical properties of the device. These effects are expected to be concentrated at the

gate-drain and the gate-source regions. Therefore, in Figure 4.8., the percentage

number of devices showrng "no change" is plotted as a function of channel length for

a specific gate width. The gate width of 102.9 ~m, and the gate lengths of 6.3, 10.2,

20.7, and 102.9 ~m, ensure that the degradation trends observed are solely due to the

effects of the gate area. The plots show distribuuons for single pulses of 150 V and

200V.

4.2.2. D-mode NMOS transistors

60

The characteristics of an undamaged deVIce are shown in Figures 4.9. and 4.10. for

V 05>0 and V os<O respectively. The charactenstics observed after application of a

single 100 V pulse are shown in Figures 4.11 and 4.12 for Vos>O and Vos<O

respectively.

The characteristics for V 05>0 show sirmlar degradanon to those exhtbtted byE-mode

NMOS devices. A difference does exist in gds(sat) which shows an mcrease,

compared to the decrease observed in damaged E-mode transistors.

For V os<O, the charactenstics are quite chfferent. As V GS becomes more negative, tt

IS seen that Ins first decreases for a given V ns as for an undamaged device, but an

increase in channel conductance (gds) is observed. As gds gets more negative, Ins

increases at low values ofVns (<2 V). At higher Vns values, between 2 V and 10 V,

Ins remams almost constant.

4.2.3. E-mode PMOS transistors

The characteristics of an undamaged device is shown in Figure 4.13 .. The

characteristics obtained after application of a 350 V pulse is shown in Figure 4.14 ..

The observed degradation is idenncal to that shown by E-mode NMOS tranststors.

4.2.4. MOS capacitor structures

The results of the expenments on the three capacitor structures are summansed in

Table 4.1.. These devices had not been subjected to HTRB screens.

The table shows the magnitude of the applied pulse voltage, and typical values of R

and C, before and after stress was applied. R and C values were measured at 1 kHz

61

1os

t

VOS

V : IV/step ~· t

1V/d1V

FIGURJ: 4-,q r-v characterl.StLcs of a D-mode tranststor appltcatLon of an ESD pulse, VGS > 0.

before

1os t 0.2 mA/dtV

VGS • - 1 V/step

-v05 1 V/dt.v

FIGUR£4.10 I-V charactertsttcs of a D-mode NMOS transutor before appltcatton of an ESO pulse, VGS < 0

1 mA/dt.v

FIGURE+ 11

1os i 0 2 mA/d1V

0

t VGS "' lV/step

_____.. v05 1V/d1V

I-V charactertsttcs of a D-mode NMOS trans1.stor after apph.cat1.on of an ESD pulse, VGS > 0

v~,

QV

-lV

-2V

-3V

v05

lV/dtv

I-V Charactertsttcs of a D-mode NMOS tranststor after appltcatton of an ESD pulse, VGS < 0

V ...

v05

• - lV/d~v.

lV/step

IDS "" 2 mA/dtv

FIGURE4.a. I-V charactenst~cs of an E-mode PMJS trans~stor before appl~catton of an ESD pulse

v05

.. - lV/d~v

V .. - lV/st.e <U

2 mA/d1V

FIGURE4.l+. I-V charactensttcs of an E-mode PMOS translStor after apphcatton of an ESD pulse @ 1150V.

RESULTS OF ESD EXPERIMENTS USING POSITIVE AND NEGATIVE

VOLTAGE PULSES ON E-TYPE AND D-TYPE NMOS AND E-TYPE DMOS CAPACITORS

(NO HTRB SCREENING)

CAPACITOR NO: OF APPLIED TYPICAL TYPICAL TYPE DEVICES VOLTAGE CAPACITANCE RESISTANCE COMMENTS

(V) (pF) (k!l)

before after before after

E-TYPE NMOS 10 +1SO 20.0 20.0 0/C 0/C O.K.

E-TYPE NMOS 10 +200 20.0 16.S 0/C 1SO BREAKDOWN

E-TYPE NMOS 10 -7SV 20.0 20.0 0/C 0/C O.K.

E-TYPE NMOS 10 -100V 20.0 17.0 0/C 6S BREAKDOWN

D-TYPE NMOS 10 +1SO 13.0 13.0 0/C 0/C O.K.

D-TYPE NMOS 10 +17S 13.0 9.0 0/C so BREAKDOWN

D-TYPE NMOS 10 -7SV 13.0 l3 .0 0/C 0/C O.K.

D-TYPE NMOS 10 -100V 13.0 9.0 0/C so BREAKDOWN

E-TYPE PMOS 10 +SOV 1l.S 1l.S 0/C 0/C O.K.

E-TYPE PMOS 10 +7SV 1l.S 7.0 0/C 7S BREAKDOWN

E-TYPE PMOS 10 -sov 11.0 11.0 0/C 0/C O.K.

E-TYPE PMOS 10 -60V 1l.S 6.0 0/C 2.16M BREAKDOWN

TABLE 4-.1

0

C.apKltC\CI

(.arb ~,~t~HI)

FIGURE-4-.15" C-V curve on E-mode p-Sl MOS capacltor, before appl1cat1on of an ESD pulse

_,

\ \

"

l C.&pac:~tance

(arb unHs)

FIGURE4.U,. C-V curve of E-mode p-St MOS capacltor, after appl1cat1on of a 150 V ESD pulse

t~V

F1gure4.11

Ftqure 4·18'

C~pdClt.tnce

c-V curve of an Undamaged E-Mode n-Sl MOS Capacttor

C-V Curve of an E-ModP n-St Capac1tor after appllcatton

of an ESD Pulse of + SOV

Capactt:.anc;.e

ABSOLUTE NUMBER Of' DEVICES SHOWING CHARACTERISTICS DEPICTED.

AS A f'1JNCTION Of' TilE NUMOPR Of' AI"Pl,JEO ESn PUlSES.

ANO TilE APPt I EO ESD VOI TAGE

OlTS PUl.SES CATASTROPUIC REDUCED NO CIIANG PArt ORES CI!ARACTERISTIC

so 2S 0 1 7

so 0 ] s

lOO 0 8 0

I 150 2S 1 7 0

50 0 s I J

lOO 1 7 i 0

200 25 1 i

s I 2 : I so 1 7 0

I lOO ! 7 1 0

TABLE+ 2

11H:: EFFECT OF INC'"REASING TilE APPLIED ESD VOlTAGE AT A CONSTANT 25 PUlSES

ABSOlUTE NUMBER OF DEVICES.

EXIHBJTJNG THE GIVEN CHARACTERISTICS ARE SIIOWN

lvoLrs <'ArASTROPruc I r I NEAR r-v I REDUCED

I FAILURES I CllARACTERISTJCS CllARACTERISTIC

! I 350 10 i 12 I

'>25 16 I 2

I 6 !

720 16 i 7 I

I kV 24 I 0 0

TABLE+- 3.

TABLE44

Results for sequenually pulsed p-St capacitors

Pulsed ResiStance (kn)

No. of Devtces No. of Pulses Voltage

M I 5 10 15 20 25

10 !50 o/c o/c o/c O/C - -

10 200 !50 100 70 55 50 48

on the LCR meter. However, some capacitors showed resistances as low as 1 kQ,

with an associated capacitance of 0 pF, after damage. The upper lirmt of resistance

after damage was around 300 ill for devices on wafer type No.l. Some devices on

wafer type No.2 had resistances as high as 1 MQ.

The positive voltage breakdown threshold of p-Si (E-type NMOS) Capacitors was

+200 V, while the negative voltage threshold was - 100 V. With n-Si (D-type

NMOS) capacitors, the breakdown thresholds were +175 V and -100 V. It is

observed that the neganve voltage threshold is not affected by the type of deVIce, but

the posinve threshold is dependent on the dopant at the Si surface. The n+-Si (E-type

PMOS) capacitors showed almost no polarity dependence.

Figures 4.15. and 4.16 show two C-V curves made before and after applicanon of a

+ 150 V pulse to a p-Si capacitor. There is very little variation between the curves.

The deVIce itself showed no decrease m parallel resistance, indicating that no damage

had occurred. Figures 4.17 and 4.18 show two C-V curves made before and after

applying a +50 V pulse to an n+-Si capacitor. A Significant shift of the capacitance

minima, m the negative voltage direction, is observed.

4.3 SEQUENTIAL PULSING

4.3.1. E-mode NMOS transistors

The results of sequential pulsing experiments on E-mode NMOS transistors are

presented in Tables 4.2 and 4.3.. Table 4.2 shows the effect of mcreasing the

number of pulses at different voltages. The absolute number of devices with

characterisncs in each category are given. Table 4.3. shows the effect of increasmg

62

the applied voltage for a fixed number of pulses. Again, the absolute number of

devices, exhibiting characteristics in each category, is given m the table.

4.3.2. p-Si MOS capacitors

The results for p-Si MOS capacitors are presented in Table 4.4 .. R and C values are

shown, after pulsed voltage stresses of 150 V and 200 V, as a function of the number

of applied pulses. Resistances are observed to decrease as the number of pulses IS

increased.

4.4. CONTINUOUS VOLTAGE STRESS EXPERIMENTS

4.4.1. p-Si capacitors (E-mode NMOS)

4.4.1.1. Gate oXIde leakage currents

The gate OXIde leakage current (IG!eak) has been plotted as a function of the applied

voltage in Figute 4.19 .. It is important to note the rate at which Iateak varies with

voltage, as a function of polarity. The I-V curve is asymmetrical for p-Si capacitors.

A lower Iateak is observed for positive voltages compared with negative voltages.

A C-V curve made after a +36 V stress is shown in Figure 4.20 .. Figure 4.21.

shows a C-V curve of a device stressed at -30 V. Figure 4.22 shows how the

capacitance rmnima changes (~C) as a function of a positive voltage stress ranging

from +26 V to +48 V.

4.4.1.2. Temperantre effects

63

40

30

20

lO

-SO -40 -30 -20 -10 lO 20 30 40 ~

FIGURE 4. l'l .

-10

-20

-30

-40

-SO

-60

V (Volts)

Graph of the oxide leakage current (IG 1

k ) as a function of the applied stress ea

voltage for an E-mode p-Si MOS capacitor

-- Uur

FIG.4.20 FIG.4.21

FIGURE 4-.lO. C-V curve of E-mode p-St. MOS capacuor after conttnuous posttt.ve voltage stresSI.ng 3 e + )6 v

FIGURE 4-~ll. C-V curve of E-mode p-St MOS c:apac1tor after contt.nuous negatt.ve voltage stresst.ng at - 30 V

~c

(arb t unLt•l

2.0

1.5 •

1.0

0.5

0

26 30 34 38 42 46

Stress Voltage (Volts)

t:.c • c - c stress

BREAKDOWN lTQLTAGE

(V)

FICURE +.:U

20 40

Graph show1.ng the chQ!lCje 1.0 C-V curve mt.nl.ma (!::.V ) as a funct1on of the stress voltage for an E-mo~e p-Sl. MOS capac1.tor

60 80 lOO 120 140 160 180 200

FIGURE +.l.3 TI1e temperature dependence of the oxtde breakdown threshold under cont1.nuous voltage stress for MOS capacttors.

FIGURE 4.14

-50 -40 -30 -20 -10

40

30

20

10

10 20 30 40 50

-10

-20

-30

-40

-50

-60

-V

(Volts)

Graph of the oxide leakage current (I 1

ak ) as a function of the applied stress voltage for a

10 e P·mo<ie

n-Si MOS capacitor

40

30

20

1 0

-50 -40 -30 - 0 -10 10 20 30 40 50

-10 -V

-2 0 (Volts)

-3 0

-4 0

-50

-6 0

FIGURE 4.25. Graph of 0x1de Leakage Current (16! leak) as a Funct10n + of the Appl~ed Stress Voltage for an E-Mode n-S~ capac~tor

The effect of temperature on the gate oxide breakdown strength of a p-Si capaCitor is

shown in Figure 4.23 .. The breakdown voltage threshold decreases from +36 V at

room temperature (25°C) to +28 V at 200°C.

4.4.2. n-Si capacitors (D-mode NMOS)

Figure 4.24. shows the vanation of IGJeak with voltage for an n-Si capacitor. The

curve is snll asymmetrical, but the disparity between ~{}leak at positive and negative

voltages is not as large as that observed with p-Si capacitors.

4.4.3. D+·Si capacitors (E-mode PMOS)

Figure 4.25. shows IGieak as a function of applied voltage for an n+-Si capacitor.

The curve IS seen to be fairly symmetrical about the origm, for positive and negative

voltages and currents.

4.5 SUMMARY

1. The results of single pulse voltage stress expenments, pulse sequence experiments

and continuous voltage experiments have been presented. E-mode and D-mode

NMOS, E-mode PMOS transistors, p-Si, n-Si and n+-Si capacitors, have been

reported m separate subsections, for each expenmental condinon.

2. The pulsed voltage expenments on E-mode NMOS transistors, have been

evaluated by considering the percentage distributiOns of the device 1-V

charactenstics, after pulsmg. The characteristics are summarised in three

categories, a) no change, b) degraded, c) catastrophic farlure.

64

3. The distributions indicate that the pulsed breakdown IS voltage sensitive, but is not

affected by temperature. It IS also dependent on the surface area of the gate ox1de.

4. D-mode NMOS charactenstics when degraded were observed to be different to

those of degraded E-mode NMOS transistors.

5. E-mode PMOS transistors showed degradation identical to that of E-mode NMOS

transistors.

6. The pulsed voltage breakdown of capacitor structures was shown to be polarity

dependent. The breakdown threshold is higher for pos1tive voltages. The dopant

concentration of the Si surface influences breakdown, more n-type surfaces

showtng lower breakdown thresholds.

7. Sequential pulsing was found to increase the degradation observed in both

transistors and capacitors.

8. Constant applied voltage stress on capacitor structures, showed that breakdown

was dependent on the polarity of the stress voltage and the dopant concentration at

the Si surface. More n- type surfaces showed a higher leakage current, while

devices were more affected by negative voltages.

65

CHAPTER 5

DISCUSSION

5.1. INTRODUCTION

In this chapter, an analysis is made of the experimental results. The mechamsms and

modellmg of oxide breakdown are considered m Chapter 6.

5.2. DAMAGE IN MOS STRUCTURES

The 1-V characteristics indicate that damage in the transistors manifests itself as

various levels of degradation.; i.e. Ins decreases for a given Vns· Degradation can

range from minor ( 1% of the undamaged Ins ), to major ( Ins=O ), Implying

catastrophic failure.

In E-mode NMOS transistors, the decrease in Ins. and the corresponding decrease in

gds, indicates that the n-type channel had not reached the level of mvers10n expected in

an undamaged device. This IS due to the formation of a leakage path through the gate

oXIde, which prevents electrons from accumulating at the semiconductor surface under

positive bias conditions.

In D-mode NMOS transistors, the leakage path prevents the surface from depleung

under negauve b1as conditions. This is confmned by the mcrease in gds, observed m

these devices, after degradauon

66

In E-mode PMOS transistors, the inversion channel is affected by ox1de leakage.

Hence degradation characteristics, of the same land as those obtamed with E-mode

NMOS transistors, are observed.

R and C measurements on damaged MOS capacitors, showed that the leakage

resistance dropped by orders of magmtude, =1014 ohms to 106 ohms. the capacitance

was observed to decrease by various degrees, ranging from 1% to 100%. Oxide

breakdown is, therefore, comrrmed to have taken place.

Detailed failure analysis of the damaged devices was not performed. This would have

involved secnoning the wafer and dissecting the chips to s1zes suitable to surface

analysis equipment. As a result, other devices on the wafers, which were required for

further experiments, would have been destroyed.

5.3 PULSED VOLTAGE STRESS EXPERIMENTS

5.3.1. E-mode NMOS transistors

5.3.1.1. Analysis ofi-V charactensncs- voltage effects

Category 1 - The unchanged characterisucs mdicate that the oxide has not been

damaged. As the magnitude of the pulsed voltage increases, the number of

undamaged devices decreases, from 70% at 50 V to 10% at 250 V. A strong voltage

dependence of the damage mechanism is therefore indicated.

Category 2 - This category of damage has serious 1mplicanons in the applicattons of

MOS devices. The characterisncs show such devices could snll appear as operational

transistors, espec1ally in digital circuitry. They form part of the "walking wounded"

67

which could conmbute to latent failures. Faliures of this type are extremely hazardous

since they occur during the working life of a device. Tins IS supported by the results

of experiments with sequential pulses.

Category 3 - In this case, as V GS increases beyond a certain voltage, Ins begins to

decrease for a given V DS· This effect is the result of deep depleoon taking place at the

semiconductor surface; i.e. when the depletion layer width becomes wider than in

thermal equilibrium [1]. The oxide IS once again damaged and becomes a weak

conductor; however, the leakage resistance is less than in the previous category.

Consequently, a larger number of electrons are conducted out of the semiconductor

surface, through the oxide. The number of ionised acceptors (N A) at the surface

increases, in order to support charge neutrality, and this causes the depletion layer to

widen. The result is an increase in the threshold voltage of the transistor, since [2] -

[4],

The transistor mutual transconductance is given by [2] - [ 4],

.,. _ LllD sat "m sat- D. y

GS

and,

The symbols have therr usual meanings.

68

......... Eq(S.l)

......... Eq(5.2)

......... Eq(5.3)

Therefore, as VT becomes greater than V GS• gmsat goes neganve, giving rise to the

characterisncs observed m this category. At acceptor concentrations of N A= 1017 cm·

3, a VT of"' 5 V can be expected [2].

Category 4 - The resistive characteristics are another form of degradation. The

restoranon of standard I-V charactenstics when the source and dram contacts to the er are reversed, indicates that the oxide leakage path is between gate and drain. Drain

lateral diffusion under the gate is approXImately 0.5 IJ.m and oxide breakdown can take

place directly between the gate and drain. The er measures I os at the drain terminal,

and, Will only see the gate mude resistance as current flows from the gate to the drain.

Measurements using separate multimeters at the drain and the source of a biased

transistor, have confirmed that this IS true. Since oxide breakdown between the gate

and source/dram is not sigruflcantly different from breakdown directly over the

channel, all three types of breakdown descnbed by categories 2 to 4 Will be classified

as degradation. This degradation damage, in transistors can be compared to the MOS

capacitor damage, where the leakage resistance ranges from 50 kQ to 1 MQ, with a

capacitance which is snll significant ( =50% of its original value ).

Category 5 - These characteristics are the result of senous oXIde breakdown. The

extent of the damage prevents an inversion layer from formmg at any V GS; the device

IS, therefore, inoperative. A comparison With MOS capacitors can be made, where the

measured resistance ranges from 100 Q to 1 kQ and the gate capacitance is zero.

5 3 1.2. Temperature effects on oxide breakdown

No distmct trend was observed for the temperature dependence of any of the

categories. It is therefore concluded, that the pulsed voltage breakdown sensitivity of

MOS devices is temperature independent.

69

Other workers have observed an ESD sensitivity for NMOS LSI deVIces which IS

affected by temperature [5]. The cause of failure was traced to a diode in the

protecuon circuit which was influenced by the applied temperature. Relating this

finding with the results for discrete MOS structures, as descnbed in this thesis,

implies that it is possible for input protecuon circuitry to introduce a temperature

dependence.

5.3.1.3. Dituensional dependence of oxide breakdown

The increase in the percentage number of deVIces showing degradauon as the gate area

IS increased, supports the results of Welters et a! [6], for continuous voltage

breakdown ( N.B. The results on dimensional dependence presented in this thesis

were first published in August 1984 [7] ).

The presence of defects in an oxide in the form of impunties or dangling Si or 0

bonds, will weaken the dielectric strength of the oxide [8][9]. Such defects have been

termed intrinsic. Extrinsic defects are mtroduced in the manufacturing process, and

take the form of pinholes through the oxide, and, surface non-uniformities at the

interfaces. The density of such defects is expected to be very small (=1 cm-2) m a

production assessment wafer. A large sample size, such as that used in the NMOS

transistor expenments, rnininuses the possibility of extrinsic defects influencing the

results.

It is reasonable to assume that intrinsic defects are randomly distributed across the

oxide area, A, which IS defined by the gate width and the gate length. Welters

assumes that the probability that m defects, failing at or below a field strength F, being

present m a certain area is given by the Po1sson distribution.

70

The probabtlity of having one or more defects in an oxide failing at a field

strength F, is given by,

P(F) = 1 - exp { -A.D(F)} .......... Eq(5 4)

Therefore, as A increases, P(F) gets larger. Eq(5.4) holds for large gate areas

and uniform electric fields. The effects of source/drain lateral diffusion and field

oxide undercutting which will be found in very small dimension devices, are not

included m the equanon.

The gate to drain/source breakdown would be expected to become more

sigruficant as the ratio of the effective channel length to the length of the lateral

diffuswn gets smaller. Figure 5.1 shows the % number of devtces which

exhibited gate-source or gate-drain breakdown as a function of the channel

length at a constant gate wtdth of 3.2 ~m. The devices were all stressed at 200

V. Hence, it can be seen that as the length approaches D.L( =0.5 ~m) the number

of breakdowns mcreases. The implications of thts result with respect to very

small devices are discussed in Appendix 3.

5.3.2. D-mode NMOS transistors

The degradation charactensncs of deplenon-mode devices were

different to those of the E-mode NMOS transistors because of the Implanted

mversion layer. The higher gds sat observed in damaged devices with

neganve V GS• mdicates that the surface was not depleted to the extent of

an undamaged devtce. As V GS is made more neganve, a constant gds

is observed, wl!h I os increasmg in the posttive direcnon. This imphes

71

FIG5. 1 % DEVICES SHOWING GATE TO SOURCE/DRAIN DAMAGE AT 200 V

80~-------------------------------------------.

V1 w u

70

60

50

> 40 w 0

~

30

20

10

w=3.2pm

o+----r--~----r---,----r---,----~--,---~---4 2 3 4 5 6 7 8 9 10 11

CHANNEL LENGTH, um

that the increase in jV GS/ does not affect the inversion layer, but instead begins to aid

conduction through the oxide.

However, there is the possibility that if the point of breakdown 1s closer to the source,

then a pos1ttve V os will begin to cause pmch-off in the inversion layer at low /V GS/·

This is because the lateral voltage in the channel, 1.e. V os eff• is greater than V os

because of the added effect of V GS· I os. therefore, mcreases as V os goes from 0 V,

and then decreases as pinch-off sets in. The current, preferring the path of lower

resistance, travels from the source contact to the gate. For h1gher V GS• the circmt

becomes a current diVIder, and, a steady Ins w11l be observed. From the type of I-V

characteristic observed, it IS possible to identify the possible location of the damage;

i.e. whether damage is closer to the source or the drain.

The experiments on a small sample of D-mode NMOS transistors ( 28 devices ),

showed that the extent of the degradanon mcreased as the magnitude of the applied

voltage pulse was increased. All deVIces which were stressed showed degradation.

5.3.3. D-mode PMOS transistors

D-mode PMOS transistors were not available for experimentation. However, It IS

expected that the shape of the I-V charactenstics after damage, will be similar to that of

the D-mode NMOS transistors. The only consideration here, IS that the operatmg

voltage polanty of a PMOS transistor, is opposite to that of the equivalent NMOS

device. Electrons in PMOS devices will flow in the opposite direction to those m

NMOS devices, but this should have no significant effect on the characterisncs

obtained.

5.3.5. MOS capacitor structures

72

The results for the capacitor structures have been related to the transistor I-V

charactenstics in Section 5.3 ..

The breakdown threshold for negative voltage pulses, i.e. when the n+ polysilicon

gate was the inJecting electrode, was not affected by the dopant concentration at the

silicon surface. However, positive voltage breakdown thresholds were significantly

affected by the type of silicon surface. As the surface became more n-type, the

disparity between the positive and negative breakdown thresholds becomes less. This

indicates that the breakdown threshold IS mfluenced by the electrode which injects

electrons into the Si Oz. Charge injection and Its influence on breakdown has been

discussed by other workers [10][11], although it is a relatively new concept with

regard to the mechanism of oxide breakdown [12]. Earlier work always considered

breakdown to be a field-dependent phenomenon [13].

C-V curves made on pulsed MOS capacitors would indicate whether any new electron olC.ide

traps have been generated in the~. No shift in the C-V curve of a p-Si MOS capacitor

was observed after a 150 V pulse was applied. It can, therefore, be concluded that the

pulse did not generate any new electron traps in the p-Si capacitor. However, the

capacitance minima of n+-Si capacitors showed a significant shift m the negative

voltage directiOn [14], after bemg subjected to a positive pulse just below the

breakdown threshold. Hence, poslt:lve pulsed voltage stress forms interface states m

n+-Si capacitors.

5.4. SEQUENTIAL PULSING

5.4.1. E-mode NMOS transistors

73

The extent of the degradation increases as the number of pulses is increases.

However, devtces which had not shown degradation after a single pulse, did not

appear to be affected by further pulses at the same voltage. This is in agreement with

Welters' [6] assumption, for constant applied voltages, that the weakest defect

determines the dielectric strength of the oxide. Therefore, in the oxides which showed

no damage at a given voltage, there were no weaknesses acnvated by that elecmc field.

5.4.2. p-Si MOS capacitors

Experiments on p-Si MOS capacitors clanfied the results obtained after sequennally

pulsing E-mode NMOS tranSIStors. As the number of pulses increased, the resistance

got lower. This is comparable to the mcrease in degradation observed in the

transistors (Section 5.4.1.).

It must be noted, that m both the tranststors and the capacitors, the degradation was

not a linear function of the applied number of pulses.

5.5. CONTINUOUS VOLTAGE STRESS EXPERIMENTS

5.5.1. Breakdown thresholds

The breakdown threshold of the three MOS capacitor structures were approx!IDately

±35 V. This is sigmficantly different to the pulsed voltage breakdown thresholds,

!IDplying that two dtfferent mechanisms are involved m the two cases. The continuous

voltage breakdown thresholds were shown to decrease as the temperature was raised.

Pulsed breakdown, m comparison, was not temperature dependent, adding further

eVIdence to the case for two different mechanisms of breakdown.

74

5.5.2. Polarity

The polarity of the constant applied voltage did influence the breakdown threshold,

and, was related to the type of capacitor. For all three types of of capacitor, the

negative voltage breakdown thresholds were very abrupt. However, in the positive

direction, the rate of increase of gate leakage current with applied voltage, was greater

for more n-type Si surfaces. These results are comparable to the threshold voltage

differences under pulsed conditions, and, supports the charge InJection model of

breakdown.

5.5.3. C-V curves

Changes in C-V curves of the MOS capacitors began at ±30 V, which 1s in the voltage

region where the equivalent I-V curves began to change. Therefore, sh1fts in the C-V

curves can be cons1dered to indicate the onset of made damage.

The shift of the curves in the neganve direction, after the application of neganve

voltage stress, implies that a posinve charge has been formed at the Si-Si02 interface.

This can be attnbuted to the emission of electrons from surface trap states and into the

Si under the influence of the large neganve voltage. A number of uncompensated,

posinvely charged states, are formed at the mterface [15]. The applied gate voltage

under normal operanng conditions is supplemented by these charges, causmg

depletion, an subsequently, inversion to occur at less posmve voltages.

After a posltive voltage stress, the C-V curves become distorted, although there is

negligible shift along the negative voltage ax1s. In this case, the semiconductor

surface lS the cathode. Any unoccupied interface states are fllled by electrons injected

from the surface. In addltion, a number of electrons will be trapped at newly formed

75

states in the oxide within close proximity ("'20 A) of the surface. The result is that the

fixed charge concentration at the surface mcreases, requirmg that the voltage required

for inversiOn is greater. This broadens the C-V curve. The space-charge capacitance

( Csp) will also nse because of the fixed charge, causing the minimum overall

capacitance to increase.

5.6. GENERAL

A distinct difference exists between the charge supplied by a single pulsed voltage and

a constant applied voltage. In the first case, a fiXed amount of charge is deposited on

the contact electrode. This charge Will decay according to the properties of the gate

oxide capacitor. In contrast, a constant applied voltage will connnuously supply

charge to the contact electrode, at a constant energy level.

5.7 SUMMARY

1. Damage m MOS strucrures IS due to electron conduction paths in the gate oxide, as

a result of the voltage stress. The presence of oxide defects will enhance the

prospect of damage.

2. Analysis of the I-V charactenstics of MOS transistors showed that as the

magmmde of the pulsed voltage mcreases, devices are more likely to be damaged.

3. Devices can snll be considered to be funcnonal even though therr I-V characterisncs

show degradanon, especially in digital applicanons.

76

4. The application of sequential pulses showed that degraded devices would be highly

prone to subsequent failure. Such devices would form part of the "walking­

wounded" once operational and can give nse to latent failures.

5. The dimenswnal dependence of oxide breakdown suppons the assumption that

mtrins1c defects, such as those introduced by weak S1-0 bonds or 1mpunties,

increase the sensitivity of the SiOz to breakdown.

6. The temperature independence of pulsed voltage damage when compared with the

temperature dependence of contmuous voltage damage, mdicates that two different

breakdown mechanisms are involved.

7. This IS funher highlighted by the large difference between the breakdown

thresholds under pulsed and continuous voltage conditions. Pulsed breakdown

thresholds are a factor of 5 greater than the continuous voltage thresholds.

8. The observation of a sigmficant polarity dependence for both pulsed and

continuous voltage breakdown of MOS capacitors, is related to the effect of the

dopant concentration at the Si surface. This indicates that the breakdown

mechanisms are strongly influenced by the charge injection process at the

electrodes.

9. C-V curves on MOS capacitors show that the inJection of charge at the Si-Si02

mterface does take place. The effects are observed just pnor to the onset of oxide

breakdown.

5.8. REFERENCES

77

1. NICOLLIAN E.H., BREWS J.R., MOS Physics and Technology.­

John Wiley and Sons (New York), 1982.

2. BLICHER A., Field Effect and Bipolar Power Transistors. - Academic

Press (New York), 1981.

3. RICHMAN P., MOS Field Effect Transistors and Integrated Circuzts. -

John Wiley and Sons (New York), 1981.

4. SZE S.M., Physics of Semiconductor Dev1ces, 2nd Edition. -John Wiley

and Sons (New York), 1981.

5. HART A., TENG T.T., McKENNA A., Reliab1lity influences from

electrical overstress on LSI devices. - 18th Ann. Proc. IRPS, pp. 190-196,

1980.

6. WOLTERS D.R., VAN DER SCHOOT J.J.,Dielectric breakdown zn

MOS devices Part I: Defect-related and intnnsic breakdown.- Piu!. J. Res.,

40, pp. 115-136, 1985.

7. AMERASEKERA E.A., Failure mechanisms in semiconductors dev1ces.

Report No 2, MOD Contract No. ASa/1265, LUT Contract No. ELB

2JJW.-Internal publication, Loughborough University, July 1984.

8. OSBURN C.M., ORMOND D.W., Dielectric breakdown in silicon

dioxide films on Silicon. i. Measurement and interpretation. - J.

Electrochem. Soc., 119, pp. 591-597, 1972.

9. OSBURN C.M., ORMOND D.W., Dielectric breakdown in s1licon

dioxide films on Silicon. ii. Influence of processing and materials.- J.

Electrochem. Soc., 119, pp. 597-603, 1972.

10. WOL TERS D.R., V AN DER SCHOOT J.J., Dielecmc breakdown

in MOS devices. Part I!. Conditions for the intrinSIC breakdown. - Phi!. J.

Res., 40, pp. 137-163, 1985.

78

11. NISSAN-COHEN Y., SHAPPIR J., FROHMAN-

BENTCHKOWSKY D., Trap generation and occupation dynamics m

SiOz under charge injection stress. - J. Appl. Phys., 60, pp. 2024-2035,

1986.

12. KLEIN N., Mechanisms of electrical breakdown in thin-insulators - an

open subject. - Thm Solid Films, 100, pp. 335-340, 1983.

13. O'DWYER J.J., The theory of electrical conductiOn and breakdown in

dielectric solids.- Clarendon Press (Oxford), 1972.

14. AMERASEKERA E.A., CAMPBELL D.S., ESD pulse and

contmuous voltage breakdown in MOS capacitor structures - Proc. 8th

Ann. EOS/ESD Symp., Las Vegas, 1986.

15. MANY A., GOLDSTEIN Y., GROVER N.B., Semiconductor

surfaces. - North Holland Publishers (Amsterdam), 1965.

79

CHAPTER 6

MODELLING OXIDE BREAKDOWN MECHANISMS

IN MOS STRUCTURES

6.1. INTRODUCTION

A model of the SiOz breakdown mechanisms, under pulsed and continuous voltage

condinons, is presented in th1s chapter. The model1s founded on the experimental

work discussed in the previous chapters.

In Chapter 4, it was observed that MOS capacitor structures w1th three different

concentrations of electrons at the surface, when in thermal equilibrium, had dlfferent

rates of breakdown. Devices w1th more n-type doping showed more defined

breakdown thresholds. Under pulsed condinons, the pos1tive breakdown thresholds

were greater than the neganve thresholds, for more p-type deVlces. Therefore, it was

concluded that the injection of electrons from the cathode into the Si02 was

responsible for breakdown.

Previous workers have observed that MOS structures with n-type surfaces had lower

breakdown thresholds than p-type surfaces [61] - [63]. There is also evidence to

show that the breakdown threshold wah an n+ polys1licon gate as the cathode, is

lower than when a less n-type surface is the cathode [51]. This dispanty between the

breakdown thresholds of the p and n-type structures has been attrlbuted to mtrinsically

higher defect densities in films grown on different wafer types [ 62]. However, this

explanation is not consistent Wlth both the pulsed and continuous voltage observanons

wh1ch indicate that the mjected charge must be cons1dered. In add1tion, numerous

80

papers on oxide breakdown and charge injection, have observed differences in the

behaviour of Si02 films on p and n-type Si, but have not analysed these effects

[24][51][53][56][64]. It is significant that, m every case, then-type structure has a

lower breakdown threshold or shows a higher leakage current.

MOS charge injecnon theory, and electron conduction processes are descnbed in th1s

chapter, and adapted to explain the phenomenon associated w1th ox1de breakdown in

MOS structures [67][70]. Two different breakdown mechanisms are proposed for

continuous and pulsed voltage breakdown.

6.2. THE MOS STRUCTURE

6.2.1. Introduction

Th1s secnon (6.2) outlines the principal theory of MOS structures, paving the way for

the adaptation of dielectric breakdown theory to these structures in later sections.

6.2.2. Energy band structure

The energy band structure of an MOS capacitor is shown in Figure 6.1. [1][2]. Si

has a band gap of 1.12 eV which is small compared to the forbidden gap in Si02 of

8.8 eV. It must be noted, however, that in SIOz, it is not strictly correct to refer to a

forbidden (or band) gap, smce It is an amorphous matenal and therefore has localised

rather than connnuous energy levels [3].

The electron affimty (X) of Si02 1s 0.9 V, 1.e. the energy requrred to remove an

electron from the bottom of the conduction band is 0.9 e V. x IS =4.15 V in Si. The

81

-----­ _ _ Vacuum level ,

4.25 eV

3.15e

i T -1-_-_-_-_-_-___ ....::,...Eit_- 12 eV

E V

8.8 eV

+ n poly Si gate p-type Silicon

FIGURE ~.1. En~rgy band-diagram of MOS structure (n polySi-Sio

2- pSi).

' -

n-type MOS

n + polyS1 gate 5102

FIGURE '.2. a) n-Si HOS 1n accumulatLon (VG > 0)

+ n PolyS1 gate

-, ' '

'

"---------- E c

- - - - - - - - EFp

n - SL

E

' E

V

FIGURE ,.2. (b) n-SL MOS 1n LnversLon (VG < 0)

- - - --------------------------------------------------------------,

position of the Fermi level in the Si is dependent on the impunty concentration in the

matenal. A p- type material will have an effective, or quasi, Fermi level (Epp) below

the intrinsic Fermi level (EFi) of undoped Si. Ann-type material will have Ep0 > Ep1

(4]. Then+ polysilicon gate has a Fermi-level which coincides with the bottom of the

Si conduction band [2](5].

From the energy level differences between the bottom of the Si02 conduction band

and the Si conduction bands, the energy required to get an electron from the Si mto

the lowest unoccupied states m the Si02 is "'3.15 eV.

6.2.3. Band-bending

Upon application of an electric field across the capacitor,the energy levels in the

conduction band and the valence band are shifted in order to accommodate the charges

at the Si surface. Energy diagrams for an n-type MOS system in accumulation

(Figure 6.2 (a)) and in depletion/inversion (Figure 6.2 (b)) show the various potential

and the surface charge concentrations [1].

The potential <j>(x) is defined by,

q<j>(x) = EF - E (x) n t

Eq (6.1)

where E,(x) is the intrinsic Fermi level.

As x--?oo, I.e. deep m the bulk of the S1, <j>(x) becomes the bulk potential <j>8 . At the

silicon surface (x = 0), <j>(x) is the surface potential <l>s· The band-bending <p(x) is

then defined as

82

cp(x) = cj>(x) - cp8 Eq (6.2)

cp(x) is therefore, representanve of the potennal at any point in the depletion reg:ton,

with respect to its value in the bulk. The total bend-bending, cps, is given by the total

potential difference between the silicon surface ( cps) and the bulk ( cp8).

Eq (6.3)

In order to calculate the surface potential as a function of the chstance, x, from the Si­

Si02 interface (x = 0) to the Si bulk, it is necessary to solve P01sson's equation in one

dimension.

d2cj>(x) -p(x) =--

dx2 Eq (6.4)

p(x) is the charge density (coul cm-3) and es=l.04 x 10-12 Fern-! is the permittivity of

Silicon.

The solutions of this equation have been analysed by Kingston and Neustadter [6],

Garrett and Brattam [7], Seiwatz and Green [8] among others [9][10][11] and will not

be descnbed here. However, the solunons are complicated and Will be summansed as

follows:

1. The relanonship between the elecmc field (E = -dcp/dx) and the potential is given

for a p-type matenal as,

Eq (6.5)

83

where Ln 1s the effective Debye length for holes.

and

~=.3._ kT

Eq (6.6)

Eq (6.7)

Ppo and npo are the equilibrium densities of electrons and holes respectively, m the

bulk of the semiconductor.

Eq (6.8)

for a non-degenerate surface. A degenerate surface will require adjustment as

described by Seiwatz and Green [8] and Many et a! [12].

2. The potential as a function of distance is g~ven by

~q>

X 1 f d(~<p) ~L0 -J2 [A npo]

~'l's F p<p,P po

84

Eq (6.9)

which has to be solved numerically.

3. The surface charge per unit area is given by,

Eq (6.10)

Eq (6.8), (6.9) and (6.10) are represented graphically in Figures 6.3, 6.4, and 6.5

respectively, for easy reference. Using these equations and the equations for surface

degeneracy [8][12], the maximum band-bending at the surface of an MOS system can

be calculated.

For example, with a positive applied voltage of 40 V across an oxide of thickness 400

A,

a) a p-type material with a bulk dopant concentration (NA) of 4 x 1015 cm·3 has a <ps =

0.98 V and is in strong inversion.

b) ann-type matenal With a bulk dopant concentration (No) of 4 x 1015 cm-3 has a

<ps = 0.33 V and is m strong accumulanon.

6.2.4. Majority and minority carrier response times [1]

In accumulation and depletion, the charge in the silicon surface contributes to the

MOS capacitance. Majority carrier response times to an applied gate voltage are given

by [1],

85

FIG 6.3 GRAPH OF F -FUNCTION VS SURFACE POTENTIAL FOR p-TYPE Si

1rf

1rf

10'

1rf

z 1rf 0 >= u 10' z ::> ~

~ io'

la'

10'

1rf

10.1

., -08 -06 -o• -02 0 02 OA 06 08 SURFACE POTENTIAL, V

FIG.G.4 BAND-BENDING VS DISTANCE FROM INTERFACE FOR n-S1

••.---------------------------------------------~

> <5 z 0 z w m I

0 z <{ m

0 2

·02

-00

-06

-o • (

15 -3 No= 4x1o cm

_,:r...._ __________________ ~

00 50 100 150 200 250 300 350 400 450 DISTANCE ems •1o·•

FIG 6.5 GRAPH OF SURFACE CHARGE DENSITY VS SURFACE POTENTIAL

"s 6 o

N

' • 0 c u

;; a.

~ lJ u a

?C ~ 0 0 w 0 w •o ~ <{ :t -2 0 u w u ;:: ~

~ ... )

-0.

I pSI 15 -3

I NA::4x1Qcm

\ I \ I

I I I

I '

-02 f) ' r) 4 ' 6 SIJPrt.rr Pf)T[NTI/.1 V

Eq (6.11)

where n is the number of carriers per unit volume. For n = 10 16cm-3, 'tmaJ = 10-12

secs .. The majority carrier response can be considered instantaneous for the purposes

of the analysis presented here.

In inversion, the minority carrier response nme is important. Response times in Si at

room temperature are very slow, typically 0.01 - 1 sec. in strong inversion. The exact

value is dependent upon the impunty concentration, the density of conduction band

electrons or valence band holes and the electron/hole lifetimes [1]. However, the

response time IS very long and Will mfluence the charge concentranons at the silicon

surface, when pulses with risetimes of the order of 10-6 secs. are applied. While the

risetime of the pulse should have no effect on the mversion layer, the decay nme,

which 1s proportional to the system RC time constant, will result m bringmg mmority

carriers to the silicon surface. The resistance of a typical MOS gate oxide capacitor is

=1016 n while C = 10-16 F, for a gate area of l!J.m2. The decay nme is 1 sec. which

is well Within the minimum mmority carrier response nme.

6.3. PROPERTIES OF THE SILICON DIOXIDE DIELECTRIC

6.3.1. Structure of silicon dioxide

Thermal Si02 is amorphous m structure, i.e. long range order is absent, the array of

equilibrium atomic positions being strongly disordered [13]. This disorder gives rise

to localised energy levels withm the forbidden gap due to the t:uls of energy states

emergmg from the conducnon and valence band edges and stretching into the

86

forbidden gap (see Figure 6.6) [14][16][17]. However, these localised energy levels

are not considered to be sufficiently deep or dense to be important to the electromc

conducoon processes in Si02 [14][17]-[20].

Si02 is formed by a sharing of valence-electrons between silicon and oxygen to form

four silicon-oxygen bonds. Each bond is largely covalent with a small Ionic

component [1]. The bonding energy between silicon and oxygen is= 6 eV [15].

6.3.2. Oxide defects

6.3.2.1. The Si-Si02 interface [1][21]

Chermcal inhomogeneities such as stretched, bent or broken bonds, stoichiometric

conditions as well as 10nic impurities at the Si-Si02 interface, will result in the

formation of traps, which, by capturing charge carriers, can affect device

performance. Additionally, these traps can also provide the first stages of an

electronic conduction process in the Si02. Interface traps charactenstic of thermal

OXIdation are donor type, and, under the mfluence of a suitable electric field, will

release electrons to form a positive charge d!stribuoon at the interface. They have

energies ranging all the way across the Si forbidden gap. If the Silicon surface IS p­

type, the posiove charge causes mvers10n to occur at more negative gate voltages.

This can be observed using a C-V plot as shown m Chapter 4.

6.3.2.2. Bulk oxide traps [1][22]-[27]

Bulk oxide traps are associated with defects in the S10z such as Impurities and broken

bonds. All thermally grown Si02 films contain electron traps related to the presence

of water (H20) m the fihn [22][23]. It has also been shown that ionic impurities such

87

Energy

E c

E V

ln D(E)

Tails of localised states in the forbidden gap.

FIGURE 6.6. Schematic illustration of the forbidden gap, depicting the presence of localised energy states.

as Na+ exist as traps in the Si Oz. The energy levels of the traps with respect to the

conduction band edge (the trap depth) have been reported as 1.9, 2.0, 2.13, 2.35 and

2.37 eV, with a spatial distribution which IS uniform through the ox1de [24]-[26]. Ion

implantation of boron, arsenic and phosphorus 1s also a source of defects, creating

numerous traps resulting from exchange of energy between the 10ns and the S102

lattice. Trap densities are proportional to the implantauon energy for a given number

of implanted ions [1][27].

6.4. ELECTRONIC CONDUCTION PROCESSES IN Si02

6.4.1. Hopping conduction [14][28]-[32]

The oxide traps and donor sites described in the previous section, will appear as

coulomb1c potential wells in the S10z band-diagram, once charged. A trap site having

captured an electron becomes negauvely charged and the energy diagram takes the

form shown in Figure 6.7 [29]. A donor site havmg errutted an electron becomes

positively charged and the energy diagram takes the form shown in Figure 6.8 [32].

The difference m the two energy diagrams is that the former has an external potential

well which is assumed to be coulombic, while the mner potential well is slightly

steeper in order to maintain the trapping level. However, the effect of a uniform

external field, in either of the two cases, would be to lower the potennal barner. This

IS due to the density of 10mzed centres becorrung sufficiently large for their potential

wells to begin to mteract with each other. For a donor centre, the effect can be

descnbed by Figure 6.9 [14]. The potential energy of the well <j>(r) then becomes,

2 e <j>(r) = ---- eFr cos9

47tEr

Eq (6.12)

88

where F is the external field, e IS the angle between the radius vector r and the electric

field. The zero of energy is taken to be the bottom of the conduction band [32].

The result is that electrons are able to move through the oxide by hopping from well to

well in a manner analogous to that described by Schottky emission. This is known as

the Poole- Frenkel effect [33].

It is possible, to picture the mechanism of hopping transitions between traps in a high

electric field, m a qualitative manner, using Figure 6.10 [30]. The electric field

enables earners to r:use their position relative to the conduction band edge and so to

'move' to another trap site.

A fmite temperature dependence does exist for this mechanism. Electrons gain

thermal energy from the lattice vibrations to enable them to escape from the coulombic

potential wells. Hence, it is possible for conduction to occur at lower electric fields as

the temperature of the sample is increased [29].

Trap relaxation times are expected to be of the order of milliseconds (l0-3 secs) if not

longer, and are dependent on the energetic distances between neighbouring traps [30].

6.4.2. Impact ionization in Si02

been Impact iomzauon m solids ha~extens1vely studied by Fri:ihlich [37][38], Seitz [39],

Callen [40] and, more recently, O'Dwyer [35].

Since the forbidden gap in Si02 IS very large (=8eV), the conduction band can be

considered to be almost devoid of free electrons. However, under the influence of a

large electric field, the conducuon band edge is sufficiently deformed to enable

89

I \ I \

I \ I

\ I I \

I \

T •

1 Steeper liell

FIGURE ,.7. A negatLvely charged electron trap-s 1te

<)(x)

Ground state

FIGURE 6 9.

Coulomb Le "Hill"

X m

E

FIGURE &.8. A postttvely charged donor stte

A pontLvely charged donor stte under the tnfluence of an external electrLC fteld

FIGURE {,. 10.

0 ~0 0

.~ 0

• • ........_-o ~ 0 0

•• "-... 0 • • 0 0 . ·~ • • • ?'Z

0

• •

• •

Schemattc tllustratton of electron transLtLons between full and empty traps under the 1nfluence of a h1gh ElectrLC fteld.(ref. 14)

electrode

'\.

' ' '

+ +

/

'

htgh-energy electrons

Ji' electron d1strtbut1on --r- E tontzatl.on

+

e- -.,after

e-_....1mpact 1 nu:atton

e- +- recombtnatton

E c

electrode

-+r-----.J Ev

Posttl.ve charge butld up

FIGURE ,.11. Schemattc tllustrat1on of the tmpa~t tontzatton process tn St02 (re£ 46)

injection of electrons from the conduction band of the Silicon into the conduction band

of the silicon dioxide, either by means of Schottky emission or by Fowler-Nordheim

tunnelling [33]-[35]. Once in the conducnon band of the SiOz, these free electrons

gain energy from the electric field and upon collision with the latnce, unnl there are

enough high energy electrons to cause impact IOnization of electrons from the valence

band, leaving behind low energy holes. A distonion of the electric field occurs

because of the positive charge contributed by the build-up of residual holes, resulting

m a correspondmg increase in the injection current. Hence, an increase m the rate of

Impact IOnization occurs due to the higher field and current [46]. The process is

schemancally depicted in Figure 6.11.

The threshold energy for ionization, E1, is given by [45][49][50],

E =E [(2+ fr1t)/(1+ fr1,)] , c m m

e e

Eq (6.13)

and lies between 11.5 e V and 12.5 e V for SI Oz. mh/me is the effective mass ratio for

SiOz and Eo IS the band gap. The cnncal electric field for breakdown under

continuous voltage conditions IS given by [ 46],

Eq (6.14)

Eo = 9 0 e V is the insulator band gap, A. IS the electron-phonon scattenng length and y

=iiro/eFA..iiro is the phonon energy. A. IS requrred to be about 1.4 A in order to fit

experimentally determined breakdown fields where Fb = 9.5 MY cm-1. It is found

that Fb IS only dependent on A. and Eo.

90

The ionization rate for amorphous SiOz with an applied field of =107 Vcm-1, is 1012

per sec. [49]. It has been estimated that =1012 electrons are required to cause

breakdown in a solid 1 Q-5 cms2 in area and 1 cm long, which is eqmvalent to =40

generations of collision IOmzation [39]. If a(Fb) is the collision ionization rate per

umt length, then [ 48]

Eq (6.15)

where d IS the thickness of the oxide. a(Fb) has been shown [45] to be =104 cm-1 for

Fb = 107 Vcm-1, and with d=10 nm the time required to initiate Impact ionization

breakdown is <10-9 sec. in Si Oz. Therefore, 1t is well within the risetimes of the

pulses used in the experiments described in Chapter 3.

The effect of traps in the insulator on the tunnelling properties has been investtgated

[41]-[44]. It has been shown that the presence of a trap with the same energy as that

of the mcident electron causes the amplitude of the wave to resonate With the potential

well created by the trap. The transmission function of such an electron Will be greater

than for an electron tunnelling via the usual process. Transrmssion of this nature IS

called resonance tunnelling, and electrons transmitted in this manner will mcrease the

probability of rmpact IOnization in the Si02 conductton band.

Traps have also been shown to have an imponant effect on the mternal fields m the

oxide [ 46][51]. As mentioned ear her, holes generated m impact ionization will be

dnven to the cathode where they can be trapped, thereby, increasing the field.

The result will be an mcrease in electron mjection from the cathode due to the higher

localized field and therefore a higher probability of impact IOnization in the Si Oz. A

quantitative model has been developed by Chen et al [51].

91

6.5. CHARGE INJECTION MECHANISMS

6.5.1. The Schottky effect [2][29]

The Schottky effect ts the injection of charge by thermionic emission over a potential

barner, which has been reduced by the mfluence of an external field (Figure 6.12).

The current density can be wntten as [2] [29],

Eq (6.16)

where m* ts the effective mass of the electron and ~s is the Schottky field-lowenng

coefficient given by,

Eq (6.17)

where Eo is the permunvity of free space and !; is the relative permtttivity of the

insulator. <P ts the potennal barrier between the cathode and the dielectric. Injection

takes place over the potential hill and not through it, and is a funcnon of the barrier

lowering due to the applied field, as well as, the thermal energy of the electrons at the

electrode.

6.5.2. The Poole-Frenkel effect [2][14][29][32][33]

92

The Poole-Frenkel effect is an extension of the Schottky effect [33], and considers the

thermionic emission of trapped charge earners in a solid under the mfluence of an

external electric field, as described in Section 6.4.1.. The current density Is of the

form [2][29],

Eq (6.18)

where ~PF is the Poole-Frenkel field lowering coefficient given by,

Eq (6.19)

~s is as given in Eq ( 6.17).

The constant of proportionality will depend on the number of available donor/trap

centres m the dielectric and the distance travelled by each carrier after emission [14].

6.5.3. Tunnelling in MOS structures

Electrons can also reach the S102 conducnon band by quantum mechanical tunnellmg

under the mfluence of strong electric fields [34]-[36][52]. Early work is based on a

seffilclassical framework, using the dynamics of a free-electron model of a metal­

vacuum contact.

Consider the triangular potential bamer shown in Figure 6.13 .. The potennal barrier

V(x) IS given by,

93

eV(x) = -eFx Eq (6.20)

where e IS the electron charge (1.602 x lQ-19 coulombs), F is the external electric field

and x IS the distance m the direction mdicated in the figure. However, the external

electric field induces an image-force which rounds off the top of the barrier, lowering

the potential energy at the interface (as in the Schottky effect) ( Figure 6.12). The

potennal barrier becomes [35][36],

2 e

eV(x)=-eFx--4ex

Eq (6.21)

The tunnelling current, J, is found by inserting this potential energy into

Schrodmger's Equation and solving it to obtam the wave function and the

transmission and the transmission probability D, as described in Appendix 2 [34][52].

Hence [35][53],

J = e3~ .exp~4~ 4>;] 8nhq> 3beF

Eq (6.22)

where 4> is the barner height measured between the Fe= surface m the metal and the

conduction band in the dielectric. m* is the effective electron mass appropriate to the

electrons in the &electric.

The transmission coefficient, D, IS given by [34][36],

94

I I

2 2 [ '] 4E (cj>-E) 4a -D(E)= x x .exp--(cp-E) 2

x cj> 3F x

Eq (6.23)

where,

[ 21! I 8m1t 2 1 • 2 -I

a= T = 5.16 X ro· (eV) cm Eq (6.24)

and,

Eq (6.25)

IS !he kinetic energy of !he mcident electrons.

However, when considering tunnelling !hrough MOS structures, !he above theory is

inadequate. Under !he influence of !he high fields required to initiate tunnelling at !he

Si-SiOz interface, !he Si band-bending will be significant and !he lugh concentration

of charge at !he sermconductor surface (whe!her m inversion or accumulanon) must be

considered. Large concentrations of charge at !he surface will cause energy level

quantisatlon (subbands) to occur Within the Si conduction band. Motion

perpendicular to the Si-SiOz mterface Will, !herefore, take place only at discrete

energy levels. Hence, !he free-electron model used by Fowler and Nordheim in !herr

!heory, cannot be used [54]-[58].

The effect of energy band quantisation at !he SI-StOz mterface has been extenstvely

studied [54]-[57]. It has been shown !hat !he ground state in the silicon conduction

95

band (E0) can be separated from the next energy level by almost 0.1 eV depending on

the extent of the band-bending and the dopant concentration [55]. In order to obtain

the modified transmission coefficient and, therefore, the tunnelling current under these

conditions, the basic approach described in Appendix can be used [57][58].

However, once energy level quantisation is introduced, and good modelling of the

band-bending is included, an exact solution becomes impossible. Hence, various

approximation techniques have been used, although even these can become extremely

complicated. The outcome IS a transmission coefficient and a tunnelling current which

are dependent on the energy of the ground state subband (E0 ) and the depth of the

silicon band-bending [56][58][60]. A simplified expression for the tunnelling current

is obtained by considenng the Si-Si02 interface shown in Figure 6.14 as [56][60],

J =q9N P mv Eq (6.26)

where Nmv is the number of electrons per unit area at the mterface, and a is the

fraction of these that reside in the lowest subband. P IS the transmission probability

current per electron for the ground state. For an mversion layer density Nmv ~ 1013

cm-2 corresponding to an external field of 107 Vcm-1, and with a depletion

concentration Ndep = 1011 cm-2 correspondmg to a bulk impunty concentration of NA

= 1Ql5 cm-3, J becomes,

Eq (6.27)

where,

Eq (6.28)

96

1 ' ' 6<1>

' ~ ' V m

t -'>.. -E -------- -

EF X

X

FIGURE &.12. The Sthottky effect at a metal-sem1.conduceor/ d1.electr1.c 1.nterface

V(x)

0 -X FIGURE (,.ll. The Fowler-Nordhetm tr1angular barr1er at a

metal-semt.conductor/dlelectrt.c t.nterface

Energy (eV)

-q Fl X

FIGURE 6 14

REGION 1 Semtconductor

REGION 2 Insulator

Ltnear approxt.matt.on of the potenttal barner at the St- St02 tnterface (ref. 56)

EMPTY

TRAP SITES

EMPTY

FILLED

a) n-type

b) p-type

V > 0

FIG.6.15

FIGURE 6.15

FIGURE ,.16.

EMPTY

a) n-type

EMPTY

b) p-type

FIG.6.16

Illustrat~on of the trap states at an n-type and a p-type St-St02 tnterface (V > 0)

Illustratton of the trap states at an n-type and p-type Sl-St02 tnterface (V < O)

V<O

and Fox is the oxide field.

Comparing the multiplier m this expression with those of the Fowler-Nordheim

expressiOn, it has been calculated that Eq ( 6.27) is approximately a factor of 2.5

higher for the conditions given here [56][60].

6.6. THE OXIDE BREAKDOWN MODEL

6.6.1. Continuous voltage stress breakdown

The main features of continuous voltage breakdown were;

a) the sigruficant temperature dependence of the breakdown thteshold,

b) the asymmetrical !leak vs. Yappl curves for p-type structures compared to more n­

type structures,

c) the shift in the rmmma of the C-V curves in the negative voltage direction with

negative applied voltage, and the increase m the rnimmum value of capacitance

with a negligible shift m the rmnima with posltlve applied voltage.

The temperature effect implies that electron traps are generated Withm the oxide under

the mfluence of high electnc fields (=7.5 MV cm-1) and enhanced by temperature

[69]. Ermssion of electrons from 1mpunty or donor sites IS, therefore concluded to be

of a therrnionic field ermssion nature governed by the Poole-Frenkel effect.

97

The C-V curves are typical of surface state mteractions [1][2][12]. Figure 6.15

shows the effect of interface states on the energy bands of an n-type and a p-type

semiconductor. A positive electric field across an n-type capacitor structure causes the

bands to bend downwards. Hence, traps at the mterface will be filled with electrons,

while donor sites will emit electrons to traps (or empty donors) in the oxide bulk

under the Poole-Frenkel effect and capture electrons from the Si surface. The trap

sites become negatively charged, but the donor sites remam neutral. The increased

negative charge at the surface affects the depletion layer of the n-type Si and so

reduces its influence on the overall capacitance since [1][2],

1 1 1 -=--+-CS c c ox sp

Eq (6.29)

where Csp is the capacitance of the space-charge (depletion) region. A large neganve

voltage will bend the bands away from the Fermi level (Figure 6.16.), causing

electrons to be ermtted from trap and donor sites at the mterface. A poslttve charge IS

formed at the interface whtch, in p-type capacitors, enhances the acnon of the gate

voltage and attracts electrons to the surface.

The result 1s that the onset of depletion takes place at a less posinve voltage. In n-type

structures, the positive charge requires that the applied voltage has to be more

negative, in order to obtam inversion. Both structures show C-V curves shifted in the

negative direcnon along the voltage axis.

The asymmetry of the I leak vs. V appl curves IS a consequence of the mterface state

effect observed in the C-V curves. The n+ polysrlicon gate has a Fermi level which

comcides With the bottom of the conducnon band, and so has a large population of

free electrons when in thermal eqUilibrium. Although the interface between the

98

FIG 6.17 BAND-BENDING VS. DISTANCE FROM INTERFACE

> <:i ~ 0 z w CD I

0 z <! CD

o a

0 6

0.

0 2

0

-o 2

- I

15 -3 N=4X10 cm

-04~,--------~--------~--------~------------------~ 0 0 5 0 10 0 15 0

DISTANCE, ems 20 0 25 0

*10''

polystlicon and the Si02 is a deposited one, it can be considered to have interface

states similar to those at the thermally grown Si-Si02 interface [1][65][66]. When the

gate is the injecnng electrode (negative voltages), the conduction bands at the

polysi!icon-Si02 interface bend very slightly downwards. In fact, due to the very

high doping of the polystlicon gate (=1Q21 cm-3), this band-bending can be

considered to be negligtble. Band-bending at the semiconductor surface depends on

the doping concentration and is descnbed m secnon 6 2.3 .. Figttre 6.17. shows how

the bands vary as a function of distance from the mterface for NA = 1016 cm-3 and No

"' 1016 cm·3, the bulk acceptor and donor densities, respectively (from Eq (6.9)).

For an n-type surface with a dopant density N 0 "' 1016 cm-3, a positive gate voltage

results m an accumulation region with a maximum band-bending of 0.33 V. For a p­

type surface with a dopant density NA"' 1016 cm·3, a positive gate voltage will result

in an inversion region, the maxtmum band-bending bemg 0.97 V. The charge

induced at the surface as a result of an applied gate voltage can be obtained usmg

Gauss' Law which gives [2][67],

Eq (6.30)

where Eox is the permittivity of the OXIde, and E0x is the electric field across the oxtde.

For a gate voltage of 40 V across an oxtde of thickness 400 A, the total charge is Q5 =

3.45 x l0-6 Cou1 cm-2 indicanng a surface charge density of n5 = 2.2 x 1013 cm-2. n5

is constant for the values assumed, and is independent of the doping type or the

concentration of charge at the Si surface. However, the spatial depth of the band­

bendmg is greater for p-type than for n-type Si. For n-type Si the electron

concentranon in the accumulation regton can be 5 to 10 times greater than the electron

concentranon in a p-type inversion layer. Therefore, the number of occupted states m

99

------------

the conduction band of an n-type accumulation layer is greater than that of a p-type

mversion layer with the same applied voltage.

The tunnelling current density is dependent on the electron charge dens1ty by means of

the supply function N(Ex), since [41][52][58],

00

D(E ).N(E ) dE X X X

Eq (6.31)

0

where Ex is the energy of the incident electrons, D(Ex) is the transmission probab!lity

and N(Ex) is the supply function, i.e. the number of electrons m the energy range Ex

to Ex+dEx ava!lable for tunnelling through the barrier.

Eq (6.32)

where C is a constant and the logarithmic function 1s based on occupation statistics

[52].

The low number of available unoccupied states in then-type conduction band in

accumulation, would also undicate that the probab!lity of reflection at the Si-Si02

mterface IS less, mcreasmg D(Ex) [ 68].

Hence, the tunnelling current for electrons at the Si-Si02 mterface would be greater

for an n-type accumulation surface compared to a p-type mvers10n surface with the

same b1asmg conchnons.

100

The process can be summarised as follows;

Electrons tunnel from the Si mto mterface states or impunty sites in the Si02,

initiating the electroruc conducnon process through the oxide. The higher the

concentration of electrons (N A) m the Si, the greater the leakage the leakage current,

givmg nse to the !leak vs. Vappl curves observed expenmentally (Chapter 4).

6.6.2. Pulsed voltage stress conditions

Pulsed voltage stress experiments described in Chapter 3, showed that the positive

voltage breakdown thresholds for p-type MOS structures were almost twice as much

as the negative voltage thresholds. This difference was reduced as the semiconductor

was made n-type, suggesting a charge injecnon effect. However, the effects of

pulsed voltages on the semiconductor surface must be considered.

When a large posinve pulse is applied to an n-type structure, the surface is forced

towards accumulation. The majonty earner movement is important m accumulanon

and, as discussed in Section 6.2.4., the response time is almost mstantaneous (10- 12 !o

secs.). Hence, the Si surface has time~reach strong inversion Within the risetime of

the voltage pulses used m the experiments. Electrons injected from the strongly

accumulated Si surface, together with electrons from traps and impunty Sites already

m the ox1de, tunnel through to the SiOz conduction band. Impact ionization (as

descnbed in Secnon 6.4.2.) takes place and results in oXIde breakdown [71]. With a

large negative voltage, the injecting electrode IS the n+ polysilicon gate, with sufficient

electrons to be able to match the process described for a positive pulse. The

breakdown thresholds are, therefore very similar in the two cases for an n+type

surface.

101

For a p-type surface, a large positive voltage induces an inversion layer consisting of

electrons, at the Si surface. In this case the electrons are minority carriers, and as

described in Section 6.2.4. tmm ~ 0.01 - 1 sec. which is definitely not Within the

risetime of the pulse. Initial injection of charge into the Si02 conduction band,

therefore, takes place from Impurity sites and trap sites in the Si02. However, dunng

the decay tune of the pulse (dependent on the resistance and capacitance of the oxide;

Section 6.2.4), the surface has time to go into strong inversion, but the electric field

across the oxide would have decreased. For tmm ~ 0.01 secs., R0 x ~ 1016 Q and

Cox = 10-16 F, the effective voltage at strong mversion is =0.9 Yapp1· In addition,

the tunnelling factors which influenced d.c. breakdown thresholds would also be

present here, resultmg in an injection current lower than that with an n-type

semiconductor. The consequence is a higher breakdown threshold under the same

stress conditions. A negative voltage pulse would have a breakdown threshold

similar to that of an n+-type structure because the injecting electrode would be the n+

polysilicon gate. Therefore, the positive voltage breakdown threshold of p-type

structures would be higher than the negative thresholds. The more p-type the surface,

the higher the expected breakdown threshold. There is, however, the consideration of

oxide defects which do contribute electrons to the conduction process for the whole

duration of the pulse. If there are large enough numbers of these defects, 1t is

possible that they contribute sufficient electrons to reduce the breakdown threshold of

the ox1de.

6.6.3. Comparison with experimental results

6.6.3.1 Pulsed voltage stress conditions

The model explams the polarity dependence and the electrode dependence of the ox1de

damage. Impact ionization is a field-dependent mechanism and IS not significantly

102

affected by temperature. The temperature independence of the results is, therefore,

supported. The electric fields at which breakdown occurs, = 100 MV cm·l, are

sufficiently h1gh to proVIde electrons with energies of the order required to cause

avalanche multiplication in the Si02 conduction band (=16 eV).

The presence of defects in the oxide, close to the Si-Si02 interface, deforms the Si02

conduction band and enhances the prospect of electron injection directly into the

conduction band. This explams the higher breakdown sensitiVIty of MOS devices

with larger oxide areas.

6.6.3.2. Continuous voltage stress conditions

The mechanism presented for breakdown due to constant apphed voltages explains the

polanty effect and tlle electrode effect observed. The lower breakdown voltage,

compared to that under pulsed conditions, IS a result of the longer ttme penods

mvolved with continuous voltage stress. Sufficient charge can, therefore, be

conducted via defect states m the Si02 forbidden gap to cause breakdown. When the

temperature 1s rused, more electron traps are generated as a result of field-enhanced

thermionic processes. More electron conduction takes place and a lower breakdown

threshold is observed. Therefore, the temperature dependence IS explained by the

model.

Leakage currents measured were of the order of I0-9 A at =35 V, which is comparable

With a calculated current of= IO·ll A for a 400 A MOS structure, m an electric field of

= 109 V m· I. This is a reasonable comparison when additional factors wh1ch

contnbute to the leakage current, are considered. The calculation IS made usmg Eq

(6.17) of Section 6.5.3 ..

103

6.6.4. Comparisons with existing work

Exisnng work on oxide breakdown is beginning to show more in favour of the charge

injection model, as opposed to the field dependent model [72][73]. The experimental

data presented m this thesis is consistent with the charge injection model. The

mechanism of charge conduction proposed in the model for constant electric fields, m

this chapter, is in agreement With that proposed by Wolters [72]. The experimental

work showing the temperature dependence of the constant voltage breakdown

thresholds, can be favourably compared with the results of Harari [64]. The

agreement of the experimental data of the work, in this thesis, on continuous voltage

breakdown, with published work, lends confidence to the results obtained under

pulsed condinons.

The work on pulsed breakdown appears to be isolated; no literature was found on

experimental work on MOS structures, using pulses in the lQ-6 secs. to 10·9 secs.

range. The model is consistent with the charge mjection models considered for

constant voltage breakdown, while takmg mto account the higher electric fields

( ~ 1 OOMV cm·!) and the shorter dura non of the pulses. Impact ionization has been

refuted by some authors [72] for breakdown in continuous electric fields. However,

the fields under pulsed conditions are very much higher. Experimental work on

tunnelling through thin oxides [60], and theoretical work on high field effects at the

semiconductor surface [54][57], do tend to support the model proposed for pulsed

breakdown proposed in thiS chapter.

6.7. SUMMARY

1. The Silicon MOS structure has been descnbed with respect to !IS physical

properties properties, energy bands and electronic conduction processes.

104

2. Qualitative models have been presented for Si02 breakdown, under continuous

and pulsed conditions. These models are based on existing solid state physics

theory and are supported by the experimental data in Chapter 4.

Continuous voltage conditions

3. OXIde breakdown under continuous voltage stress is the result of charge injecnon

from the Si surface or the n+ polysihcon gate. Charge injection at the Si-Si02

interface takes place by quantum mechanical tunnelling through the potennal

barrier, or, by themnomc excitation over it Electrons may tunnel directly into the

Si02 conduction band or into traps and Impurity sites within the Si02

bulk/interface. C-V plots suggest that tunnelling to trap/impurity sites is more

likely than tunnelling directly mto the conducnon band.

4. Once m these trap sites, electrons are able to move further mto the oxide by means

of the Poole-Frenkel effect. Emission over the barriers presented by the

Coulombic potential wells at these sites.

5. n-type silicon can inject more charge mto Si02 than p-type Silicon, because of the

positions of the Femn levels and the greater probability of tunnel emissiOn at the

surface.

6. Since the Si02 conduction process under d.c. voltage stress, is thermiomc, 1t IS

temperature dependent. In addition, combined temperature and field effects can

generate further trap sites by affecting any weak bonds m the Si02.

Pulsed voltage conditions

105

7. Pulsed voltage breakdown is initiated by direct tunnelling of electrons from the

cathode into the Si02 conduction band. There they undergo impact Ionization

through collision with the lattice, causing an avalanche multiplication of electrons

in the conduction band.

8. When the injecting surface is in accumulation, the very fast response times of

majonty carriers enables them to contnbute to the impact ionization process within

the risetime of the applied pulse.

9. When the mjecting surface is in inversion, the response time is very much slower

than the risetime of the pulse, and the effective electric field in strong inversion is

lower than the actual applied voltage pulse. Also, the tunnelling probability from

invened surfaces IS less than that from accumulated surfaces for the same applied

voltage.

10. Tunnelling into the Si02 conduction band can be enhanced by resonance

tunnelling in oxide trap sites, suggesting that defects will influence breakdown

under pulsed voltage conditions.

11. The actual breakdown mechanism IS a result of the collision of electrons,

travelling in the Si02 conduction band or between defect sites, with the Si02

lattice. Energy is transferred from the electrons to the lattice by means of

phonons.

12. The breakdown process under pulsed voltage conditions is not influenced by

temperature. This is supponed by the experimental data on MOSFETs presented

in Chapter 4.

106

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109

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110

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Ill

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113

CHAPTER 7

DISCUSSION AND CONCLUSIONS

7.1 INTRODUCTION

Chapters 2 to 6 have identified and examined failure mechamsms in semiconductor

devices with detailed work being particularly related to the effects of electrical

overstress in MOS devices. The purpose of this chapter is to show the unified namre

of the approach used in tackling this project. Major points made in each chapter are

emphasised here and discussed m relation to this proJeCt as a whole.

In Chapter 2, the pnncipal failure mechanisms in semiconductor devices were

identified by means of a combined literature and industrial survey. Chapters 3, 4 and

5 detail experiments conducted into the most common fmlure mechanism, namely

Electrical Overstress/Electrostatic Discharge Damage, with a view to gaining a deeper

understanding of the physical processes involved in the damage. A model of the

breakdown mechanisms is described in Chapter 6 enabling the analysis to be extended

to predict the influence of sirmlar stress factors on other types of MOS devices.

7.2. SURVEY ON FAILURE MECHANISMS IN

SEMICONDUCTOR DEVICES

As a result of this survey It became evident that although many failure mechanisms

exist, one mechanism dominated device rehabihty. Over 50% of all failures both in

the field and m laboratory lifetests were related to EOS/ESD. Although listed as an

event- dependent fmlure mechanism, EOS/ESD has become of increasmg concern to

114

------------------------------------------------------------

both sennconductor and equipment manufacturers because of the complex, state-of­

the-art applications required of sennconductor devices in modern industry. Solunons

to the problem were centred on protection circuitry capable of dJ.ssipanng any excess

voltages (within the design limits of the protection circuit) before they reached the

deVIce stress points. Therefore an area in need of further research was revealed.

A study on failure mechanisms could not be totally divorced from the concepts of

reliability modelling and reliability assurance. Analysis of these topics led to the

conclusion that reliability modelling must be considered purely as an indicator of

device reliability. The uncertainty factors involved in any mathematically-based model

made a mockery of the very precise reliabihty figures provided by these models.

Similarly, conditions under which laboratory lifetests were conducted and the methods

used m extrapolating the data to real time-scales and operating envrronments, meant

the figures obtained should only be used as a gmdeline to device reliability.

Furthermore, particular applicatiOns favoured particular models, and data obtained

from an environmentally bemgn model such as those developed for telecommunication

or computer applicanons, may bear no relationship to actual failure rates of deVIces

used m the automobile or aircraft industry. It becomes apparent that a universal

model, such as that presented in MIL- HDBK-2170, must necessanly be pessimistic,

and even heavily pessimistic, when applied to less demanding environments,

compared to actual failure data.

Increasing complexity in integrated circuits and the large number of functions they are

required to mcorporate, make it very difficult to "test-in" quality. In fact it has been

increasmgly acknowledged that "test-m" quality was both uneconomical and

nnpracncal. The solution is "built-in" quality, or the principle of "genmg-It-nght-frrst­

nme". This requrres that the enure workforce from the management levels downwards

must be committed to producing good devices first time. Furthermore, close

115

cooperation between the consumer and the device manufacturer, can ensure that more

complex devices are functionally tested for the specific purpose for which they are to

be used. Such a policy would reduce test costs and also provide a higher guaranteed

reliability to the consumer. Fmally, there is the trend towards "design-for-testability"

whereby chips are designed with funcnonal test programmes in mind. On the whole 1t

appears that the problem of testing complex i.c's may prove to be one of limitation by

the actual size of an integrated circuit. The advent of automatic test equipment should

phase out the human mterface on the semiconductor device production line, and

therefore increase the quality of manufactured devices.

In order to rruse the inherent reliability of a semiconductor device it is necessary to

understand and eliminate the fa1lure mechanisms which affect that device. This

requires a knowledge of the physics of the frulure process u the whole thing IS not to

become a black art An understanding of failure physics also enables predictions to be

made of the possible effects of any changes in the dev1ce structure or fabrication

techmques on deVIce performance and reliability. Hence, it becomes poss1ble to

evaluate devices which can be considered to snll be in their infancy, as far as the

manufacturing technology is concerned, With regard to therr behaviour under various

stress conditions.

7.3. EXPERIMENTS ON CONTINUOUS AND PULSED

VOLTAGE STRESSING OF MOS STRUCTURES

7.3.1. Pulsed voltage stressing of enhancement mode n-channel

MOSFETs

Breakdown threshold voltages under pulsed (or ESD) stress conditions are not well

defined quantities. Because of the number of factors mfluencmg breakdown,

116

parncularly Wlth regard to the mechanisms involved in the breakdown process, it is

possible for identical devices to respond differently to a gtven ESD pulse. However,

taken over a large sample size, disnnct trends can be observed which enable the overall

response of a given device type to be established.

The main conclusions drawn from this experiment were that ESD damage in discrete

enhancement-mode n-channel MOSFETs was

(i) Voltage dependent

(iJ.) Temperature independent

(in) Dunension dependent

It was also observed that sequential pulsing mcreased the degradation m damaged

devices and eventually resulted in catastrophic fru.lure, although the extent of the

degradanon after each pulse could not be predetermined.

The unplications of this work are sigmficant, and these experiments can be looked

upon as a springboard from wh1ch an m- depth mvestlganon into the physics of

EOS/ESD damage can be launched. Firstly, the mechanism involved in pulsed voltage

damage, which in most cases is due to high voltages (up to 20kV, but usually around

100 V) with risettmes between I0-8 secs. and I0-6 secs. is that of impact 10mzation.

Therefore, when considering ESD senslttVlty of dev1ces, 1t becomes necessary to

consider the influences of the stress factors whatever they may be, on the breakdown

process, which includes the tunnel injecnon of earners into the Si02 from both the Si

and eXlsting ox1de defects. To this end, minirmsing the number of traps during the

fabncation of thermally grown oxides, could mean lower ESD sensittv1ty. Secondly,

the degradation effect on the devices is important. It was observed that degraded

devices had electrical charactenstics which would have passed screening tests based

117

on a pass/fail system. However, these devices were now able to contnbute to the

scores of latent failures which usually occur dunng their operational life. Sequential

pulsing of damaged devices confirmed that this could happen. Many field failures

attributed to EOS could well have originated with latent ESD damage [1]. A thrrd

factor was highlighted by the temperature independence of the damage. Experimental

work on packaged i.e.'s have found that the input protection crrcuit introduces a factor

affecting reliability which is not present in

the device itself, i.e. the temperature dependence [2]. Therefore, if the breakdown

mechanism can be mhiblted either by improved fabrication techmques [6] or by

changing the MOSFET structure to reduce high field charge injecnon into the oxide,

then the improved i.e.'s will be more economical (no large input protection circuit) and

have comparable or even better reliability than present i.e.'s.

7.3.2. Pulsed voltage stressing of other MOS structures

The arm of these experiments was to expand the pulsed voltage breakdown analysis to

cover all standard MOSFET structures. Although p-channel depletion mode

MOSFETs were not available, results from the other three structures are extrapolated

to predict the behaviour of these deVIces under similar stress.

Essentially, both the D-mode n-channel MOSFETs, and the E-mode p- channel

MOSFETs showed degradanon behaviour of similar nature to that observed in E-mode

n-channel MOSFETs. The trend towards degradation 1s very sigmficant, and smce the

proposed breakdown models forE-mode NMOS transistors do apply to these devices

as well, such a large sample size was not required m order to evaluate their behaVIour

under the vanous stress factors. E- mode p-channel MOSFETs that were subJected to

ESD pulses showed degradation charactenstics very smular to the E-mode n-channel

MOSFETs. A lower Ios was observed for a g~ven V os at the same gate voltage.

118

Degradation characteristics in D-mode n- channel MOSFETs vaned slightly because of

the implanted inversion-layer already present in the channel as discussed in Chapter 5.

The polarity dependence of pulsed breakdown was observed in experiments on MOS

gate-oXIde capacitor structures on the same wafers as the MOSFETs. Positive voltage

breakdown thresholds were twice the negative voltage breakdown thresholds for p-Si

capacitors. n-Si capacitors showed about 50% larger positive voltage breakdown

thresholds compared to the negative voltage breakdown thresholds. For n+-SI

capacitors the difference in breakdown thresholds was almost negligible. In all cases,

the breakdown thresholds with negative voltage were about the same ( -1 OOV) while

the positive voltage breakdown varied according to the type of semiconductor. This

sigmfied a dependence on the dopant concentration in the silicon. Results with

continuous voltage (d. c.) stressing confirmed that this was indeed the case.

Capacitors were also subjected to positive ESD pulses below their known

(experimentally determined) breakdown thresholds, and C-V curves made.

Comparisons with C-V curves made before applicanon of the pulse showed that:

(i) in the case of the p-Si and n-Si capacitors, no noticeable change had occurred,

Withm the bounds of expenmental accuracy.

(ii) n+-Si capacitors had a very much higher minimum capacitance than before the

applicanon of the pulse.

The latter result indicates that charge trappmg has taken place at the Si-Si02 interface,

which, with larger pulses, will enhance the prospect of oxide breakdown. The fact

that no change was observed in the NMOS deVIces, together With therr higher posiove

breakdown thresholds, implied that the injection of earners into the oxide was

important to the breakdown process.

119

7.3.3. Continuous voltage stressing of MOS Structures

The very short duranons of the pulses (=l0-7 secs) meant that the breakdown

mechanisms were time-independent. Under time-dependent continuous (d.c.)

voltage condinons different mechanisms become important, and different breakdown

thresholds may be expected. Experimentally, d.c. stress on MOS capacitors showed

that this was indeed the case. The breakdown thresholds with both posmve and

negative voltage stresses were m the region of 35 V, almost five times less than the

pulsed thresholds. A polarity dependence was still observed, however, as a funcnon

of the semiconductor dopant concentration. The p-Si capacitors showed symmetrical

Ileak vs. V appl curves, whereas n-Si capacitor curves were less symmetrical, and the p-

SI capacitors were very much asymmetrical. Carrier injectiOn was still, therefore,

important to the breakdown process. The significant temperature dependence was m

agreement with the nme-dependent nature of the stress voltage, and indicated that the

breakdown process was related to thermionic conduction processes withm the Si02.

Thus the breakdown mechanism was concluded to be due to hoppmg conduction via

!tupurity sites and electron traps in the oxide. Defects of th!s kind could be generated

by the lugh fields (=107 V cm-1) and enhanced by htgh temperature (=200°C), by

which weak Si-Si or Si-0 bonds could be dissOCiated.

"Freeze frame" pictures of the breakdown processes were obtamed by making C-V

plots after applying voltage stresses below the breakdown thresholds. Shifts in the

capacitance mmima and distortion of the curve confirmed that traps did have a

significant role in the breakdown mechanism.

7.4. THE OXIDE BREAKDOWN MODELS

120

7.4.1. Theoretical analysis

The theoreocal analysis presented in Chapter 4, is based on two aspects of the high­

field behav10ur of MOS structures. Charge injection at the oxide mterfaces and

electronic conduction process in the oxide itself. While the actual theorencal

backgrounds of the subjects have been well developed, therr effects on the oxide have

always been considered in isolation of each other. The qualitaove models presented

earlier in this work consider the two phenomena as mteracong to cause high field

oxide breakdown. In essence, electrons are injected into the oxides, either at the oxide

interfaces or from donor impurity Sites within the oxides, by tunnelling or thernnomc

field emission (i.e. Poole-Frenkel effect). Conduction through the oxide can either be

directly in the conduction band, or by hopping between impurity sites in the Si02

forbidden gap.

The models are based on the expenmental data in Chapter 4. The trme-dependent

feature of the pulsed voltage stress was also considered together with the time­

dependence of d.c. breakdown. Hence, the model also mcludes minority/majonty

carrier response nmes in the silicon, the thermal generation of defects and thermally­

acovated emission from defects in the Si02.

Quantum-mechanical tunnelling theory shows that the tunnelling probability is

dependent on the transmission coefficient at the barrier, and also the supply function,

i.e. the number of electrons avrulable for tunnelling. High electnc fields cause severe

band-bending at the surface, leading to energy quantisatlon effects at the

serrnconductor surface which influences the transmission coefficient. The extent of

the band-bending vanes for different dopmg concentranons m the silicon. This means

that the supply function for an n-type Silicon surface will be higher than that of a p-

121

type surface, thus influencing the amount of injected charge in p-Si and n+-Si

structures under Identical stress factors.

The influence of the Fermi level on the injection of charge to interface states was

considered. Since the energy levels of the interface states extend uniformly across the

forbidden gap of silicon, the higher the Fermi level, with respect to the valence band,

the greater probability there is of these states being occupied. High electric fields

under d.c. conditions cause these earners to be enutted to traps further in the oxide

bulk, leavmg empty states, thereby enhancing the probability of charge injection at the

interface.

Oxide traps are also known to increase the probab1hty of tunnelling. Resonance

tunnellmg, whereby, traps affect the electronic wave function, means that ox1de

defects conmbute to the charge injection and conduction process in Si02 and lower the

oxide breakdown thresholds.

7.4.2. Model of oxide breakdown under pulsed voltage stress

In modelling pulsed breakdown, the effect of the applied voltage on the silicon surface

becomes an Important consideration. Two states are poss1ble under high field

conditions;

(i) the surface IS in accumulation

(ti) the surface IS in mvers10n

Since then+ polysJI!con gate has a very large concentration of electrons (= 1021 cm·3)

charge injecnon with negative applied voltages can be considered identical to that of an

n-type surface in heavy accumulation. Positive voltage pulses w11l see different

122

behaviour from surfaces in heavy accumulation (n-type) and surfaces in heavy

inversion (p-type ).

Upon application of a large positive voltage pulse to an MOS device, for an

accumulated surface (n-type silicon) the majority carrier response nme is Important.

Smce this is very fast ("'l0-12 secs.) the surface charge will respond almost

instantaneously to pulses in the region of l0-7 sec. risetimes. Charge injection into the

OJade then takes place, and the field at breakdown ("'109 V cm-1) causes electrons to

be injected directly mto Si02 conduction band. Here the electrons gain sufficient

energy from the electnc field to cause Impact ionization which leads to lattice heanng

and eventually breakdown. The time scales involved in this process are very short.

Impact ionization to breakdown proportions is possible in <10·9 secs.. This is well

Within the risetimes of any standard ESD pulses. It is also possible that the high

electric fields can cause trapped electrons to tunnel through the coulombic potential

barriers into the SiOz conduction band and contribute to the breakdown process.

Inversion in p-type devices requires mmority carriers to respond to the applied voltage

pulse. The response times of mmority carriers is slow compared to maJority earners,

typically about I0-3 secs. Therefore, when the surface is in strong mversion, the

effective voltage across the oxide would have decreased ("'0.9 VappJ). Tunnelling

probabilities and field ermss10n will be less than in an accumulated device with the

same surface conditions and the breakdown threshold is mcreased. Impunties and

trapped electrons in the bulk oXIde will however snll be able to tunnel through to the

oxide conduction band, as in the accumulated case, and therefore can mfluence

breakdown if available m sufficient quannnes.

7.4.3. Model of oxide breakdown under continuous voltage

stress

123

Under d.c. voltage stress, electrons quantum-mechanically tunnel from the Silicon

electrodes into the oxide. The tunnel current is dependent upon the surface charge

concentration, higher injection being obtained With more n-type surfaces. Conduct:J.on

through the oxide is by hopping via impurity sites and electron traps m the bulk oxide.

Hopping conducnon is a therrnionic field-enhanced mechanism indicating that the

breakdown threshold IS lowered under high temperature and high voltage conditions.

The thermal energy gained by the lattice under high fields can result in dissociat:J.on of

Si-Si, Si-0 and 0- 0 bonds at weak points in the lattice, generat:J.ng more defect Sites

[5][9][10]. Such a process would have a finite lifetime(> 1 sec), but under d.c. stress

conditions the time scales would be long enough to encourage defect generation

[7][8].

Breakdown in the d.c. case, therefore, takes place due to a combinat:J.on of impact

10mzanon and hopping conducnon. Electrons may tunnel directly from the Silicon

conduction band to the Si02 conduct:J.on band, but are most likely to tunnel to trap Sites

close to the Si-Si02 interface and to travel through the oxide by hopping conducnon.

The number of defects in the oxide play a considerable role in the breakdown process,

and a lower number of defects would mean a lower oxide conduction current, and a

higher breakdown threshold.

7.5. FUTURE WORK

Future work can be described in three areas;

(i) invest:J.ganons m to pulsed voltage breakdown effects,

(il) quantitative modelling of the oxtde breakdown mechanisms,

124

(iii) experimental verification of the predicted breakdown effects in silicon submicron

MOSFETs.

(I) Investigations mto pulsed voltage breakdown effects

Analysis of the pulsed breakdown mechanisms showed that MOS damage was related

to the silicon dopant concentration as well as the majority/minority carrier response

times at the surface under pulse conditions. The influence of oxide defects on

breakdown thresholds is also of importance. Future work would focus on these

effects.

Experimentally, the majonty/minonty carrier response times could prove to be a

limiting factor in pulsed breakdown. For instance, a positive voltage across a p-type

MOS capaCitor achieves full mverswn after ,().01 secs. Therefore the actual rise time

of the pulse ( < 10-6 secs.) is not important, while the decay time does become

important. Extending this theory to p-n Junctions, it will be possible to evaluate the

necessity in obtaining very fast risetimes in ESD test equipment and the mfluence of

faster risetimes on breakdown mecharusms. Since, pulsed breakdown is attributed to

impact ionization, the time required to generate sufficient secondary electrons to initiate

breakdown could also be sigmficant. Therefore It may be that a pulse with a very fast

nsetime ( < lQ-12 secs.) does not result m breakdown unnl well into the decay period.

The influence of oxide defects on pulsed breakdown can be mvesngated further.

Exammmg the pulsed sensitivity of devices with oxides of different defect

concentrations ranging from high to very low (e.g. radiation hardened) would enable a

more quantitative understanding of the effects to be gained. Methods of reducing the

pulsed sensitivity of MOSFETs can be analysed. Such methods would mvolve

reducing the probability of charge injection at the Si-SiOz interface. To achieve this it

125

would be necessary to either increase the Si-SiOz work function perhaps by

introducing an intermediate material at the Si-Si02 interface or by moving the

conductmg channel to the device bulk (a two-dimensional epitaxial interface, still

Influenced by the gate potential is a highly speculative possibility). Improving the

integnty of the oxide by reducing the number of defects, as is currently achieved in

radiation-hardened structures could increase deVIce reliability to EOS/ESD. Possible

defects caused by ion implantation, for example, could be mmimised by using a pre­

Implanted oxide layer. The effectiveness of such techmques would need to be

experimentally proven on test samples.

(ii) Quantitative modelling of the oxide breakdown mechamsms.

The models presented in this thesis are qualitative in that they do not lay a

mathematical base for the breakdown mechanisms. A quantitative model would

include mathematical treatment of the tunnelling equations to the Si-Si02 interface as

well as between trap-sites Within the oxide. Coupled with analysis of the Poole­

Frenkel effect under these conditions it will be possible to obtain mathematical

expressions capable of predicting breakdown voltages for given MOS structures,

under both pulsed voltage and continuous voltage stress conditions. Silicon dopant

concentrations, oxide defect densiues and device dimensions should all be

incorporated in the final expressiOn for the breakdown threshold.

Expenmental venfication of these calculauons should comcide with the results

presented in this work for the type of deVIces used here.

(iii) Expenmental verification of the predicted breakdown effects in szlicon

suhmzcron MOSFETs.

126

The predicted breakdown effects in submicron MOSFETs, as outlined in Appendix 3,

could not be venfied because of the unavailability of suitable samples. Small gate

dimension capacitors With varying silicon dopant concentrations and submicron size

MOSFETs would be requrred to obtain confrrmatton of the predictions. This work

could obviously be considered as an extension of (i), the samples being used for both

experiments. The quantitative model outlined in (ii) above would also be supported by

expenmental work on submicron MOS devices.

7.6. SUMMARY

1. A survey of the most common failure mechanisms in semiconductor devices was

made. EOS/ESD damage was found to be the most frequent cause of failure

accounting for over 50% of all observed damage.

2. The effects of EOS/ESD damage on MOSFETs were studied using continuous and

pulsed voltages simulating the stress conditions. Hence 1t was possible to identify

the physical processes involved m the breakdown mechanisms in these conditions.

3. A qualitative model of oxide breakdown in MOS structures was developed, based

on the experiments. Two different mechanisms were proposed for continuous and

pulsed voltage breakdown.

4. Continuous voltage breakdown is the result of hopping conduction of charge

carriers through the oxide, v1a electron traps and impurity sites. The mechanism IS

both voltage and temperature dependent

5. Pulsed voltage breakdown IS the result of electron conduction in the Si02

conduction band, having been injected directly into the band v1a quantum-

127

-- ------

mechanical tunnelling. Impact ionization and avalanche mulnplicanon of carriers

under the high electric fields then leads to breakdown. The mechanism is voltage

dependent but independent of temperature.

6. Both mechanisms were found to be dependent on the surface charge concentration

at the Si02 interface and therefore polarity dependent. The charge injection

process mto the SiOz is important to the breakdown mechanisms.

7.7. REFERENCES

1. ENOCH R.D., SHA W R.N., Event-dependent ESD behaviour of bipolar

integrated circuits - Proc. ERA Sennnar on Electronic Discharge Damage m

Electrorucs, pp. 4.1.1-4.1.9, 1986.

2. HART A., TENG T.T., McKENNA A., Reliabilzty znfluences from

electrical overstress on LSI devices - 18th Ann. Proc. Re!. Phy. Symp., pp. 190-

196, 1980.

3. FRANK D.E., Please keep your EMC out of my ESD - Proc. Ann. Re!. and

Mamtainability Symp., pp. 290-294, 1986.

4. KIM S.U., Charge trapping, interface state generation and intnnsic breakdown

m thm oxide under h1gh field.- 36th Elec. Comp. Conf., pp. 395-398, 1986.

5. NING T.H., OSBORN C.M., YU H.N., Electron trappzng at positively

charged centers zn Si02.- pp. Phys. Lett. 26, pp. 248-250, 1975.

6. For example see CO HEN S.S., Electrical properties of post-annealed thin Si02

films - J. Electrochem. Soc., 130, pp. 929-932, 1983.

7. HARARI E., Dielectric breakdown in electrically stressed thznfilms in thermal

Sz02 - J. Appl. Phys., 49, pp. 2478-2489, 1978.

8. NING T.H., Thermal remission of trapped electrons in SiOz. - J. Appl. Phys.,

49, pp. 5997-6003, 1978.

128

9. WOODS M.H., WILLIAMS R., The nature of hole-traps 1n Si02 . - J. Appl.

Phys., 47, pp. 1082-1089, 1976.

10. NGAI K.L., WHITE C.T., A model of interface states and charges at the Si­

Si02 interface: Its predictions and comparzsons wzth experzments. - J. Appl.

Phys., 52, pp. 320-337, 1981.

129

APPENDIX 1

SPECIFICATIONS OF WAFERS No: 1 AND 2

1.1. WAFER No: 1 - PRINCIPAL PROPERTIES

1. Diameter of silicon wafer

2. Material

3. Orient at ion

4. Resistivity

5. Field implant

6. Implant Boron

7. Implant Phosphorous

8. n• doping

9. Fteld Oxidation

10. Gate Oxide (thermally grown)

11. Polysiltcon gate (n+ implanted)

12. Metallisat~on

13. Passivation

14. Anneal

15. Strtp resist using fumin~ HN03

16. Correctton factor to channel

= 3 inches

= p-type

= < lOO>---­

= 20 n cm

= Boron B+

= 4.0 x 1olS cm-~

= 1·0 x 1ol' cm-~

= ).0 x loll cm· 3

= 0.5 to 0.7 pm at 900'C

= 425 A at 950 'c

= 4552 A at 620 'c

= Al sputtered, 1.5Z Si/Al/Cu

: Silicon Glass (SILOX),

10485 A at 400 'c

= 425 'c

length due to dopant diffuston (~)= 1.067 pm

17. Correction factor to gate width

due to field oxide inset ~W)

130

= 1.512 pm

18. Threshold voltage varies between

0.75 volts and 1.38 volts

depending on dimension

19. Junction depth = 0.4 ~m

20. Capacitors; polysilicon (n+) -gate oxide - silicon;

Area = 49.0 x 103 ~2

Periphery = 910 ~

21. Transistor dimensions are shown in TABLE Al.l.

131

1

2

3

4

5

6

7

8

9

10

11

w L

1.4 1.4

w L

I. 4 w 2. 1 L

1.4 w 2.S L

I. 4 W I • 4 w 3. 2 L 3. 5 L

2 .I W l .4 L

2.1 w 1.4 2.1 L 102.')

~~---~

IL 2.5 IL

2.1-rw--;-~ ---2.-5-rw· -;-~-~-- 2.5

3.2 IL 3.5 IL 1.4JLL 2.1 L 2.5

w L

2.5 Tw-- 2~1 3.2 IL 3~

'-~-----~-:-~--~~~~----~-:-~--~~~----~-:_;~~-~----1~:; ~~--2-~_:_~-~-~----~-:-~~~----2-3_:~--L~--1-o_~_:_!_J w L

w L

w L

w L

w L

w L

w L

w L

3.2 2.5

3.5 3. 2

4.2 2.5

4.6 2.5

10.2 2.5

102.9 2.5

2.5 3.5

2.5 10.2

w L

w L

w L

w L

w L

3.2 w 3.2 L

3.5 3.5

4.2 3.2

4.6 3. 2

20.7 2.5

w L

w L

w L

w L

3.2 w 3. 5 L

3.5 4.2

4.2 3.5

4. 6 3.5

w L

w L

w L

3. 2 w 4.2 L

3.5 4.6

4.2 4.2

5. 3 2.5

w L

w L

w L

3.2 w 4.6 L

3. 5 6.3

4.2 4.6

6.3 3.5

w L

w L

w L

3. 5 w 1. 4 L

3.5 10. 2

4.6 4.2

10.2 3.5

w L

w L

w L

3.5 w 2.1 L

3.5 2.5

3.5 20.7

4.6 4.6

10.2 10.2

w 3. 5 L 102.9

w 4.6 L 102.9

w 10. 2 L 102.9

20.7 3.5

w 102.9 L 1.4

w 102.9 L 2.1

w 102 9 L 5 3

w 102.9 L 20.7

w 20.7 L 102.9

w 102.9 L 3. 2

w 102.9 L 3. 5

w 102.9 L 4.2

w 102.9 L 4.6

w 102.9 L 6.3

w 102.9 L 10.2

w 102.9 L 102.9

V..' 3. 2 w L 3. 5 L

w 3. 2 w L 10. 2 L

3.5 w 3. 5 L

3.5 w 10.2 L

4. 2 w 3. 5 L

4.2 w 10.2 L

TABLE Al.l.

4.6 w 3.5 L

4.6 w 10.2 L

6.3 w 10.2 w 102.~ 3.5 L 3.5 L 3.5

6.3 w 10.2 w 102.9 10.2 L 10.2 L 10.2

Gate width (W) and gate length (L) dimensions of a block of transistors on a chip in Wafer No: 1.

132

1. 2. WAFER No: 2 - PRINCIPl.L PROPERTIES

1. Diameter of silicon wafer

2. Material

3. Orientation

4. Resistivity

5. Field Implant

6. n-channel, implant Boron

p-channel, implant Arsenic

7. Source/Drain doping, Boron (p+)

8. Field Oxidation

9. Gate Oxide

10. Threshold voltage for

PMOS is approximately

11. Junction Depth, n-channel

p-channel

= 3 inches

= n-type

= < lOO >

= 25 Q cm

= Phosphor~s ,,p+

= 1 x 101'5 cm->

= 1 x 1ol!i cm-;

= 5 x 101'1 cm-3

= noo A

= 320 A

= - 0.8 volts

= 0.35 I""

= 0.7 I""

12. Capacitors; polysilicon (n•) - gate oxide-silicon,

Area

Penphery

: 4.9 X 103 1""2

= 280 I'm

13. MOSFET Dimensions are as shown in TABLE Al.2.

133

P1

Nl

P2

Nl

P3

N?>

P4

N4

w 20.0 w 20.0 w 20.0 w 20.0 w 20.0 w 20.0 w 20.0 w 20.0

L 1.0 L 1.25 L 1.5 L l. 75 L 2.0 L 2.25 L 2.5 L 3.0

w 2.5 w 2.5 w 2.5 w 2.5 w 20.0 w 20.0 w 20.0 w 20.0

L 1.25 L 1.5 L 2.0 L 2.5 L 20.0 L 7.5 L 5.0 L 3.5

w 1.0 w 1.25 w 1.5 w l. 75 w 2.0 \'1 2.25 w 2.5 w 3.0

L 10.0 L 10.0 L 10.0 L 10.0 L 10.0 L 10.0 L 10.0 L 10.0

w 1.5 w 1.5 w 1.5 w 1.5 w 20.0 w 10.0 w 5.0 w 3.5

L 1.25 L 1.5 L 2.0 L 2.5 L 10.0 L 10.0 L 10.0 L 10.0

TABLE Al.2.

Gate width (H) and Gate Length (L) dimensions in ].lm of a block of MOSFETs on chip on Wafer No: 2. Pl, P2, P3 and P4 are p-channel devices. Nl, N2, N3 and N4 are n-channel devices.

134

I <!>

t

APPENDIX 2

SOLUTION OF THE SCHROEDINGER EQUATION FOR TUNNELLING

AT A POTENTIAL BARRIERl-4

V (x) e

X

'-........

6cj> '-

.........

V m

------------ ..::... -E EF X

' ... X

FIGURE A2.1 - A metal-dielectric interface, showing Lmage force

lowering under an applied electrLc field. EF is the

metal FermL level, ~ lS the potential barrier at the

interface and Ex is the energy of the tunnelling

electron

The 1-D time-independent Schrodinger Equation for the metal-dielectric

interface shown in Figure A2.1. is given by:

135

+ { V (x) - Ex 1 1/1 = 0 Eq (A2.1)

where

V ( x) = - Fx - !]> Eq (A2 .2)

F is the applied electric field,

!]> is the barrier lowering due to the image force at the interface.

!]>= Eq (A2 .3)

where e is the permitt1vity of the dielectric

Solving for 1/J (x) from Eq (A2.1)

1 X < 0

= r{si(-y) + Ai (-yl1 1 X > 0

Eq (A2.4)

where

1/2

Eq (A2.5)

136

and

( +X) al/2 ( E- q ~)

y = q F Eq (A2.6)

2m q F a =

1\2 Eq (A2.7)

The functions Ai(-y) and Bt(-y) are two real linearly independent

solutions to Airy's equation.

The probability current normal to the interface is given by

j11

{ f oj* f'__:!_1 p = 2m ox ox

Eq (A2.8)

h kx I 2 = T nm

The transmission probabiltty, D, of the barrier is defined as the

ratio of thts current to the probability current P0 = 1i.k/m in the

incident plane wave.

137

For a triangular barrier,

p

Eq (A2.9)

The current per unit area can be written as

J l 0

Eq (A2.10) =

where,

N (Ex) d Ex is the supply function representing the number of

electrons in the energy range (Ex, Ex+ d Ex) which are available for

tunnelling through the barrier. Assuming that all electrons escaping

from region I are swept away by the field tn region 2.

This leads to the tunnelling current, calculated following the

conventional Fowler-Nordheim derivation and using bulk statistics4,

of

J = Am-2

Eq (A2.11)

138

References

1. FOWLER R., NORDREIM L., Electron Emission in Intensive Electric

Fields

- Proc. Roy. Soc., All9, p. 173, 1928.

2. DUKE C.B., ALFERIEFF M.E., Field Emission through Atoms Adsorbed

on a Metal Surface

- J. Chem. Physics, 46, pp. 923-937, 1967.

3. O'DWYER J.J., The theory of electrical conduction and breakdown

in solid dielectrics; Clarendon Press, Oxford, 1973.

4. I<EINBERG Z.A., Tunneling of electrons from Si into thermally

grown Si02.

-Sol: St: Elec., 1Q, pp. 11-18, 1977.

139

APPENDIX 3

DEGRADATION MECHANISMS IN SILICON SUBMICRON MOSFETs

A3·1• INTRODUCTION

As device geometries get smaller, the properties of the devices

are affected by the changes in the structures and fabrication

techniques required to achieve optimum performance at smaller

dimensions. Very small dimension (VSD) MOS device can be classified

as devices with gate widths and length < 5 ~· It is at these sizes

that the electrical characteristics of the device begin to differ from

those expected of a standard device. Dimensions of less than 1 pm

constitute what are known as submicron devices. Silicon MOS submicron

devices are expected to form the backbone of the future generation of

semiconductor technology. Hence, an understanding of possible

degradation mechanisms, which may be introduced by the manufacturing

and design techniques employed, is important to their development.

However, due to the difficulty at present in obtaining devices

manufactured to submicron dimensions, much of the experimental work is

carried out on VSD devices and extrapolated to gate lengths and widths

of less than 1 pm. Accurate computer s imul at ion, necessarily

involving complex 3 - D numerical analys~s, is another means of

investigat~ng the behaviour of subm~cron structures. The data gathered

by these methods can be coupled with theoretical studies into the

physics of the devices and their properties, to enable the behaviour

to be effectively predicted under various operating conditions.

140

It is the intention in this chapter, to outline the principQl

mechanisms of degradation observed in VSD devices, and to apply them

to submicron silicon MOSFETs. Particular emphasis will be be placed

on the effects of the oxide breakdown mechanisms proposed in Chapter

b, on the behaviour of submicron MOSFETs under stress conditions.

Important features of submicron silicon MOSFETs are discussed in this

chapter. A brief description is given of three dimensional computer

simulation of VSD MOSFETs, and due to the difficulties in obtaining or

developing a suitable 3-D program for this project, published results

are presented. It then goes on to discuss known degradation

mechanisms caused by the small dimensions involved, and finally

extends the oxide breakdown analysis to submicron MOSFETs.

141

A~.2. IMPORTANT STRUCTURAL FEATURES OF VERY SMALL DIMENSION (VSD)

MOS DEVICES

A3·2.l. Dimensions

The gate dimensions of a VSD device are of critical importance to

the electrical properties of the devicel. Investigations into short

channel MOSFETs have shown, that with effective gate lengths of less

than 2 pm, the electric fields in the conducting channel can be large

enough under normal operating conditions, to cause degradation of

device behaviour2. Degradation occurs as a result of electrons gaining

sufficient energy (- 3.2.eV) to surmount the Si-SiOz interface barrier

(hot electrons) or, by means of punchthrough conduction whereby the

depletion regions of the source and drain are able to make contact

providing carriers with a low resistance path through the

device3,4,16,

The gate width has always been known to have an influence on the

electrical properties of MOS devices. However, the development of

three dimensional transistor modelling programmes has shown that at

widths less than 2 pm, the surface potential, electric field and

electron density in the conduction channel are affected by the gate

width5,29, This is because the fringing effect of the electric field

at the edges of the gate ox~de can no longer be considered negl~gible,

as the gate width approaches the depletion layer thickness in the

transistor.

The gate ox~de thickness is the third parameter of importance in

the transistor operation s~nce it influences the electric field in the

channel. Defect mechanisms associated with oxides ranging from 200 A

142

------------------------------------------

to 600 A have been discussed extensively in Chapter of this

work. Experimental data on 400 A ox1des has been presented in Chapter

{,. In this chapter, the models presented earlier will be extended to

VSD and submicron devices. High electric fields across the thin gate

oxides, can lead to quantization of the energy bands in the invers1on

layer at normal operating voltages6. Hence the electrons can be

considered to be confined to a two dimensional layer at the surface,

affecting electronic conduction properties and the electrical

behaviour of small dimensions devices22,23.

The shapes of the source and dra1n junctions are also of

importance in VSD devices. Diffus1on of the source/drain implants

under the gate can be quite considerable (- 0. 7 I'm) and will

influence the device behaviourl.

A;.2.2. Doping concentrations

In order that very small dimension transistors have the same

electrical performance as long channel devices, it 1s necessary to

increase the doping concentration. The exact increase is dependent on

the threshold voltages and conduction properties required and may be

two orders of magn1tude greater than that of a convent1onal

dev1cel,8,13. In addition the depths of the source and drain

junctions affect the punch-through voltage and in order to control

this, the energy of the source and drain implants must be reduced,

requiring higher dose rates for the dopant concentrations necessary.

Hot electron emission can be controlled by graded doping of the drain

and source junctions which aga1n adds further complications to the

fabrication techn1ques1,1,13

143

The effect of this heavy doping on interface states may be

significant, influencing the reliabLlity of the device. High dopant

concentrations will also contribute to surface quantization

effectsl,6,8,23.

It is also necessary to keep heat treatments and annealing steps

at low temperatures and as short as possible to minimize excessive

diffusivity of the implanted ionss.

144

A3 .3. COMPUTER SIMULATION OF SUBMICRON SILICON MOS DEVICES

A3 .3.1. SemLconductor device equations

The equations used in the simulation of silicon MOS devices are

the Poisson equation (EqA3.1), the current equations for electrons

(Eq. A3.2) and for holes (Eq A3.3) and the continuinty equat1ons for

electrons (Eq. A3.4.) and for holes (Eq. A3 .5.) in three

dimensions;9,10,Z6.

v2 V (x, y, z) = - p (x, y, z)

Eq <M.ll

= q Pn n F + q Dn Vn N

Eq (Al.2)

= q }lp p! - q Dp Vp Eq (A~. 3)

1 on Eq (A:\.4) = G - R

q ot

1 op + = G - R

q ot Eq (43.5)

where

p (x, y, z) = - q ( n - p + No - NA) Eq (~3.6)

145

is the total space charge in the semiconductor, n and p are the

electron and hole concentrations respectively, and No and NA are the

donor and acceptor concentrations respectively. V (x,y,z) is the

electrostatic potential.

!n and ;!p are the electron and hole current densities

respectively, while f'n and f'p are the mobilities. G describes the

generation rate incorporating impact ionization or carrier generation

by external radiation, while R describes recombination processes. F

is the electric field given by -~.V.(x,y,z). On and Dp are the

diffusion coefficients for electrons and holes respectively.

Poisson' s equation is derived from Maxwell 's Laws and describes

the charge distribution within the semiconductor as a function of the

electrostatic potential at any given point V (x,y,z) The current

equations define the absolute values, directions and orientation of

the electron and hole currents, while the continuity equations

characterise the balance of sinks and sources for electron and hole

currents.

The equations are solved using complex numerical methods based on

either Finite Element or Finite Difference techniques for parti~l

differential equations, to obtain a simulation of the charge

concentrations, potentials and electric fields in a MOS device

depending on the boundary conditionsl3. Figure M.l. shows the area

over which the equations are to be solved. The boundary conditions

are chosen according to the type of device being considered and may

vary depending on the '!10del9-12,26. Basically, charge neutrality is

assumed at the source and drain contacts which are considered ohmic,

as well as the substrate contact, giv1ng:

n - p + No - NA = 0 Eq (M. 7)

146

GATE OXIDE

Channel Dop1ng

-----

GATE ELECTRODE

/ _ ...... ' .....

" ........ Substrate

Rectangle over "h1ch Po1sson's Equation 1s to be solved

n• DRAIN

Deplet1on reg1on

--------

FigureA3-1 CROSS SECTION OF AN NMOS TRANSISTOR SHOWING THE AREA OVER WHICH POISSON'S EQUATION IS TO BE SOLVED BOUNDED BY THE THICK RECTANGLE

147

In thermal equilibrium

np = Eq (l3.8)

The electric displacement D is considered to be continuous at the ~

Si-SiOz interface, givtng

~ox = ~s Eq (A>. 9)

where E0 x is the electric fteld at the interface and e0 x is the ~

oxtde permtttivity. Ustng

E :-V. V Eq <M.lO) N

the electrostatic potential can be determined.

Vartous modifications have to be made to these boundary

condittons when applying the solutions to submtcron devtces, in order

to accommodate high-field phenomena and heavy doping effects as well

as the edge effects at the gate width5,12,26.

148

5.3.2. Simulation of very small dimension MOS devices

Very small dimension MOS devices have been successfully simulated

using three dimensional techniques to observe the effects of the gate

length and width on device performanceS ,10,12 • 30. Due to the

restrictions on the export of computer software of this nature from

the U'>A, the author has had to rely on published results to evaluate

the influences of small geometries on device behaviour. The high

complexity of the numerical analys1s and the extent of computer

programming involved made it impractical to develop a programme for

this project, here at Loughborough. The published results have

therefore been used 1n the rest of this chapter to form the basis of

the analysis into degradation in submicron devices presented here.

Three dimensional simulation of an n-channel small geometry (l ~

x 1 I'm) MOSFET device has provided results for the potential

distribution as a function of gate length and gate width as shown 1n

Figure 4~.25. The substrate voltage Vsub =- 3.0 V, gate voltage VGs =

0.9 V and the drain-source voltage Vos = 2.0 V. It can be seen that

the channel width does affect the potential distribution. The

effective channel width b not uniform along the channel length. being

wider near the source and then tapering off to a m1nimum at the

pinch-off point, widening again towards the drain. The width w1dening

effect at the source is attributed to the substrate b1as, Vsub •

although in the channel it is due to the width influenc1ng the surface

potential5,29. The electric field dependence on channel length and

channel width (Figure A3.3.) confirms the width influence. A decrease

in effective channel width causes a decrease in surface potential. At

149

the pinch off point the channel width is at a minimum and hence the

total electric field near the drain is a minimum as indicated by the

trough in Figure A3.3. However, the field in the vicinity of the drain

is extremely high under the biasing conditions (Vsub = 2.0 V, VGs =

1.6 V, Vos = 8.0 V).

Results for avalanche breakdown have shown the ionization

integral to decrease as the channel width got smaller. Hence the

avalanche breakdown threshold voltage was greater for smaller devices.

Punchthrough conduction is found to decrease at channel widths below

4.0 vm. This is attributed to a decrease in potential at smaller

widths with an increase in the potential barrier at the source to bulk

junction. Current flow is therefore reduced5,29.

150

FIGURE /l.j.2. The potential distribution in an MOS transistor in 3-D (ref. 5).

FIGURE A~3. The electric field distribution in an MOS transistor in 3-D (ref. 5).

151

A3.4. THE EFFECTS OF VOLTAGE STRESS ON SUBMIC~ON MOSFETS

A3.4.1. Introduction

In this section it is proposed to use the understanding of

submicron MOSFETs gained by computer simulation (as described in

section A3.3.2.), in conjunction with the understanding of oxide

breakdown mechanisms described in chapter (, , to predict the

effects of voltage stress on submicron MOSFETs. Degradation

mechanisms caused by stress in the lateral direction, i.e. Vog, will

be briefly discussed with regard to published results, for

completeness.

A3.4.2. Lateral field effects

F1gure ¥>. 4 shows a typical distribution of equipotentials in an

n-channel MOSFET under the influence of a positive Vns• with Vcs > o4.

Electric field lines and current flow will be in a direction normal to

these equipotentials. Therefore, it~n be seen that the highest

electric fields are obtained close to the drain and along the

semiconductor surface. As device geometries get smaller and electric

fields get larger, three main effects influence degradat1on mechanisms

in MOSFETs.

(i) Avalanche breakdown through carrier multiplication at

the large drain-substrate reverse-~sed junctionlS.

(ii) Punchthrough conduction and drain induced barrier

lowering due to interaction of the large depletion regions

• 1&,11-at the dra1n and source

152

SOU'l.CE

'0 28 V

FIGURE p.J.4. The potential distribution in a MOSFET under the influence of a drain-source voltage (v

05)

153

(iii) Hot carrLer effects where electrons or holes may gain

sufficient energy from the drain-source electric field

to surmount the potential barrier at the Si-SiOz

interface.

Degradation of device performance occurs as a result of interface

state generation which affects the properties of the conduction

channel. Extensive work has been carried out into hot electron and

hot-hole effects and methods of improvement in small geometry

devices2,7,18-20,27,28.

Avalanche breakdown and punch-through conduction in very small

dimension devices has been briefly discussed in the previous section

(l\3.3.2.) Hot electron effects are believed to be reduced, as the

channel length decreases below about 5 ~ml8. This is attributed to be

proximity of the drain and source diffusions causing electrons

generated in the substrate, as a result of impact ionization at high

fields, to be swept directly to the diffusion region rather than to

the surface. However, a decrease in channel width would increase the

hot carrier effects, because of the edge effectsl8. The higher

electric fields generated at the gate edge would enhance the

probability of emission from silicon into the SiOz increasing the

hot-electron emission current. Improvements are cent~e4 on lightly

doped drain structures or graded drain doping,7,20 although the

influence on degradation of traps and interface states present in the

oxide and therefore the quality of the oxide, must be considered28.

154

A3.4.3. Vertical field effects

Vertical field effects are a consequence of stress voltages

applied to the gate of the MOSFET. Chapter b ha~ covered the

effects of gate voltage stress on oxide breakdown mechanism, and

highlighted the following features.

(i) Breakdown was caused by the conduction of electrons through

the SiOz either by hopping conduction (d.c. stress) or by

impact ionization in the conduction band (pulsed voltage

stress).

(ii) Electrons were injected into the SiOz by means of tunnel

emission at the Si-SiOz interface, a mechanism which is

dependent on the electron concentration at the injecting

electrode as well as the interface traps.

( iv) Breakdown was enhanced by the presence of traps and donor

sites in the oxide bulk.

Section 113.4.2. has also shown that under the influence of high

electric fields in the channel, a further injection mechanism at the

Si-SiOz interface, in the form of hot carrier emission is introduced.

These injected carriers will also contribute to electron~c conduction

process in the SiOz and therefore to the mechan~sms of oxide

breakdown.

Figure A?..S. shows a cross sectional view through a MOSFET

indicating areas most sensitive to breakdown is small d~mension

dev~ces. The underdiffusion of the drain and source wells will take

up a greater proportion of the gate length with respect to the channel

155

-----------------------------------------------------------------

SOURCE DRAIN

+ + n Hot n '--------------J electrons~------------~

p- type substrate

n - MOS Device

FIGURE A3.5. MOSFET showing areas of high breakdown probability in submicron devices (cross-section through drain and source).

156

length compared to a long channel device24,25 The surface charge

concentration dependence of oxide breakdown will therefore mean that

n-channel MOSFETs will be more sensitive to gate voltage stress,

especially pulsed (ESD) voltages, at submicron levels. Hot electron

emission is highest at the drain junction and under dynamic operating

conditions, these carriers can contribute to the surface charge

concentration effect to result in lower breakdown thresholds (d.c.

gate voltages) for n-channel submicron MOSFETs. In p-channel MOSFETs

the high channel dopant concentrations requ1red to maintain

performance characteristics will mean more electrons at the

semiconductor surface. These devices will therefore be more sensitive

in the channel region to positive voltage pulses, particularly of an

ESD nature, than n-channel MOSFETs.

Figure A3.6. shows a width cross-section through a MOSFET device,

indicat1ng the edge effects of the electric field. Higher electric

fields at the edges enhances hot carrier emission under dynamic

operating conditions, as well as contributing to the oxide breakdown

mechanisms.

However, oxide thicknesses below 150 A are expected to show an

increase in pulsed breakdown thresholds because of their lower

sensitivity to impact ionization. The thinner oxide providing less

time for the ionization process to reach breakdown proportions21.

A3.4.4. Conclusions

Oxide breakdown mechanisms proposed in previous chapters have

been applied to submicron MOSFET device structures to identify areas

which may be sensitive to voltage stresses. The dra1n-source voltage

157

in small MOSFETs causes hot carrier emission which can contribute to

these breakdown processes making devices even more sensitive under

bias conditions. n-channel and p-channel MOSFETs are sensitive at

different regions, i.e. the drain and source underdiffusion and the

channel region respectively. Submicron CMOS devices can therefore be

considered to be more sensitive to breakdown because of these effects

than standard geometry devices. Narrow gate widths (< 2 I'm)

universally enhance the oxide breakdown process, both under gate

voltage stress (high electric fields due to edge effects) and dynamic

bias conditions (increased hot carrier emission due to edge effects).

Experimental observations of pulsed voltage effects on small

dimension devices indicate a trend supporting the increasing

probability of gate to drain/source breakdown with smaller channel

lengths.

158

GATE CONTACT

FIELD

OXIDE

SUBSTRATE

FIGURE M. 6. MOSFET showing areas of high breakdown probability in submicron devices (cross-section through channel indicating electric field effects due to width).

159

A3.5. SUMMARY

1. Important features of very small dimension MOSFETs are;

a) the high electric fields in the conduction channel region

b) the increasing influence of edge effects as width dimensions

approach the depletion layer dimensions.

c) higher dopant concentrations required to obtain device

performance comparable to standard devices.

d) drain and source underdiffusion and dopant concentrations and

their influence on oxide breakdown mechanisms and interface

states.

2. Computer simulation of MOSFETs in three dimensions is

essential with devices approaching submicron sizes, since width

effects can no longer be ignored. Programmes of this nature already

exist, and published results, showing width and length effects on the

surface potential and electric field of VSD devices, have been

presented in this chapter.

3. Published results from the computer simulation of VSD devices

show that as the width of the device decreases, the avalanche

breakdown threshold voltage at the drain increase, and the punch

through current decreases for a given voltage.

4. Hot electron effects are found to increase with smaller

channel widths, although at channel lengths less than 5 ~m, the

emission current decreases. Degradation in VSD MOSFETs is the result

of interface state generation in the presence of hot carrter injectton

at the Si-SiOz interface.

5. The smaller geometry of VSD devices compared to standard

MOSFETs make them more sensitive to some of the oxide breakdown

160

mechanisms described in Chapter 3 and 4. Particularly sensitive is

the gate oxide at the drain and source underdiffusion regions in

n-channel MOSFETs and at the channel regions in p-channel MOSFETs

because of the higher surface charge concentrations and the

corresponding effect on oxide breakdown. Higher

electric fields at the gate edges (along the channel width) and the

prospect of higher hot carrier emission can make the gate oxide in

this region also very sensitive to breakdown.

6. Experiments on small dimension devices described in Chapter 4

have indicated a trend towards increased gate to drain/source

breakdown as the channel length decreases. This is considered to be

justification for the validity of the proposed breakdown sensitivity

of silicon submicron MOSFETs presented here.

161

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27. TAKEDA E. o JONES G.A.C. o ARMED H., Constraints on the

Application of 0.5 rro MOSFET 0 s to ULSI systems.

-IEEE Trans. Elec. Dev. 0 ED-32 0 pp. 322-327 0 1985.

164

28. MATSUMOTO H., SAWADA K., ASAI S., HIRAYAM M., NAGASAWA K.,

Effect of Long-Term stress on IGFET Degradations due to

Hot Electron Trapping.

-IEEE Trans. Elec. Dev., ED-28, pp. 923-928, 1981.

29. LAI P.T., CHENG Y.C., An analytical model for the narrow-width

effect in ion-implanted MOSFETs.

-Sol. St. Elec., lL• pp. 639-649, 1984.

30. PISCES II - developed by M.R. Pinto, C.S. Rafferty, R.W. Dutton;

Center for Integrated Systems, Stanford University,

California.

165

APPENDIX 4

ABSTRACTS OF REPORTS ASSOCIATED WITH THIS WORK.

Report No: 1 MOD Contract No: ASa/1265 LUT Contract No: RXB 211W (August 1983 - March 1984)

Report No: 2 MOD Contract No: ASa/1265 LUT Contract No: ELB 211W (March 1984 - September 1984)

Report No: 3 MOD Contract No: ASa/1412 LUT Contract No: ELB 247L (September 1984 - April 1985)

166

ABSTRACT OF REPORT No: 1

An investigation has been conducted into the failure mechanisms

of semiconductor devices based on a study of the available literature

on the subject.

This report provides an extensive coverage of the extsting

theoretical and experimental aspects with respect to each area of

semiconductor reliability. The survey has included analysis of

reliability engineering and failure physics pertinent to a thorough

understanding of semiconductor failure mechanisms. Hence,

manufacturing procedures, screening processes, quality assurance and

reliability modelling have been dealt with extensively.

The principal object has been to identify the possible sources of

failure mechanisms, and to investigate methods for detection and

elimination which could be used to improve the reliability of

semiconductor devices.

Over 300 references have been studied and provide much of the

informatton contained in this report. Discussions with semiconductor

device manufacturers, electronic equipment manufacturers and users

have helped to evaluate the literature in a practical context.

167

ABSTRACT OF REPORT No: 2

The Electrostatic Discharge (ESD) sensitivity of small dimenston

NMOS Field Effect Transistors has been investigated. Discrete NMOS

FETs of varying dimensions and a constant gate oxide thickness of 400

A were each subjected to a single ESD voltage pulse of between SO

VOltS and 2S0 VOltS I at temperatureS between 2S"C and 20Q"C. Over

4000 devices were used, all resident on a single 3 tnch stlicon water.

The object of the experiments conducted, was to determine the

dependence of device ESD sensitivity on temperature, applied voltage

and the gate dimensions. The voltage pulse was generated using the

"human-body model" ctrcutt as described in Method 301S.2 of the

MIL-STD 883 C.

Device I-V characteristics obtained after application of the

pulse were classified into five categortes.

1) No change

2) Reduced characteristic - a degradation in device performance

3) A reduced characteristic with anomalous high gate-field

effects.

4) Complete failure with no current being obtained.

S) Linear I-V characteristics

At SO volts, the Z number of devices showing "no change" was n;t,

with only s;t showing complete breakdown. At 2SO volts, the Z number

showing "no change" had dropped to 7;!, with about 10;! showing complete

breakdown. Degradation accounted for over so;t of the devices.

No temperature dependence of device ESD sensitivity was

observed within the range of the experiment.

168

A cumulative ESD effect was observed, whereby the degradation of

device performance was found to increase with the number of applied

pulses. All devices showed complete breakdown with the application of

25 pulses at 1 kV.

Complete breakdown was found to be gate dimension dependent

increasing with increased channel length at a constant width.

Analysis of the breakdown characteristics enabled a model to be

developed describing the mechanisms of ESD damage.

169

ABSTRACT OF REPORT No: 3

This report describes the work done on the contract "Failure

Mechanisms in Semiconductor Devices" between November 1984 and Apr i 1

1985.

Further analys1s of the ESD results reported 1n Report No. 2.

have been made and this has been followed by an invest1gation of the

application of continuous ramped volta~es to MOS capacitors of the

same oxide thickness as that of the gate oxides of the MOSFETs. The

following conclusions have been reached:-

(a) The len~ths of the polysil1con gate contacts do not have an

attenuating effect on the amplitude of the applied ESD

voltage pulse. Both experimental and analytical

investigations show that all devices with a common gate

contact would see the same gate voltage.

(b) The geographical distribution of the damage categor1es 1 to

3 do not show a d1stinct preference for any particular

location on the chip. Category 4 devices are found to show

a preference for devices with small gate width (1.4 vm < w <

2.1 vm). While category 5 devices are clustered around the

gate contact pads.

(c) Experiments on 1\IOS Capacitors showed a sign1ficant

differences between the breakdown voltages of devices upon

application of an ESD pulse and with a continuous ramped

voltage. Damage with an appl1ed ESD pulse occurs at

approximately 200 volts compared with approximately 40 volts

when the stress is continuous.

170

Work has been extended into failure mechanisms in submicron

MOSFETs and it has been decided that the effect of the fringLng field

becomes of considerable importance in small dimension devices.

171

----------------------------------------------------------------------------

APPENDIX 5

Failure Mechanisms in Semiconductor Devices by E.A. Amerasekera and D.S. Campbell (to be published by John Wiley and Sons (U.K.) 1986.)

ABSTRACT

This monograph prov~des an extensive coverage of

the ex~st~ng theoretical and exper~mental aspects w~th

respect to sem~conductor rel~ab~lity. It includes

analys~s of rel~ability engineer~ng and fa~lure phys~cs

pert~nent to a thorough understand~ng of sem~conductor

fa~lure mechan~sms. Hence, as well as rel~ab~l~ty as

such, manufactur~ng procedures, screen~ng processes,

qual~ty assurance and rel~ab~l~ty modelling have been

cons~dered ~n deta~l.

The pr~nc~p~L obJect has been to ~dent~fy the

poss~ble sources of fa~lure mechanisms, and to

~nvest~gate methods for detect~on and el~m1nat1on wh~ch

could be used to ~prove the reliab1lity of semi-

conductor devices.

Over 300 references are quoted and prov1de much of

the information contained 1n th1s monograph.

D~scuss1ons with semiconductor dev1ce manufacturers,

electron1c equipment manufacturers and users have also

helped to formulate this survey and strengthen the

pract~cal context.

172

APPENDIX 6

Electrostatic Pulse Breakdown in NMOS Devices - QRE International, ~. pp. 107-116, 1986.

173

1}1 \Ill' ,\ ... IIIHII\111111, l"oi"IKI'\(•I'\IIK.,.,\1\ti..,Al \fll 1117 Ill> t l''""l

ELECTROSTATIC PULSE BREAKDOWN IN NMOS DEVICES

I A .\MEKr\<:;LKI RA \NI> I> ~ ( t\Ml'IH 11

I h•t frOI/1( ( 11111(10111 m r, ( lmolor.:\ (lrrmr, fit ( trmll< Will Eft ( tru llllm~llll'( rt/11: f), flllrmu m I ou~hlmrmu:lt VIlli f'r\IH oj I ( ( lmolo~\ I o11~hhrmm~lr l.t "nlt nlure !.Cl/ ?I U U A.

SUMMARY

1 he deuro,t.ttH. di\Ch,lf!.!C ([SD) ,~,n,ltl\llV ot ,m,tll J•mcthlon n·Lh.umd mct.d oxtdc 'cmu .. onduuor (NMO~) held dlcu tr.m~I..,IOr.., (FC f.,) h.a... t1ccn mvl!,llg.ttcd NMOS F[T.., of \'.trvmg <.hmcn..,.on' .md ,, <.on..,tdnt g.llc o\ldc th1d.nc" of ~!lOA were L.H.h 'UhJC<.tLd to .t :,mglc ESD volt,lgc pul'c of hctwcc:n 50 ,md 2-=iOV .tt tc:mpcro~turc\ bLtWLLn :!-=i .md :!OOOC o, l..'r .moo dc.:\tLC' "'~.re u\cd .tll rc\1dcnt on " .. :nglc 3 mch 'di<.On w.ilcr The nhJI.<.t of the~.. \pcnment '"·"to dctcrmmc the dcpendenu! of dcv1LC ESD .. cn,lt!vltv on h:mpcr.tturc \Olt.tge .tnd dcvu .. c duncn,!On' "' wdl ,,, to IIWt.,tlg.ttc the me<.ham"m' th.tt Cdu'c oxu.le hre..tl..dov .. n ,~, J. rt .. ,ult of ESD J.un.tgc

Nn tcmper.11urc depcndcm.e tiiLIL ..,;LC [50 ,~,11-.LII\ 11~ '' .~, oh,cr,cd \\ 11h1n the r.1ngc <•f the exp~:nmcnt A ... g.lllfu...ult \olto~gc dcpcntkn<.c ''·L' oh,~.n·cd \\tlh dcg.r.Lt.l.l!Lon <~ctountmg for over SO per cent ot u~. Vl(..t: ... 11 250V A <.umul.ttl\ c: [~D et feet \ .. , ... (lh .. cn cd, whereby the dcgr.td.ll!On of deVICe pcrform.mcc w,,, found to mcrc.t\1! wHh the number of .tpphcd pul'c' An.dy"' of the bre..t!...down ch.tr.Lcten..,uc' n:ve.iled th.!l the t...IU,e of d.mlJ.g.e w • ..., ox1de hr~..LJ..down Apphc.Lt!On of the E~D pul-.1! .tppe.Lr' to k.tc.J to Ol.; tdc brc,t!...dnwn through unpt~ttLUilLZJ.tlon \\ 1thtn the O\tdc the' cry 'hurt dur.ttton of thl! publ! not bcmg. f.1vour.tblc to pro<.t.'i'e' lll\olv1ng elc:ctron tr<1pp1ng. unle" lhe..,c tr·•P' .lre .tlre.Ld} prc-,cnt 111 the o>.tde

INTRODUCTION

The problems dS\OCI<~ted w1th the presence of \tdtJC potential' m worl-..tng envtronments hJ.ve been well documented.' ' St,Jt!C potentl<~ls ot 211kV <~re eas1l~ generated The d1clectnc 'trength of S102 IS appro\· Jmdtelv between 9 <~nd 14MV/cm (1 e. between 90 <~nd 140V ford IOOOA ""de th1ckne") ' • Hence MO~ devtce~ .trc very \Cnstttve to electro..,t,ltJC (h:,chJrgl.!

(ESD) d<~m<~ge \Vuh the J.dveiH of dev1ces ot ver: ~m.tll dtmen­

stons the problem':> ,,o;;..,octated wuh E~D Jre bt:com· mg more trnportant OxuJe th•c"ncs~ down to l50t\ .tnd MOSFET dlmcn\ton-, dpproJchtng 1!-Lm .tre even more ~ens1t1Ve to ESD than edrher devtccs

InvestJg.tttOns m to ESD sensitiVIty ,md fdtlurcs arc wu.le-rangmg. covcnng J. VJ.St multitude of dcvtcc' .tnd opcr.llmg conc.lioon:, There 1~. however. a gn:\ .1re<.1 rcg.1rdtng the mcclunt~m~ bchmd the hre.l"· down ot ESD d.tnl.lgcd dcvtcc..,

The objc.:t.tJvcs ot the 1.!"\penmcnb pre~ented here.: were twotold

(.1) to cx<~mmc the ESD ..,cn~ltlvtty of NMO~ d!.!vtces J.S .1 tuncuon ot tcmp...:rLHure

(b) w mve::-..ug.He th!.! mech,mt~m.., ot ESD d,mug...: .md th \Ub'-lcqucnt effect on deviLC bch~lVIOUr

Item (.t) 1~ bJ~cd on" JMper by H.trt et a/"' wh1<.h prc'\Cnt~ .1 <.,t\C tor the tt.:mpcr.tturc dependence ol

ESD \Cn\ltlvtty However the dcviLC\ mvc .. ug,ucd by H<~rt <'I a/ were p.!d.<~gcd 11.10'> LSI LievKe' Lont.unm~ mput protcctunl <.Irtuiln F.ulurc w,,, trJ.ced to d.un.tgc.: 111 rh ... • prolc<.uon ctr<.ult. "' ·'

117 ~X-~1117. X6tll2111117 -111$115 1111 (f) l 1JKl, In lnhn \Vile\..,\.. \nn' I Id

wmbmed re\ult of the ESD puhe and the dpphed temperJture

A need wa\ theretore seen to mvesugate NMOS FET> Without protectiOn c~rcuury at the g<~te contact For th1s purpo>e Wdfers consisting of d1screte small dmten>Jon NMOS FETs were obt,Jmed by courtesy of Ple<>ey Re>eJrch (Caswell) Ltd The'e w,1fers con­st~ted of transJo;;tors of a vanety of dtmcns!Ons. m.J!...mg them !dcLtl for the expenments .lt hJ.nd

The pdper con\lsts of four secuons detJJhng the \\ork In Section 2 a bnef outline 1S g1ven ot C"<tSttng d1elcctnc bre.1kdown theory Secuon> 3 and 4 present the expenmental procedure and the result> respec­u,ely. dnd SectiOn 5 prov1de> the an<~lys•s dnd dJ>cuss1on of the datd obtJmed Over 4000 dev1ces were used m the C"<penment. provtdtng J. very IJ.rge d.tta hank for analys1s

2 DIELECTRIC BREAKDOWN

2 I lntroductum

There .1re two mcch.IOI\m\ wh1th .tre domtnJ.nt m the clcttnc.ll brc.t"down ot <.lich:LtnL mdtt:n.d~ They .1rc

(1) unp.1ct tOntLattOn \ r .... "

(11) electron tr.1n~port through tht: ox1dc by mcJ.n\ ot t.:'h!ctron rr.1p.., 1n thc O\H.k 'l

111

fhc two mt:ch.uu .. m~ .m: hndly mllltncd hdmv

IllS \ ,\\11 KA\1 1\.1 R,\ ,\NI> 0 ' (AM PIU Ll.

In the prc,l!ncc ot h:~gh l!lcc:tnc held,. m c"X<..cv .. of IMVh.m. the tonc.Jm.tHm h • .Hld edge '' dl\tortcd Hcn<..c clc(.tron' c.m g.un .1ct.C\\ to the condu<..uon h.1nd front the v.ilcncc b,md Electron\ .1rc tllJC<..tcd hy Schottlo.y h.trncr cn11""u.m {potcntJJI h.1rncr lower­mg). Poolc-Frcnkcl cmtvmm (hcld-cnh.tn<..cd thl!r­m.tl cxclt,ttlon of electron~ m to the condu<.t1on h.111d) or Fowlcr-Nordhcrm tunnelling. from both the mct.111rc contc~ct~ .md donor 1mpunty <;ltcs wlthtn the OX!dC

11

Once m the conductiOn bJrH.J dcctron~ m.l) be .u..<..clcratcd by the Jpphcc.l elect ne tic id to Jll energy IMge enough to umzzc the !.IUILC .md prodm.c J

dc\trucuvc elcctromc LJ\C.1dc Encrgy tr.tno;;fcr be­tween electron\ .1nd the I,Jttlcl! tdlo.C\ pl.tce ·" ,1 rt:,ult of clc<..tron-phonon Jntcr<~ctJOil!) w1thm the O\tde Cono;e4ucntl] loc •. lltled hedllng occurs \\ohKh could lc,u.l w therm,ll burnout '

2 3 £/cctrontappml)-.' 2

D1stort1on of the b.tnd edge> m the pre;ence of h1gh electnc tkld" could ,ll(jo en.1ble electron tr,m"port through the n·<1de by hopp1ng between donor nnpur­tty 'Jtcs ,md tr,ap 1mpunty \ltC\ Hence .1 k.md of 'conductum bJnd IS formed wlthm the lorb1ddcn energy gJp H.tr.tn9 h<t~ dcmon\tr<~ted J. strong reiJ­ttonshlp between electron traps generJted under high l)tres'\ com.huons. Jnd oxide bre,lkdown Tr..Ip­ped electrons could Jbo result 111 locJI1zed electnc held; tn e\ce;s of the d1ele:tnc lield strength

E\penment.tl evu.Jence presented by Hughe!) 111 Jnd H.trJniJ hJ\ \hown thJt defects <..J.n be gcnerJ.tcd 111 ox1tlc~ wh1ch were ongmally tlefect free. untlcr lime-dependent h1gh stres" con<..liuon~ Such .t

mc<...hdlll\m would he "igmfic.mtly temperJture de­pendent

2 .J Temperature and voltage dependence of o ndc hrea/...down

[t "lmportJnt to bc,1r m mmd th.tt the electn)\tJ.tJC dJ..,<...h.arge \Cil'ltlvlly of MOS dev1ce\ would not mvoh c .1 tlrnc-dependcnt f.tctor the dur.ttlon ot the pul'e bemg very ;m.tll (0 15m')

Q,burn ,tnd Ormond 1' h.ave ~hown J very ..,m,ill

tcmpt:r.tture lkpendcncc of the hrt!,tk.Jown 'trcngth ol .. woA S10~. between -.30 .md .311WC Thcv ,ug­gc,t«.:d rh.tt unp.1ct IOllJZ,llJOn rJthcr th.m the therm.tl­lv dcnve<..I cleltron tr,tp mech.ml ... m, w,t\ the domt­nt~nt mech.llll\111

The electron tr.tp mcch.m"m .~ ... prc,entcll h} ll.tr.tn ,.., ,!l,o le\\ "llltcd to the very n.1rrow pul\e w1dth' ,,..,..,ou.tted with ESD The long time­lh:penden<..c rcqUJrec..J to gener.1tc 'uthc1cnt tr.ap.., to c.IU'c.: O'<Jdc bre.tkdown would not he relcv.ant to E\D H.1r<~n 'uggc,tcd .a tcmpcr.Jturc dependence hc~,c.:d on th1' Jllc.:t.h.tnl'm \\ h1<...h ''ould thcrclnrt. not he .tpplit.Jhk to E\D hrt:.tlo.d<H\11

(hhnrn .111d \Vl'lltm.nt 11 lound tll llllrL.I''-' 111

kJk.1go current through the d1clectnc '" the ,1ppl1cd field '" mcre.tsed. 10 accordance wuh the 1mp.tct IOllll,l!lon model They Jho found thJt the lc.1k.1ge current .tnd nhl'<lmum dJclcctnc field ')frcngth were not \Jgmhc.mtly mtiucnccd hy the \Ubstr.tte lJPC or Jop.uu conccntrJtlon

3 EXPERIMENT

3 I The Hiiconovafer

A\ noted e.triler the te::.ts and re~ults to be dc­'\Cnhed were obtcl!ned on proces'\ J.\sessment w.1fers kmdly pnw1ded by Ples<ev Re<earch (C..,well) Ltd The NMOS trJnmtors arc manufactured on 3 mch \lice p-type wJfer> On the<e wafers ,• wells .tre dtffuscd to form the source and drdm usmg J.rsemc •ons. with .1 concentration of 6 x 101' cm-' at 100 J..eV A g.1te ox1de of 400A thickness 1s therm.dly grown .lt y.:;ooc The polys1hcon n ... gate 1s grown .tt

620'C Jnd IS ~550A th1ck In order to obtJIII po<tt1ve thrc'\hold voltages for the enhancement type devKe the ch,lnncl " prelcrentlJlly doped wtth ooron lOll< w1th .1 wncentrJtton of~ 0 x 10 11 cm-' at 30 J..eV The ;uostr.ne resiStivity IS 20!1 cm

The water consiSts of about 100 ch1ps EJch ch1p conSists of three blocks of NMOS tranSIStors. two of wh1ch con;~st of enhancement mode dev1ces and the thtrd of depletion mode dev1ces The transiStors are "et 111 row'\, each w1th a common source and a tommon g,tte contdct. In some cases mdlvJdual MOS tr~ms1stors .tre constructed 111 parallel and connected ,1-; a -;mgle transistor m order to enable better current me.!\Uremcnts to be mJde Results were examtned to cn;ure th.tt th" pJr.lllehsm d1d not affect the result< 111

.my w.ty E1ght dr.un c.ontacts wnh effectively e1ght tr.tnsJstor'\ .tre dvatlable m each row The tranststors drC of v,trvmg chJnnel lengths and gate Widths r.1ngmg from I 4~m and 102 9~m

There .tre approXImately 176 dev1ces avatlable for expenmcnt.ttton per ch1p ,md a sum total of approx­un,Hely 17 600 dev1ces on a wafer

1 J The apparawr

rhc E '>0 puhe "gcncr.Hed u'tng the 'hum.m oodv' model tJrcuu .t\ de"cnbed 111 Method ]015 2 of the MIL-STO-SX3 C ,md \hown 111 F1gure l(a) A IIXIpF c.lp.tcJtor "th.trged up to the reqUired pulo;e voltJge .tnd then dt..,<...h,trged through .t I Skfl re..,l\tor directly onto the g,ttc cont,tct of the devtcc under tc...r Both the <..lcvJtc cont,lct c1nd the \Ottrcc tont.tct were lctt tlo.Jtmg The ... ub..,tr~tte w.1-; grounded

A hc.ltcd chutk With thcrmo,t.Jt c.ontrol cn.ahlc' the tcmpcr.uure of the wt~tcr w he \C:t .lt tht: dc,Jru.J level (±::!°C) when lllVC\fi!_!.IIJng the tunpcr.tturc c..kpc.'IH.kllLL ol f:<)J) 'cn,JtJ\'11\ h~urt• I (h) 'htm' 1

hind. dJ.1gr.t111 ol thc tot.II '-''pcrlltlUll,d trr.tnl.!'- · lllllll

Ill Cl lW.., lA 11< l'Ul ..,, HRI ,\"-I>OW"'' IN NMO' l>l \I< I' 10'1

Rt R2

.---c=~--~sr---c=~--,

DC power supply

Cl OUT

Fn!un .. 1{.1) Hum.ut h\lJ\ nwdd urt .. UII u":d tu l!liH.r.lll! [~[) pu·l,l!(,•ft!!rMIL-')lD-1\:-\1(') RI"" IMU R1 =I ·(\...1! Cl= lOll

pF !>--t"ll-poh.. rd.1v Dlo T -J'-' Ill! umll..r IV• I

r--ESO M•croscope

Power CirCUit 1----, supply aod '

' reloy ' ' '--- ' ' ' ' 0 :Gore F: t contact Curve

l Probe

tracer

I I S•l•con wafer

J Heated chu ck

r-- ~

Curren source

Thermocouple Thermostat

F1gurc 1(11) Bloc\.. dl,l!_!r.un nl ·•PP 1r nu ..

3 3 Expenmenwl protedure

3 3 I Measuremen1s The current-voi!Jge (I-V) charactensucs obt,uned usmg" curve trJcer (CT) contam mformatton from whtch mo~t of the clectnc,tl propert1es of the tr.mM-.ror LJn he detc:rmmcd Therefore. the CT w.t ... u~ed tn mollttor ch.mge' tn

tran-.t<;tor chJracten\tiC\ atter .tpplu...ttlon of the ESD pu"e

All me.t,uremenr... wcr-t! m.tde dt room tempcr.t­turc When ,1 w.tfer w,l\ he.tteU .tnd puJ..,ct..i. u ... elccrrtc.II propcrt1e.., \\ere cx,mHneU ,Jt room tt!mpt!r­"ture (29XK)

3 3 2 Volta~-:e ""'~e The uk.tl volt.1gc r.tngc w.t ... considered to he one m '' htch .1 stc.t<..ly n..,c 111

<..u."trophtc f.ulurc would be l)lhcrvt!d With lncrc.t-..­mg temper .tture. hut lOO per CL'nt t.ul urc of .111 dcv1ce-. 1n ,, group w.1-. not dv·-~rcd Th\.· voii.Jgl.! r.mgc tounU to h\. mo ... t ... uu.thk ,,,1.., hct,,el.!n -=i() .tnd 'OO V

I hu "-fore the tk \ ll \...,''ere ... ub 1'--lh .. d to plll""--. t ll -=iO IIlO I -=iO 2011 .111d 2""11 \'

3 3 3 Temperawre rangt:> The tempt!r.Jture range W.IS requ1red to encompd..,S the ..,t.uH.I.trd ma;.,. tmum operatmg temperatures for commer<.t.tl dev1ce<; (70'C) dnd m1h1ary dev1ce; ( 125'C) In ,u.Jchllon me.J~urement~ were .1bo m..1de .tt room tcmpt!r.tturc:. wh1ch were u~cd .1.., .1 control group E\tremc tcmp..:r­,uure dependence Wd' e\dmancd with .1 group .lt

2110'C The five ;elected tempcr,nurc; were thcrdore 25 70 110 1511 ,md 21HI'C

3 3 .J Numher of deltle' The tot.ll numhcr of dl.!vt<.e.., U\t...d m tht\ C\penmcnt w.t-. .tpprtl\tlll.th.:ly ") x 176 = XOO .H.! gtvcn tcmper.lture -=i "<~SO= -l-HlO 111

tc..H,tl lllll.., 25 1..h1p' , .. ere u"(..'d

3 3 5 Preuwflollt lt \\,J.., nnpnrt.trll th.Jt lll<i'<­

nnum prcc.tUlJonJr~ ml.!.t-.un:' \\Cr1..· t,i\,\.n to L"n-.urc th.tt di.!VtCC\ whu..h \\Cre d.lm.Jged .1\.Ltlknt,dlv e1ti1Lr h~ the mc,t..,unng tt!<.h111quc nr b\ 'f'unnu' E"D pul'(..'" wc:rL not IIH.lmkd 111 the .lll.d\''' llw.., .my d"-'''-\." whu .. h ... how / 1,.., ,.., \ 1,.., dl.uo~dl..'n-.w ... -. 111

'' h 1c.. h I p-. d ilk 1.., h\ 1111 l lt t 11.111 .:: I 0 f'L" r tl n t ! 1 11111 t h\.

110 I. \ AMI Ri\'•,1 "-1 RA t\Nf> I> ~ ( AMI'Hl-LI

\t.Jm.J.ud provu.Jcd hv unpuJ .... cd dcvu..c,, or wlw .. h do nor work m the prc-cxpcnment mc.I\Urcmcnh .• 1re noted ,and left out of .my further C\pcnment.ttlon Bctorc .my cxpcnmcnt\ were begun . .tnd hdorc the w,1fcr w,,, h.mdlcd. the opcr.ttor dN .. h.Jrgcd hlm,clf of .tny ~t.lllC potentl.tl th.lt m.ty h,tvc .Jccumul.ucd

3 3 6 Method The exper.mentJI method con­"'ted of the followmg step'

I The chJrJctcmtlc' of Jilt he dev1ces on 25 ch1p' were rcconJcd

2 The w,tfcr w.1~ brought to room tcmperJturc. 25°C bemg 'elected for un1form1ty

3 All dev1ce' on one ch1p were 'Ubjected to J

~mgle ESD pulse of the rcqu1red volt.tgc .tt .1

gtven temperature 4 The cxpcr.ment w," repe,ncd tor the 'elected

voltage r.mge on hve different chtp~ 5 Steps 3 and 4 were repeJted until the enllre

temperdture rJnge hJd been covered 6 The wJfer was then allowed to return to room

temperature 7 The dev1ee char•ctenst1c' of .tll 25 ch1ps were

Jg • .Hn recorded. emphas1s bcmg !JJd on tho';e dev1ces "'h1ch showed change.., m the lhdr.lctcr­IStiCS recorded m step I

3 3 7 Dejmucon of farl11re It w.ts decided that no pdrtlcular 'pectficatiOn would be l.t1d down outs1de ofwh1ch a dev1ce was deemed to have fa1led ln"ead, any recorded vananon m devtce chJractenst!C tram measurements made before appl1ca11on ol the ESD pulse was cJtegonzed

3 3 8 Cwmclacrve ES D effect The Jbove expen-ment subjected the dev1ces to only one ESD pubc In order to ob~erve the etfect of J se ne' of consecutive ESD pulses on the dev1ce charJct~n!)tJc.., ,, '\tnJII number of d~\ 1ces were subJected w a se4uencc of pulses

Only 24 dev1ces were used for each set ot pulse,, 8 bemg pulsed at 50 V. 8 at !50 V and 8 at 250V The expenment w.t> repeated at 10 pulses, 15 pulses. 20 pulses. 25 pubes. 50 pulses and HXl pulse,_ ,md the chJrJctensttc~ were recorded

Subsequent devtces were ..,ubjectcd to .t con\tJnt number of pul'e~ .md v.utous volt<~gcs between 350 .tnd I()(XlV T11en1y-hve pulses .tt 350V, 525V_ 71KlV <~nd IOOOV were .tpphcU. the chM.ICtcn~ttc.., hcmg recorded Jtter .lpplic .. HJon ot the :!5 pube'

4 RESULTS

.J I I lVm c{orm ·1 ht: ESD pul"- gcrh .. r.Jh .. d ll'-lllg tht! hum.111 h<H.h mndd 1' nt th"- .. h.IJK' 'hm\ n 111 F1gur~.: 2 "' uh,cncJ till .Jnn,ullo'u1pc .111d u'ill~ .1

low L.lp.lut.uh.l pnlhL I he n'c llllk t!IIIK pul't..' r,.,,

V '"

t ~

0 >

>

0 ,_ 500ns tms

t sec --Ftgurt. .:! Vult.tg.l .1g nn.,t ttmc for hum.tn hodv puhl!

= 500ns I he Jcc.ty ttrne ot the pul ... e. r •. h..l•\ = I ms (th1s" dependent on the m put 1mpcd.mce oft he lo.1d CirCUit .10d hence will vdry for d1fferent gdte 1mpe· dances)

4 I 2 Polarrt\' The mJJOnty of expenments were performed wuh positive pulses However J few c\penments were performed usmg negat1ve pulses over the ~dnte voltdgc rJngc As the effects ob..,ervcd were !)lffili.tr to tho-;c for positive pulses. no ';pec1hc .m.1lys1S of these observations needs to be cons1dered

4 2 Charac..tensucs

A comp.mwn of the 10 , vs V0 , characteriStiCS ob,erved before .mu after apphc.111on ot the ESD pulse. sho'" that over 95 per cent of the dev1ces could be class1fieJ tnto one of the followmg hve cJtegonc~

4 2 I Categor_1 l-110 c!Ja11ge All pJrametcrs remam undltered. tht! typ1cJ.I transl\tor charJcten~­llc, JS 'hown 111 F1gure 3. bemg oht,nned

4 J ' Categor.' 2-degradatlOil A typ1cJI 1-V characten\tiC for devtce~ m thts category IS shown m F1gure 4 The dev1ce has the same d1mens10ns '" the dev1ce .ISSOCIJted wuh F1gure 3 However, acompdn­~on of the two char.tctenstiC'; ~haws s1gmficant de­grJdJtJOn to g1\e Ftgure-+ The mutu,ll tr.m~conduct-

t, J 40 (m A)

35

30

25

20

, 5

10

05

-"os(V\

lrctul' '·•dltlll,!l / 1"\' \p,dllflll~ll'lllh.rl~~··r\ IJ

IIICII.:U\r,\11< I'VL~l- HKLAI\I>OWN IN '\\111\ Ill \I{ 1.., I I I

.IO<..c CS:m) h.J~.o dr.!crco~..,cd .tlong: \\llh th!.! dr.un-,oun..~ condu<..tJnce (g.~ .. ) m the lme.1r reg1on gd .. m the 'i.,Jtur.lllon reg1on h.1s mcrt.!'.bed

McJ~urcmcnt... of thr.! g.lte-dr.un re"il,tancc. Uc ,f> •

• ..and the g.lte-sourcc fC'i-1\t.mce. Ru,. g1vcn 111 T J.hle I. ~how th.u only .1 very <;.mall k:.tkagc current IS prc"icnt

T.Lhk I G<~lc-.. ourcc rc\L'tl,mcc (R<,,). l!.tlc-(]r.un rC\L'tl.mcc (R<.o) .md gdiC-'tUh!>lrdiC rCMS(,IIlU! (Rc 11 )~1ogclh.:r wuh .t!>MJCI· .ltcd current v,tiUC'i for dcVLCC\ t:'<hLhL!tng the hvc. c.ttegone'i of ch.tractl..rL\IIC .. (N B No two nr the deVICe\ me 1\UfCd 10 !he tahlc

hclow h.1ve I he •;..•me dLmcns•on'}

C.tlegorv R<,, R0 D

(kll) (kll) V<, le, lm, R,,11 /< n Rn, (V) (mA) {mA) (I..U) (mA) 1..0

-------- ----X X X

2 'i(l 1 6~ f) J 0 () -16 () 1-1 I 'ill 0 3 ~ .:; 7 9 JO ~ 'i 0 94 () Ol J IOY IS -'0 Jl) 11 Y-' U Y'i2 f .. UI() 0 ()(Jf..J s ()

10 1 0 1 I JO 10 12"" l-170 () l1'i

-1 2 3 Category 3-degradauon wuh negat1ve gm at h1gh VG' In •ddn•on to the degradation descnbed above. the~e devJCe"i also exh1b1t d dr.un-source current wh1ch be gm~ to dccred.,e as V G., mcrea'i.es beyond a >pecilic vJiue (see F1gure 5) MeJsurements show that ox1de res~>tJnce value; (T Jble l) are lower than those assoc1ated w1th category 2 dev1ces

4 2 4 Category 4-catastropluc failure Th1s CJtegory IS so termed because Ios "'0 for all values of VG<· and for all values of V0, up to Jvalanche breakdown as shown m F1gure 6 Typ1c.Jl Re,, dnd R00 Vdlues m Table l md~eate thJt the ox1de dt the source >hows very h1gh leakage

-1 2 j Category j-reSL."illve characterzsucs These charactensucs are ~hown m F1gure 7 The resist­dOe~ values m T .1ble lmd!c~He an ox1de bre.tk.down dt

the dram wh1ch, owmg to the electncal c~rcumy of the cr. results Ill these chc~ractensucs

4 3 The cumulallve E!>D effect

The results of th1~ e\pcnment arc prc ... ented 111

4 • ' I (;;,t I 35

30

25

20

15

0

-v:>5(V)

FLt!Ufl -! D~.t!r Id 111111\ , .... " \ n .. dllr l{hfl .. ll(' (l '11.!!0(\ 21 \,,...:; 1\'l'lr'llp

2 3 4 5 s 1 a 9

-vos(VI F1gurc 'i In, \\ V0 , Lh.tr.u.ICrL'-IIC 'howmg dc.gr,u.l.Ltton wuh

ncg.JIIVC gm .lt hLgh V(,, (L..LII..gory 3)

t I t,

(m A)

IQ

08

os 04

02

o~rr~~~--r-~,-~U4 23456769

-vos<vJ

F1gure ('I C.tt.t\lrorhu: failure /1,.. vs V1,.. ch,J.ractcmt•c ( c.ttegorv 4)

Tables [[ Jnd [[[ Table [[ shows the effect of mcreasmg the number of pulses and mcreasmg the apphed voltage Table [[[shows the effect of mcreas­mg the apphed voltage with a constant number of apphed pulses unul complete breakdown occurs

T.lhle 11 \l;l<>olutc numhers or device.,; 'howm~ charactemtiC~ JcpJcted .ts .t function of the: number of .1pphed E:so pul-.c!> and

!he ·•rplLcd E~D voltJge (8 dcv1ces per cell)

Volt\

50 :s 50

lOO 1~0 :s

'" \()()

2fXI " '\()

J( K I

'lo chane.c ( <...l!egorv~ I)

reduced dur.tCILr·

1<;ILC (c.ucgory2)

C.tta)>­trophtc fdLiurc

( Cdtcgorv-') -------- -- ·--- --

7 I lJ 5 1 0 () H 11 (I 7 11 3 5 0 11 7 11 2 5 2 I) 7 11 0 11

T<~hlc Ill Th1.. t.fkc.t of mcre.J'tlO!t the dppht.U [!:,D \olt,tgc ,J1.u.on'tl.tnt 2~ puJ..c, the .th,olute numhcr .. oJ dCVLCe\ 1. '<hJht!Jn~ I "le \!1VLn Ch.traCICrL'tiiC\ .If~

.. hown (2.1 d~\ICI..\ ~11 LdCh volt<LgC)

V oh .. RLdUtl.d C.11 .. ,. Rl..'ii .. IIVe Lho.~.r,Kit r- trorhl( Lho!.r.tc.ll..rL\·

l\{11,. f.ulurt' Ill' fC.tiLg_on 2) (C,tiLt!Orv -1) (t.LILgorv")

l"O 12 Ill 2 'i~'i "' no 7 "' lt M M I 11 2 I " ------- --

112 \ A\11R\\Ifo..IH:\ \~ll I>.., { \f\II'IHII

1oa 20 lmA)

15

IQ

05

0

05

10

15

R~..w .. ll\\, / 0 , \' l'0 ,\.hdr.t\.h.n'l1C (t..Uumr\ "J V,,,=. IV po..r -.t~..p ~

The lollowu1g olhCf\~ltiOn\ were rcLon..JcU ( 1) ,\Iter 11111 puhc' .1t 511 I 'ill .1nd 21111V the

dl!VILC\ \till dH.I not ..,how L.tt.t\trophiC.. f,ulurc ( !0 , ;:a; 0) ,,.., Jc..,cnhcd by L.ltcgory ..f Howev­er h1ghcr dcgr.u.l.JIJon '' ob ... crved .t\ the n umhcr of L~ppilcLI pui\C\ ,.., mcrc<~..,ed wnh I 0 ..,

he1ng reduced by .dmo\t J l.tctor (lf lOO .tftcr 1011 pul'c'

( 11) 1 he degr.!<..l.niOn .tt 250 V J\lo~rgcr th,m .lt 50 V. f,ulurc.., hecomtng more con~1~tcnt

(111) Bet\\een \511 .1nd )(XIII V ,,If dcv,cc' \how C\<..ntu.tl Lomplctc f.ulurc

.J ../ (JHtp/n

F1gure.., ~-JO \umnhlriLC partlcul.tr ,,,pcct'i ot puJ .... e hrcJ!...Uown bch.tvJour F1gure X ~how~ the temperJ­turc dependence nt the devJc.e ch<~r,Jctenstlc::, and d(h.!\ not m<~i...c dt'ltJnl.fwn-, between ti1tfcrent dpphcd 'oh<~gt.:..,

F1gurt.: IJ ... how.., tht.: 'vo!t.tgc tiepcnticncc. ot dC\J<.e Lh.Jr<~Ltl.!rt..,tJL\ ,111d dot.:\ not m.J"L dJ\tHlLtions bc-1\\t.:t.:n <.htfcrcnt tcmp~.:r.Jturc\

F1gurc 10 'how.., the \ .m,ltlon rn the pcru:nt.1ge number\ of dt.:\ tLC\ 111 <.dtcgory .f ""' .1 tunct1on ot de' 1<.c J1men..,,ono., The g.Jtc w1dth '' J..cpt uHl\tdnt 111

\..',tLh L,l,\.! .111d pcr<. .. CIH,IgC t,u(urC\ plotted J.' .1 tunl.l1on ol th.mncl length

5 DISCUSSION

' I , \nal\ \1\ of \latt\ltcal data

A ,,,,t qu.tJltltV ot d.tt.J ''<~' colkLted durmg the ~.our\<.' 1)1 tlh.: C\pcnmcnt The l.1rgL numht.:r of .... unpk' u ... cd m.JJ..c.., the d.11,1 c\trt.:mL'Iv ..,ull.thlc tor

't.ltJ..,liL.tl .Jn.tly"'" I knte 11 '' po..,"hk: to JUcntttv tT~.mt ... 1n tht.: hch.JvJour ol thl.! Uevtcc th<~r.JltCri',W ......

loth'' u1d F1gun.:' .'\-111 h,l'vt.: hc"-·n prt..'"-ntt.:U ·'' p~. T<.t.:lltik hgurc'

'i I I 1/~t•tcmpc!alllll' depeml<'me oJl: \/) H'IIH-

1111/\' I rom F1gurc X 11 '" tmmc<.!J,,rdv \Lt:n t h.Jt none PI lhL' L.IIL!.!llriL' nt Ilk d'-'\JLL' dl.lfdLIL'fi'[IL"' ,JHH'•

111' ''.1-!'lllh • .tnl trt.:nd llldiL.JIJII~ ,1 IL'lllpcr<~turt: de· 1''-ndulLL' /1 '' lhL·rc/(lJL' Ltlflt..ludul th.11 no ll.:mpcro~­ILII~ lkj\\.lhkll<.t.: L\l ... h hll ihL 'J7\J()\ /J f.., lll\t:..,(J· "1!\,.d

llu\\C\L.:r pu(l!J,h~.:d opuuon 1\ th,tt the ESD ~Cn'l­l!Vtty l)l MO~ dcvt<.L.:\ ,.., mllucnccd by tempcr,uure \V or~ prc ... t.:nt~ll hy I fJrt et a/ ' ..,Jww~ th,Jt th1o., '"~ mJccJ true! But the UCVKL • .., tnvco.,tzg,w..:lf hy H.~rt

''ere patJ..,Jgcd tntcgr.JtcU CirCUit!> mtorpor,Jtmg mput protcctllHl ctrcuury The c,tu"'C of f,ulure w"' m f.tct tr,tct!U to E~D U.Jnl.Jgc ot .1 tfwdc '" the pmteLtton <.trcuHry The nnpilcdUOn. therefore. 1~ th,lt at ~~

pov~ahlc tor the protection ctrcuttry to create a tempcr.lture Ucpcnclcncc \\<htch doe<; not norm,tlly ~'"t when de,dmg w1th only the NMOS FET

5 I 2 The ,·oltage dependence of ESD ~enHtu·ttv­From Fagure Y 1t w111 he oh~cncd thdt the number

ot de' tcco., m" htch no ch.tng:e m Ucvtcc char<~ctcnstJc<; " oh<;en.cd .tttcr ESD pul..,mg dccreJ~~s a\ thc .!ppltcd \Olt.!gC lllLn!d\C\ A ~agnah<..tnt H>lt,tgl! dc­penUcncc there tore.! C\t\t\ tor d.mt.tge char,tcten,tlc<;

5 I 3 Tire dtmCII\WilleB dependen(e of E~D ~en-HIIlll) A plot \\,1\ mJUc rel.tttng the dtmen<;JOns of the de,tct.:.., to the number ot <..kvtces fatlmg m the mo\t cat.Jo.,trophtc tor m In th t'i c,ltegory (category .f). In, = 0 ,md ht!nce the dcv1ce CJn be reg.trded <I!> complete!~ Jc,tro:eJ From Ftgure 10 a dehnttc trend c.m he oh..,~ned hCt\\Ct:n mcreJo.,mg t.ulure<; .md mcrt!d"'lllg de\ 1ce dimcn-;ton tor <1 con!>tclnt gate '' tdth Tht' '\U!.!1!C"'t" th.Jt the .trc,l of the O\Jde affects the proh.Ihdll~-ot O\lde breakdown OXIde break­down mu<;t theretore be related dtrectlv to the pre~ence nt Udect~ .tnd detect mechamsms 111 the O\tde

The .tb(l\C contlu~10n 1.., Ill ,tccordancc ,..,Hh the O\H..fc hre.d ... down model prc<;ented by Har~m'' \\'here electron trar' due to O\lde defect' .1re cl.umed to he the c,w<;e ot bn:al...<.lown However this sttll <.loe~ not contr.tdtct the nnp.1t..t tolliZ,ttlon moUel bec<..~use only the t!\I<;tmg electron tr(tp\ would Jtfect hre.1J..Uown Electron<; thu~ tr.1pped would gencr,lte htgh localized clectnc field.., rc..,ultmg lll .tn tncreJ~e m Imp.Ict tOfliZJ.tion tn the are.1 Jnd eventu.tl oxtde brea~down

The number of detect' m the form ot electron tr,Ips Ill thermJ.Ilv urm~vn O\tde hlms 1~ therefore con~1dered to he relev.~n~ to rh~ ESD "'Cil..,lttVIt\ of MOS <.le\fLC\

52 4nah \I\ of c/('1 /( C < /tm ll( ICII\IIC!J ajtCI pu/wll:,

52 I (atef.!ol 1 /-no clwnf.!e Theorc..:ttc.il brc..:.JJ...down \olt,Jg."-' tor .111 o\l<..fc \)f th~<.~nc ...... .J.Oil,\ v,1n ht.:t\\LL.Il .:;;o .1nd 100 V Thcrdllrc ,Jt SOV one

''"ould t.:xput the m.qont\ ot dt.:vKc.., not to he .tlkLted. ,111d rh" t..,mdt:ed 'n ·"..,cut 111 F1g.ur~. LJ lllc..: perLcnt.Jgc ol dcvH .. v' un.lfkut.:U h\ the E.)D puJ,~,..

dt.:Lrt~'<l'C" trom 7! .tt "ill V to 7 .tt 2"0 V. t.:mph.I,ILII\g: the volt.Jgc <.kpcnUuKe ot the U.un<~gc

) ' 1 (atr•t:on 2-dcgJadalton The d~gr.Jd.J-

1 U Ill Ill dr,llll-'t ltlfLC lllrfe . .'J\1 HH.ht...IIL'' th.Jt th~o: 'li ri,ILL' tll the.: 'L'I1\1Ltl!ldtilttlr I' 11111 h\..lllt! Jll\L'rtt.:d h\ the.: ~.111.:"-'t)llfLe \Lih,tg.L ILl the llJtgrll.iiL \[C/11 ( PlldUL· fh)Jl Ll! d1.tr!.!1.. I. tlrl\.1' lh!OII!.!h t\J,_ d,tll\.l~Ld 11\1\.k p!L\Ulh ,,Jil,f,ILII\1\ lii\LI'ltltl lrorll I,JJ..J!l,:! pi.!\.\.

I I I ( I J.I:O"o I \ 11( /'I 'I "'/ HK I \/I. I H 1\\ ' I' ' \/( '" 1>1 \ 1< I -. 11'

··r ·--------· 30

:><.~ ~ -: 0 20

• z

•o t ' :------~ ~~ -- -a-----~o--

0 " '0 70 100 110 "0 200

F•gur ... /'1 I cmr~o·r.llllrl d~o. pcnllcnu .. ol u~. \ 1\.l,. l.h.lr,ll h .. rt'IH .. ' !I k r [!',0 puh...: (L.IIi..!!On'-' J-'\) (Summ.1n of .dl \OI!,i!!l.. \,!hiL') -Colh..'gor\ I \ 1...11:g.on ~ , ' L.ll! ... gurv l + l..ll"gon ~ -::J C.lll.'gnn .;;

I rum lJguH .. -J 11 t..!ll ht: 'et:n lh.at the t.h.tr.tLtCfl"'·

Ut.' .m! ol ,, rKrlculv '\(,lnd~tnl n.tture for .tn NMO~ tr.llhl'\l{n \\'11hout I he hcnctn of the tontrult.h,,r.tv

tcri'IJL"' ''' F1~urc 1 one \\oult.l hi! JU"'tlllcd 111 ,J...,..llnllng th.ll the tr.1n'''h)r '' 111 \\llrk.mg tondHJon <~lht...'lt to .t <.hltcrcnl 'flCUflC.JIJon E'en .lftl.!r .tn ESD re,,,~, 'P"-'l'h"'·d h\ •\tfl .... .., rD-H~~c the dl.!\lt.l.! m"' ,ull P·'~' ·" ht tor opt:r.ltllH1 1f u-.et.lm ,l UJg114ll Cirtllll Ht:nt.e. ,t:nou' 1rnpli<..ttJon' .trc pl.lt.l.!d on the long­tt:nn ri.!!J.lbdit\ ot dl.!\ tLC' 'uhp.:t..ted to ... uch d.mMgt:

5 .! 3 Cmcg01 \ ?-dcg1 aducum tt u/i negam e S:m ut lm:,/1 l v' De\ ILl!' 111 th1' e.Jtegnr: <~r~ more

70

60

l 50 . • ~ 40 ~

0 30 0 z

" 20

10

(ToiOO"'o lkvl

150 A pplted voltage f vo•ts I -

200 250

F•g.urc ~ \ tlll.t~~o dcrcm .. kn~o~o 111 d~,.,,~,.~,. d1u ,~,.,~,.n,J•~., .tlkr [,;.;{) puJ,c (C.H~!!nn~' 1-') ($wnm1n tll tU t~.mp~.rnur~,.• 'du. .... ) ~..u~.~,,n J \~o.lkglln ~ _'.. ... tll.!!nn' -~.,t ... !!t'n..:. :. ... ,k_:!lln'

aor------------------------------------~--~ ___ ..... 70

60

50

• 40 . V ; . ~

~ 30

20

10

0

I tf.

I

' I

J!{l!. I

-----------

o-·· - .~-0

-10

Chonnl!l Jen l th log urn

•• --•oo

lt!!lHt. Ill i'~o.fllllll!!t. 1111111ht.r' 'hto\\lllt_ , 1\I,IH•ph!< I uiHI<

(( 11\Llll\ IJ ... lillllllllllll•l k\lll lllltlhUilh

L-egend

:X~ 0 .. =:: ~

"!:} ...... \, • .::J ...

11~ ,\ \MIH\'1 1-..1 H.,\ \'ID D .., t \MI'IH 11

ohVTOU,Jy d,II11.1!,!Cd th,lll tho'~ Ill the: prt.!\IOU' (..,JILg­OTV F1gurc 11 ... how' .1 plot lll In, ,,g.nn't V,,.., tor ,, tlc.:VIll..' ,JHlWJng thc'c ch.trdliCfl,tll' F1gurc I:! ''ll'w' !,'.., ,\, .1 fllllltl011 of the g.ltC-,OUTlC volto~gc: •\

ncg.tllvc: gm '' oht.unc.:d ,lt \1( ,.., > 9 \t Once .1g.un the ox1dc h,,, h!.!en d.un.Jgcd hcl.omtng.

,, we.tk uHH..Iut..tor •• h mdtc.llcd h~ the dcgr,,d,ltlon f fowcver. 11 .1ppcJr' th,lt .1s the g.HC-\tlUrcc volt.1gc '' muc.l"cd. 1t n:,1chc' ,, -.t.tgc .11 wh1ch the E held gcncr.ltcd '' ..,ulhcJcrH to Londuu c...h.trgc t.<~rncr.., .IW.I} from tht: mvcr,a>nl,l\cr vJ.I the g.ltc O\Jdc Th~:

c..onductJon ntt:ch.m, ... m couiJ he ctthcr Fowlcr-Nord­hcmt tulliH:IImg or Poolc-f..n:nkcl cnH..,..,ton Jut: to dl' .. tortJon ot thc ~102 conJuu•on b.tn<.l edge brought on hv tht.. o~pplu...,ttJon ol the E">D pul'c

5 2 .J. ( ategon .J.-t uta'" op/111 .. Jmlw c A lugh lc.tk<~ge through the O\Jth: \\llt!IJ prt.!\Cll( .1 tkplctlon ll.!g_HHl trom torm1ng .11 thc ... cmH..omlultoJ 'urt.ILC \\lth ohv1ou' n.:pL'rlU""IOih on thc m~tgnuu<.lc ot thc <.lr.un-<o:ourtc t..urrcnt -\\tlwugh the.! dr.un-,tHlr~,;"c

t..urrent ID, doe' ntll .1!\\,l\' rcdult: Ill Ll!fll the hrc.JI..do\\ n h l.1rg1..! l.!ttough to Jt.:dule /D.._\1\ t<~ltnr ... ot .11 k.1 ... 1 Ill' tmm thc order lll mA to th.tt ol !-LA

'i 2 5 (ategm' '-IC\1\U\l' thtuauen~ta\ The (.lct..tru •• il LlfCuJtrv ot the CT '' 'uch th.lt the Lllrrult mc.J,urcnlL'IH '' m.u.k bct\\CI!n thc dr.un ~.-ont.JLI .:nJ the: b,,,,mg ... upply HcnLc .t kJLlgt! p.nh dm::ltl) hetwcen the g.llc! .tnd th~ dr,Hn JJttu~wn lOUid rc,ult 111 the rc'''t.lllCl! type tfd(.L''I obt.unt!d Me.l<o:uremc•H" ol R<,, .md /?(.J) conhrm th.1t the contluu~nn p.HI1 I'~

hctwet:n the g.llc ,1nd the dr,un \\Jth Rto~) ..... <. Rt.-. ('ce Ltbk I)

;.,.uar! 2501 lwSI

I 200i

I ISO I

I 100J

I I I I

se i

0 0 20 30 40

5'

so,

52 h (ompunwn oj tit<.• \ltlltlfl£al dt\lnhwum uJ dc•t•tu'\ 111 em !t < af<'t:on From Frgurc lJ 1t '" 'ICL'Il th,u thcrt.: '" ,, -.tc.Hh mcrl.!.t'IC ol de\ tlC'~ 'hov.mg dc~ro~d.t·

1, (mAl

I '5 J

os .

I J

F1gur~..· t I /1...," l't, !<lfdt..\ICI.. 'htn\mgJ ... grad.tllllO \11th n..:g.lll\1!

~"' ,\t ht~h I, .. {l,lllLOr\ ~, L = ~ :i1-1-m 1\ = Ill: 1-1-111 l 0 , '" = ~ "\ Q hlt:,r..: [~0 pul-...: ~ ilh.'r E"'D puh ...

so 60 90 100 110

. -· 11..!\Hl 1.! ..: ' ,, It '"I ·h .. <k\llt.. ·•1 I 1~\111,. ! ! ~~~ .. \\Ill!.!

d, Lr 1d 1!1on \lllh Ill L 111\t.. L,'" 1' ILLl!h \, , (t.. Ill _<If\ ') 0 t>._i,ll

I "'D put ... : o lllt..r I \[) t'til-.,

IIICIKO,I\IIt I'UI" HKI,\1<..1>0\\' 1;-.. NMO...,IH\Ill..., 115

uon Lh.lr.lcten,IIL...,. whcrc.t..., thl.! c.Jt.l ... trophll.. l,ulun .. L.ltcg.onc-, only .1c<..ount tor .thout 20 per Lent ol the Ucvltco;; even .lt 250 V This c.m he <Ittnhutcd to the oxtdc hcmg ddm.1ged ,,.,. the hrc.tkdown volt.tgc ,..., reJchcd (between 50 Jnd I!Hl V) However complete brc.tkdown -,ull doe ... not .tttect the m.IJontv ol UevttC\ even .tt volt.tge' over twJtC the md\lmum hre.tkdown volt.tgc expected for J.n ox1de of the g1vcn thtckne"' Thl"' md1c.ttcs th,tt ,, longer puhc or more pul';c' Jrc

n:qUJred to crcJtC the required J.V,tl.mchc current m the ox1de to c .. tu-;c brcc.~.k.down on every occ.\'lton

53 Cumulam·e ESDeffecr

Complete tadure wc~s not ob-;crved J.S o:;oon dS one nught expect Mo~t devtCC"' sull showed ~1gns of lire ,1ttcr 100 pube' m the 50 10 250 V rdngc E\cnw.illv complete t.ulure was obtained wnh 25 pube> <~t 1000 V The'c resulh Jre 10 Jccord.10ce wnh the 1mp<~ct tontZJtlon theory of d1electnc breJ.k.do"'n

The ESD pulse w<~s del1ber.nely not ot sutflc1ent magmtude to cJuse complete brea~do" n, and the duratton of the pulse was not long enough to enable enough charge conduction to tc~ke pldce to CdU"it! <~

Lompletc shon lJrcuJt through the O\Jde A cenJJn .unount of leak.Jge through the ox1de t.tk.e~ plt~cc

uunng the pube duration ThiS mu\t be dependent on the presence of electron traps "htch. "hen hlled provtde tavour.1ble reg1on> of h1gh electnc field CJ.usmg locahzed 1mpact tOOIZdtJon and conduction pJths

The 10terdependence of the electron trJp densttv .1nd h1gh electnc fields for t1.tm.tge to occur ~~ .tn tmportant ob~crvJtiOn A dt!\JCe wnh d \en good o\lde (a lo" number of defect>) would th~retore be expected to be less susceptible 10 the 'en ,hort duratiOn albeit h1gh voltage. ESD pulse Pubes 10 excess of I kV must obvwusly generate " sufhc1ent electron cascade tn the ox1de dunng the 'hort dura· tlon to cau~e complete failure

The cumulative ESD senslltvll~ of MOS dev1ces IS

"lso of 1mportance when cons1denng the develop­ment of rehab1hty tests

; -+ £5 D and v>~de hreal.dm111

A' a result ot the study di-;cu;;;sed Jhovl! 1t 1~

propmed that the ox1de dJnt.lge CJu<ed bv the o~pplic.HIOn of ESD pulse<; 1' pnm.tnly du~ to unp<~ct tOOJl.lllon w1th111 the S10~ ElcLtron tr.1p' dn tn·

lluencc:: breJkdown but c<.~nnot bl.:' g:enl:!'r.llcLI tt..) Jnv 'IJgmhc.tnt degrl.!e dunng the pennd of ,t t\ p1c.tl ESD pul<e

Further expenments m th1s .m .. ·,, Jrc llltl!nt..kd to l.!~tJbli';h J hrm model ot O>..Jtk hrc,Jk.do"'n undl.!r .1pplted ~tre~~. both ESD ,Uld Lonwwou~ \ t llt,Jgc' wtll he 1nvc~ug.Jtcd

h CONCLL~IO'-:'i

I !Jc lo1Jo\\ 111g UIOI.ili'IOII' h,J\ L h, L 11 I L' ll hL•d I lhL r)D ..,Cil'\ltl\lt\ ol '\\101.., 1--! h h lltl]

tLmflL.'r,Jtmc LlependcrH hL-twecn 25 .1ml 2011"(" .tt volt.tgl.!' hetwcen 50 .111d JO(Kl V

2 t\ ~trong volt.1ge dcpcndl.!nce "oh,erved the dcVtl.C~ 'hOWIIlg lfltrC.I'Ied ">U'\CI.!ptlhlhty to J.t111·

.1gc '" th~.: voltJgc "r.u,cO trom 50 to IOOOV 3 F1vc L.ttcgonc' of deviL!.! ch.tr.tcten,tlt"' ,1re

t..)h,erved .1fter the ,!ppltt.tl!on ot ,1 'mgle ESO pul"'c to the g<lh! ot J dcv1te The...,c h\c c.Jh:gor· IC"' h,tvc been JnJ.Iysed .md hcntc ,, qu.tlttotlvl.! model of the hrcJ~uown prop<l\ed. The c.ne­gonc' .trl.! ( .l) No chc~ngc--ch.lr .ILh!fl"'tiC"' Me un.tltercd (h) Degr.td.ttlon-typlc,d 10 ,-V0 , char.ICtl.!r·

J~tiC"' but degrJdetlmdtL.Hmg th.ll J.un.1ge h,1.,. tJ.I-..cn pl.tcc Suth dcvJcc~ would he .1

m.IJor rcltdb!laty IMJ.:,trd (c) DegrJd,ttton wtth neg.ttJ\e gm .lt l,trge

v,,,-mdtcotivc th.tt the conduLtJon lMnd edge ot the S100 h," been Jtfccted h) the ESD puhe

(d) C.tt."troph1c f,ulurc-complete bre,tl,­down of the type cnvJs,tged when looktng for fatlures

(c) GJ.tl! to drdtn -,hort·ctrcunmg Then: I'

'ome ev1dence thdt g~ttc-drJ!Il hredkdm\ n " more prev.!lent in dcv1cc~ ot ... m.ill dtmen~Jon-; due to the effect ot g.tte-Jr.lln overlap tor ~m.lil t.hmcns10n devtce' '" d

IJ.rger perccnt.Ige ot the chJ.nnel length These hve categone~ hdve heen anJ.Iysed .wd hence .1 qudlttat1ve model of the breJkdown propo\CU

-+ Brec~kdown 1~ due to dJ.mJge of the g.lte 0\1tlc At h1gher voltdges the dJm.tge ,.., gre.ttcr

5 0\ldt d<~mage due to ESD pul-;mg ts Co.lU\Cd by the clectromc casco~de c.~.o:;. .t re~ult ot nnp.1ct IOiliZ.Itton w!thtn the ox1dc E'<IStmg clcuron trap' 10 the torm oi oxtde detech (hro~en S1-0 hond~ etc ) mukes the o\ldc more sen'lltl\C: to brec.~.kdown or damJgc. owmg to the grc.uer 1mpact JOOJZJ.tlon energ~ d\,uiJble Jt loc,Jitle<.l Jre," Jround the trapped electrons

6 A cumuiJtlve bredkdown etfect IS ob<erv eu '" the nu m her of ESD pulo;;es IS mcre.t,cd D.tm.tge re~ulb 10 devtce perform,mce hetng conunuou ..... ly degr.1ded until evt.!ntually complete hre.lk­down occurs

7 A' .1 rc,ult of the O'<Ide bre.1kdown mcLh.ull'\111. 1t w,,, ex peered thJt the numher of detect' ( 1 c tr.tp kvcl') 111 the O\ldc \\Ould mtlucntc brc.Jk.­dov.n Tht<; \\.t'l conhrmed with .111 mcrl.!.t,lllg l,ulu rt.." r.1tc bcmg oh, ... ~n cd "'hen the th.mncl k. ngt h ot the dl.!'-' ltC I'' 1111.. rt:.l,t:d \\ hlie the \\ldth " 1-..L'pt l.OO'I{.IIH

Sum mm\

(I) F1\L l...ltcgmJC'\ ol d,11n.1gL' \\l!rc n!h..:n ... d ( .1tcgon i\lo Lh.1ng~..· ( ltL:g_llf\ _ R!.!dlii..L'dl..h.lr.t~..tL'ri'IIL (,n\~r

~.;,, () Jlll.tl.!L In !!·ltL' 11\lt..h. duL ltl 1111Jl,Jd llliii/,\(1\HI Ill 11\l\k

116 \ \~llltt\.._1 I\ I ItA \'il I> ' ( \~II'IH 11

( .llcgory J Reduced th<~r.u.:tcn,ttc Ncg.l­tavc J:.n .atl.trgc V<,.., lnuco~ ... c<.l ox u.le U.un.agc

C.ttt:gory ..f C.tt.t,troph!c hrc.d~Uown B.H.fly d,un.tgcd O\H..Ie prevent\ form.lt1on of -.urf<~cc Ill\ cr,wn l.tycr

C.1tcgory 5 Lnlc.tr /IV cht~r.tllCn\ttC\ Conductmg p.tth between g.1tc .1nd dr.un

(11) The elf eel\ of the ~v.tnou' p.lr,Jmcter.., were d' follow\

Drmen\1011\ lncrc.I\C .1re.a - lncrc.l' .. c.:

c.at.l'>trophtc hrt!dkdown lncrc.t'c chdnce ot unp.H..t IOO!l<~llon hrc.d •. do'' n De~

<.rc,t'c th,mnel length- In­t.rc<~-.c bn.'.1kdm'n lnuc.t ... c c.h.Jncc of pum.h through ..,ource to drdtll Dct.rCJ\C g.tte wttlth - lncrcd'\C hrc.1 !..down lncrc.t\C ch.mcc of held dt,tortJon brc.ti-..Jo,, n G - D

Tcmpcr.nurc No t.•ttect on bch.1' 1nur up to 21111°C

Volt<~gc I ncn.:d"iC d.tm.tge J\ \ olt.tg.: tn· crc.t\ed At 50V no d~tmdge rnoo.,t 1mportdnt

At 50V <..Hcgory I mo ... t fre­quent

At 250V c.ttegone' 2 .md 3 mo ... t frequent At 1000 c.uegorv ~ olrno..,t ,tlw.ty' OCtUf\

r ncrC.I\1! tl.un,tgc A l.t rgcr p-ctcent.lgc .;;ho\\ dcgro~Licd

bch.tvtour due to tnctc,,,e d.un.tgc-hut not ,,, r<~ptdl) .~, c\pectcd

AC}I. '\0\\ llO<d: \fl:.N 1..,

\Vc Wt\h to th.mk Rogt!r Tomlmson of the Ekt.tn Hltc

Component Technology Group m the Electron~t .md Elcunc,d Engtnccrmg Dc-p.trtmcnt here .11 Lough­borough Umvcr..,lty of Tcchnolog: tor ht\ \,tlu.tblc .11tltn ..,cttmg up tht.! c'<pcruncntdl .tpjMrJtu' .tnd the dc ... tgn .md m.anuf.ll.turc.: ol ..,ornc of the 'pcu,llttcd lOillfH>ncnl\ rcqutrcd 111 the ur<.uun

The prohmg c.:qutpmcm .ttu.J the w,tft:r\ \I.CJC pro­vtdcd hv Plcv ... cy Rc,..:.trch ({.~-.well) LtU .111d \\'L 1rc c'pCtl.illy gl<~lcfulto Bill Hoh R.1y O.d..Jcy .111d ;....,lJ... Arrn...,trong tor thc1r <~"-"-l,llllC

Th1' worl-.. lhl\ hccn (.,lrncd out wnh the 'llpport of the Procurement ExclUIIvc Muw .. u \ of Dl'lliKl

Rt:Ft:RENC£:~

B A Ung1.r Ekltrn ... t,IIIL dt-.lh.trl!'- f.uh1r'-' or ''-lllllnmlu'­tor t.k""-~' ICJrh tmmal l'rtl<t't:dm~' f.l!'lwht/1/\ 1'11\llt\ ''"'fiii\1/(Ul (IJSI PJl 19~-199

~ R Y \lo" C.mlltm--d~clrthl,iliC lh-.LhMI!I. 11 \\or!.. lEE£. I rml\ ( 1111/fUn/l'llh If\ brul'i am/ ,\lmlll/tu rUn m: It clrnolo~' liiMI-S (-l) 51~-'il5 (IWQ) J J 0 D""'-r fh<.Or\ or dtdi.ClriC hrc •• J..Jtmn In \Ohd ... 1 t.lt•ur(J{htflr loc 116 c::!) 239-2-U (1%9)

-l \; Kkm, fh~ m.1X1mum lhcl~l.tn<. \lrt.ngth t)f thm '•hcon nx1Jc him' IEEE Trutn Clt•c Del' r:O:tJ (12) 2HI-1XIJ ( 1966)

~ r\ H.1rt I I T .. n~ .tnd A McKcllll,t Rd~o•htlttv ml'lucnct.' lrtun d<.l.tnc.tl mc(..,,rc" on LSI d .. ,,u_.., llltil Anmw/ f'm­cudmt:' Uduthtlm l'lrll/£1 lHilfmHWir 19XO pp 1911-196

h 1 H D1 !'ltd.wo .md \1 !'lh.trzJ..c, D•ckctnc m ... t.lhllltv .md hrc.tJ..Jm~n Ill ~qtl<. h,tndg.tr m ... ul,uor.., J V ut let Tt'cluwl 12 (I) J7-Jfl (l97'i)

7 '>: KJ....m Ckctn<. d hn:.tJ..Jm,n m thm (.hd~ctnc ftlm~ 1 £/t'(frtltlrtm \t!C 116 (7) 9fl1-()7J: (IIJ69)

;.., f) K f~orn Ekuron tr..tn ... port ,111d hr ... tJ..Jo,,n Ill S10: 1 lt'f!/ /'In 1 50 ( ~~~~ I·C::!:-I-l27 ( 1'179)

I) [ ll.tr tn Dtd~1..tru ... brt..llo.do''" m d<.t..tmulh ~>lr<."Cd thm him, ul tlh .. rm.tl StO~ J Appl Pflu .:9 Pl 247S-.:!JX9 (197:...)

10 R C Hugh'-' Ho!.. mnt"'lt!m .tnd tr.lll'pllrt tll thtn StO~ him, lppl l'fn, Lur 26 (:O.J -lJ6--l3S ( 1975)

11 .-\ J Jnn ... tht.r .mJ R \1 Htll Ekctnc.tl conduct1on m dl'ort.krLJ noll-m<.t.tlhc ltJm, G H.1....,, \f H Francomhc .mJ R \\' Hotfm.1n (<.d-.) P/n•Hn of Tltm Ftft~u H \fl9-.:!-N ( 197'i)

1.:! l \I (hhurn .tnd D \\ OrmunJ Dt<.kctnc hrc.tJ..Jm\n tn ''h~oon dto\tlk him, 1111 -.tltcon 1 \h....t-.urcm<.llt tnd rnrcrpr .. t.t· tton J thumdrt'm \o( 119 5lJI-'it,J7(JlJ7.:!)

1\ C \1 ( hhurn .md D \\ Ormund D1dcctnc hre.t!..do" n m -.dt~oon dto\tt.J.. him' on ''hcoll 11 lnllu .. ncc of rrm .. c ... smg .md m.u~n.tl.., 1 Elt'ctmclrt•m Soc 119 597-60'\ ( 1972)

I~ C ~I (),.burn .1nd E J \hnzm.~n El..ctrtc.ll cunducuon .1nd d.d .. ctm hrc.tJ..dm' n tn ''!Icon dtO'irJe film' on ..,thcon 1 Clturo,/um \oc 119 60'\-/~tiJ (197.:!)

t1utlron hwgraplueo;

-\11th -\rner,l\ekera. Born m Sn L1ni-...J Rect!l\ t!d J B Se ( Hon\) Ue!.!ree m Electrontc Enc.ml!cnng .tnd Phvs1c::. trom LlHJghbon-Jugh U Ill\ er' Et' 111 l9i3 I::.. o~t Prl!::.l!nt r~seJrclung m to thc ph\ \ll::.. ot t,ulurl!' ~~f smJllliunem.Jon 'cmJcondul.­torde"t~..t:' ,tt Loughborough Umver"tY U K leJdmg to .t Ph D m llJXO

Da\ld S Campbell. After .t l..:~.reer m mdu::.trv ovl!r 17 'l!.trli lulmmJUng m hem g. the T echmc.tl Manager of J. l.~rge C.tp.tCitor f.tctory wuhm th~ Ple::.~ey Group of ~...omp<~m~' he h.t' bt!l!n Prote ...... or nt Elt:uroml Component Te~...hnolo­~" 111 th..: D~p.trtml!nt ot El~ctron1'- .md Elcun~...al Cn­~;nL~rtn!.! at Loughborough U Ill\ er ... lt\ ofT t!chnolo!!,v ~ltH..e ilJ71 H~ '' now~ m l.h,trgc nt . .tn .tlti\C group 111 tht, .tr<.',l \\hil.h h." ..,pcu,tl mtl!re'l\ m fntercnnnc<...lion T~..l.hnology rldrtiLUI.trl\ I hll.J.. him'' "tem' and d!-.o Rdiah!hl\ An.ll\ ''"' Tht..• n:li.lhthtv worJ.. 111\oht...'' .t m.tJor ... tudv on Ft<.'ld F.ulurl! ot Lkumml Componenh 111 CqU!pmt:nt <1 \IIH .. h \\ htl.h unolve ... tht...' Uni\Cf,U\ With m,qor ekl.trontl (.omp.mte' 111 the: L K .md .!l ... o \ldth l.Oillp.uuc~ 1n Denm.trl-.. thwugh the 111\tlh'-mullot the O.inhh rnglllt:Cnng t\l.ldCill\ dt L\ng­h) \l"' ... tutli'-' .trc 111 h.111d 1111 the rcl!.thllit\ of t.ornptmcnt' whrlh .trl. ''nlv nnw 1..11111111!! 11110 u''-' .md th~. .... • 111dmlt...' Surf.tl..l...' \fountuH?.. Cleuro-.i.Htl.. Br'-·.tJ..dm\n m ~10S Stli· lOll the<. ffut 011 f,uiUft! \Jt:(.h,Uli'Ol' of U'111g \uhmiCrO!l \till.llll f)~\ I(..'-' .md 1111.111\ c •.• A ... 'trut.IUrt.•,

APPENDIX 7

Oxide Breakdown in MOS Structures Under ESD and Continuous Voltage Stress Conditions

- Proc. European Conference on Reliability, pp. 325-330, Copenhagen, 1986.

174

-- - - - --------------------------------------------------,

STOR-A-FILE IMAGING LTD

DOCUME TS

Date 12102108

OF POOR ORIGINAL

HARD COPY

Authonsed by S1mon Cockblll Issue 2 Page 1 of I

ii m nara co~y, till iS page iS UNCONTriAJLLED an{j unly val1d on d.at.e oiissue 16-May-08

At!llab•I•IV Tt!chnolol)v - Tht:ory & Ap-pliCations J Meltolt and F Jensen !Ed1torsl © Elsev1er Scu!ncc Publtshers 8 V (North Holland) 1986 325

OXIDE BRlAKDOWN IN MOS S~RUCTURES UNDER ESD

AND CONTINUOUS VOLTAGE STRESS CONDITIONS

E A A~ERASEKERA an~ V.S CAMPBELL Electrontc and Electrtcal Engtneertng Department

Loughborough Untverstty of Technology, Louqhborough, Letcestershtre, UK

Investtq~ttons have been conducted tnto the oxtde breakdown mechantsms caused by the appltcatton of latge volt~ge stresses tn the form of both Electrostatic Otscharge (ESDl pulses and conttnuous d.c voltages, on metal-oxtde-semtconductor (MOSJ structures.

~he 105 structures had been fdbrtcated on p-type stltcon wafers and had an oxtde thtckness of ; 400 A Both enhancement-tvpe a~o oepletton-type n-channel MOSFETs and MOS capacttors were consttucted on the same Nafer

Earlter expertments on the ESD suscepttbtl1ty of n-channel enhancement mode MOSFETs on the same wafer have shown there to be no temperature dependence of the breakdown although a s1gn.tf1cant. voltage dependence was observed.

~he exper1ments presented .tn thts paper have ~nvesttgated the correlat.ton between the ESD sensttlvtty of MO$ ox.tdes ar~ the cont.tnuous d c. voltage breakdown strength, w1th the 1ntentton of a~d.tng the .tcer:tf.tcat.ton of the pr.tnctple ~echan1sms assoc.tated w.tth each tvpe of applted stress

MOS capacttors were subJected to oot~ ESO pulses, 1n accordance wtth the "human-body" ~odel as ptesented tn ~IL~S~D-983C, cthoa 3015.2, and cont.tnuous d.c. voltages. The breaKdown of 1>105 capac1tors upon appltcat1on of the ESD pulse occurrea at 200 volts (Breakdown betng taken as the cond.ttton whe- t"'e 9arallel res~stance of the capac.ttor becomes ftn.tte, ~.e. reduced by a factor of approx1rnately 100.)

Ident1cal capac1tors were then s~oJected to a conttnuous voltage for approxtmately 300 sec. Breakdown then occurred at 36 volts Thts 1s a factor of approxtmately 5 less than the sens1t1vtty to ESD puls.tng, .tnd1cat1ng that two dtfferent ox.tde breakdown mechan.tsms are 1"Volved

Such observat.tons are tn keept~g ~lth the ttme-.tndependent nature of the ESD stress voltage, and t~e t.tme-dependent nature of the cont1nuous stress voltage. The t.tme-dependent breakdown 1mpl1es that the ~echantsm .tnvolved 1s that of 1mpact-ton.tzatton of charge carrters wtth1n the ox.tde unaer h.tgh-fteld condlt1ons wh.tch leads to thermal runaway and then burnout. ~h.ts Mec~antsm 1S temperature-tncependent. Ttme-dependent breakdown suggests t~at the generatton of electron-traps leacs to ult.tmate fatlure ~s th1s mechan.tsm 1s temperature­dependent, tests were carrted out to t~vest1gate the temperature-dependence of conttnuous voltage breakdown. The results snowed that cont.tnuous-voltage breakdown ts stgn.tftcantly temperature dependent between 2S~c and 200C, the breakdown voltage for a 400A oxtde decreas1ng from 36V to 2BV over thts range.

1 INTRODUCTION

~he sens.ttlvtty of MOS dev1ces to Elect .. 1c;al overstress (EOS)/Electr-ostattc Dtscharge (CSD) damage has long ~een establ1shed However, the ext~nt of devtce suscepttb1ltty ts not a ~ell deftncd ared because of the d1tttcult.tes tn sp('CtftcJ.lly locattng and 1den~:1fy1ng

a parttcular breakdown mechantsm

It lS 11tenned 1n th1s paper to a.td ttns 1nent1t1Catton of the prtnctnle phys1e.J.l p1oc-esse~ by whtch EOS and ESD m.Hnfest themselves tn metal-oxtcle-sem1conductor (MOSJ dev1ces Once the

part1cular mPchan1sm by whtch bt.:>.il{clown takes placC' IS understood, 1t b.~.:-o..,t>s

Pas1er to pt Pd.tct the effect o~ t '""

proceL on ttHJ different char.lct; lf,ttcs ol tl1• .~~vt• , ..

In an earlter paper1 , expertments on the senstttvtty of NMOS devtces to ESD were descrtbed As a result of these expertments tt was shown that the ESD senstttVtty of enhancement mode NMOS devtces was not temperature dependent Thts tS a result whtch shall be referred to later tn t 1ltS

paper tn context wtth the results presented here.

The expertments descrtbed here were conducted on both enhancement-mode and oeplet1on-moJP MOS structures Dev1ces have been su~Jected to both ESD and conttnuous voltage stress and the temperature dependence of the oxldP breakdown strength has been determJnPd It 1~ therefore poss1ble to compare the pr1n~1ple phystcal procPsses of the rPSpPcttve breakdown mechdn.tsms.

326 EA Amerasekera and 0 S Camp bell

2 THE EXPERIME:NTS

2.1 The MOS oev1ces

MOS Capacitors were used 1n these experiments. The capacltors had been fabr1cated 10 ch1ps on complete p-type slltcon ~afers and have an ox1de th1ckness of ;: 400A Both enhancement {El type and deplet1on (D) type capac1tors were ava1lable on the same ch1p on the wafer The wafers themselves were prov1ded by Plessey Research (Caswelll

The capacttors cons1st of

(a) polystllcon on thermal 510~ on enhance­ment (p-typel ~lllcon (Cl).

(b) polystltcon on thermal St02

on depletion (n-type) SlllCOO (C2)

Flgures l{a) and l(b) show eras~ ~ecttons of the two capacttors In parttcular, the dtfferent charge concentratton~ tn the £-type and 0-type capacttors are emphas~sed

s.r ... ...,...-~fp'l 1.. n" ,,. • l •' JOke V

DfFIN So

,,,

lbl

.... '"'

fLg 1 (a) E-Type Capac~tor. The Boron ~mplant ensures a po~Lt~ve thre~h­hold voltage Charge densLty at the ~urface 1.s 4 x 10 11cm-: hole~ !pi

flg. l(b) D-Type Capac1.tor The Pho~phorou~ LS implanted over the Boron. Hence the re~Ldual charge den<aty at the ~urface 1s 8.5'<10 11cm-: electr'Jns {n).

The dLmen~Lonc; of the oievLcec; were ac; followc;

The area of the capacl.torc; "' 49x!o'J (1Jm)2 PerLpheral length of the capacl.torc; ~ 9101Jm OxLrle thl.Cknec;c; = 400A

2.2 The Prncedure

2 2.1 ESD

A c;et of capacl.tors wac; c;ubJected to a "ll.ngle ESD pulc;;e generated U"lLng the "human-body" model as dec;crLbed 1.n MtL-STD 883 C, Method 3015.2 Voltagec; of magnLtudec; rang1.ng from 75V to 250V were appl1.ed to the devLcec; The parallel re"ilL"ltance across the capac1.tor was measured before applyLng the pulc;e and after appl1.cat~on of the pulse

A typ1.cal rec;Lstance acrose; the gate ox1.de of an undamaged M0S capacLtor 1.<; of the orUer of 10l~n The res1.stance br1dge used 1n th~s exper1ment however had a max1mum measur1.ng capac1tance of tn9n. Breakdown was deemed to have occurred when a f1n1.te parallel res1.stance was measured across the capac1tor A typ1cal value of such a res1.stance 1s of the order of 105n wh1ch LS very much less than that of an undamaged capac1.tor.

In order to evaluate the effect of LOOLC Lmpur1t1.es 40 the oxide on the capacitOr break­down strength, another set of capacLtors was subJected to a High Temperature Reverse 81as {HTRB) screen The HTRB screen cons1.sted of applying a voltage of -12V at a temperature of 150°C aCrOSS the CapaCltO~S for apprOXimately 5 m1nutes. This has the effect of sweep~ng impurities out of the ox1.de. These capacitors were then subJected to the ESD pulses desc~~bed above.

2.2.2 Cont1.nuous Voltage Stress

MOS capac~tors of both E-type and D-type structures were subJeCted to a voltage of increasing magn~tude of the form shown in f~g 2 Each voltage step lasted approximately 5 m1.nutes. The leakage current was measured at each voltage step, and a plot made of leakage current as a funct~on of the applLed voltage

The temperature of the wafer was ~ncreased 1n steps from room tempe~ature (25°C) to 75°C, 125°C, 150°C and 2QQ°C, the experiment being repeated at each temperature It was therefore posstble to plot the conttnuous voltage break­down strength as a funct1on of the amb~ent temperature

I

Ox1de Breakdown m MOS Structures under £SO 327

Appl1ed I vol toge

o < o.V"" 1 V

o.t > 60 sec.s

-t {~C'il rtq. 2 Waveform of the voltage used 1n the

continuous voltage stress exper~ments

RESULTS

3.1 Electrostatic D1scharqe

Table 1 gtves the results of the ESD experiments on E-type and D-type capacitors that have not been subJected to HTRB screens Typical values of capacitance and resistance are given for a Single MOS capacitor. However, some capacttors d1d show reSiStance values as low as lkQ wlth a capacitance of a Opf when damaged. The upper l1m1t was about 300kfl. Breakdown was always seen to occur at 200 volts

Table 2 gtves the results of the ESD experiments on E-type capacitOrs that have been subJected to an HTRB screen. The lower limit of res~stance iS stlll around lkn With C = OpF. The upper l~mit now is about 3Mn.

These results can be compared With those obtained in ref. 1. The Slight degradatiOn characterist~cs of the NMOS trans1stors in that paper correspond to the upper l~m1t value of res1stance in the temperature, associated w1th a still functiOning capacitor The catastrophic breakdown characteristic corresponds to the lower lim~t of resistance which 1s ; lkn assoctated With zero capac1.tance -

II£SUL•S 0r API>lYitiG ESD PULSES TO 1'105 CAPACITORS

CAPACITOR 1<0 OF AREA APPLJEO TYPICAL TYPJC-'L ...,.PE OtVIC'ES •IO'io••l' VOLTACt: C.I.PACITA!ol<:'£ III!:SISTAHCt

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O/< .,. OO'pl•t "'" " .. o '" " 0 " O/< "

•ESl1\.TS ''F APPI.JII'OG £50 PULSES 'tO ..CS CAPioC't'I'O•S "'HICH 11,\V[ &tEN HT~II SC'IItENED

C'Ai>ACITOR ~ " A•EA APPI lED TY'PICAL 'NPICAL m• OtVIClS •LO'h"'l' VOI TACt CAPACITANCt lltSISTANCt ,., L prl L-01 b.alor• •fter IMfore •ft•r

£nna,...e-nl " '" '" >00 '" O/< O/<

tn~>•M'e-nl " "0 '" >00 '" .,. O/<

Enr.•nc•-nt " .. o '" '" " . 0/< ..,

3 2 Conttnuous Voltage Stress

These results are summarised ln figures 3, 4 and S 5 capac1tors of each type were SUbJected to the stress Figures 3 and 4 show the ox1.de leakage current as a functiOn of applied voltage for a typLcal E-type capacitor and a typLcal D-type capacitor respectLvely The ox1de leakage current LS seen to increase at around 32V Ln both graphs and rises to approximately S~A at 36V. Res1stance and capacJ.tance measurements made at thls stage for the E-type capac1tor 1n f1g. 3 gave-

parallel res1stance ~ 197 kO parallel capac1.tance = 18pf

and for the D-type capac1tor in Fig 4, parallel res1stance = 4 MO

parallel capacJ.tance = 10 pF

~~ese values are compa~able With the breakdown fLgures given 1n Table 1.

Increase 1n voltage Just beyond 36V resulted Ln a rap1.d inc~ease in leakage current and burn-out occurrLng. 36V can therefore be considered to be the OXJ.de breakdown voltage due to the applLed contLnuous voltage stress.

FJg S shows t,e ox1de breakdown voltage of an E-type capacitor as a function of temperature As can be seer, t~e breakdown strength drops srarply from +36V at ; 25°C to 28V at 200°C

328 EA Amerasekera and D S Camp bell

"

..

"

"

"

"

" " " " "

F~g. 3 OA~de leakage current (!leak) vs Applled voltage {Va 01 ) for a typ1cal 8-type MOS capacJ.tor The 9parallel res1stance across the gate of the capacJ.tor ~easured after 36V had been applted '"'as 197kfl:, J.ndJ.catl.ng that breakdown had occurred.

rle.lkf~.JAI

I

j

I I I

I

"I !

•• " " " )'> )6 lJ

V (VI appl1.ed

F1g ~ Ox1.de leakage current (Ileak) vs Appl1ec voltage (Vaooll for a typ1cal D-type MOS ~apac1.tor The·parallel res1stance across the gate of tne capacJ.tor measured after J6V haa ~een applied was 4M~. lndJ.catJ.ng that brea~down had occurred

'or---------------,

•e

' ';5 > .. • ~ 2 ;; ; 0 ,. " ~ 0 • di

.. iemp C

F1.g 5 O<lde breakdown voltaqe as a funct.1on ot t•·'llperatur• t..'ld•~l cont1nuous voltaye stress condltLOOS

Ox1de Breakdown m MOS Structures under €SO 329

4 DISCUSSION

4.1 Oxide Breakdown

The breakdown voltage of 200V for an ESD pulse ts ;5 ttme~ greater than the 36V observed With a contLnuous voltage stress. The strong temp­erature dependence of the cont1nuous voltage stress breakdown Js in direct contrast to earlter results establiSh1nq rhe temperature independence of ESD breakdown Therefore it ts possible to conclude that two different oxtde breakdown mechantsms are tnvolved. As dtscussed 1n ref. 1, these two mechantsms are·

4 .1.1

a) Lmpact LOOJ.Zatton b) electron-trap qeneratton.

2,6 Impact lontzatJ.On

Impact J.OntzatJ.on occurs when free electrons iO the conductJ.On band have gatned suffictent energy to enable them to transfer enough energy to a valence electron upon colltston such t~at t~at electron iS elevated to the conductlon band. The whole process occurs J.n about 1cr: secs, whJ.ch for the purposes of thts paper can be constdered tJ.me independent HLgh electrtc ftelds (•lo6v;cm) are necessary to enable the electrons to gatn the energies requJ.~~d

4.1 2 Electron-trap Generation3

•4

The faorJ.catJ.on process can result J.n dangltng (unattached) St or 0 bonds be1.ng present in the OYJ.de wnJ.ch then become traps for charge carrters. However, J.n the presence of an electrtc fteld, 1t LS poss1ble that the lattJc<:! .t:ructure can be deformed suff1ently that thermal Vibrat1ons would create new electron traps The generatton of new electron traps has been expertmentally shown by Harart as a functL~n of both electrlc fteld and temperature . Oxtde breakdown 10 these experiments are t1me-dependent {;30 secs)

once traps are establtshed wtthtn an oxtde, the appltcat1on of an electrtc f1eld sufftctently dtstorts the Sl02 conductton bana nabltng charge to hop from one trap to nether ~hts process 1s known as hopptng onduction

raps c~n also result 1n htgh electrLc fLelds ccurr1ng 1n local1Zed areas of the S1D! he[eb; enhanc1ng the prospect of tmpact ontzat10n occurrtng.

.2 2lectrostattc Dtscharge

he ESD pulse LS of very short duratton lo-6secs) and any change produced by such u ulse Cln therefore be considered ttme­naepe"'"H. Pnt The ESD breakdown process 1 s lso te..,perature tndependent. It can, herefo1e, be concluded that tmpact •on­zatLO" IS responsible for ox1de breakdown

~dbl~ 2 Lt WdS shown that devtces wh1c~ d les~ 10n1c- tontamtnatJon 10 the oxtdr> h.1d ht'}h<"- ~SO b• P.Jkdown voltage at 250V It

tnr> .. •ut~ po~ 1ble for <•1\~crron trap~

.Jireddy avdtlablc· 1n the oxLde befor~ t 1le

appl1cat10n of the pulse to enhance the probabiltty of Impact iOntzatton and thereby reduce the breakdown voltage of the dev1ces

4 3 conttnuous Voltage Stress

The breakdown observed w1th conttnuous volt~ge stress 1S tn keep1ng With Harar•'s results The temperature rlependence and the low electrLc ftelds {cf ESDI Signtfy that electron­trap generatton and the assoctated conduction processes LS the mechantsm concerned.

4 4 Imp 1 teat 1 ons

ESD 1s shown to be due to a htgh-energy 1mpact tontzatlon breakdown mechantsm It LS sLgntftcant t~at electron traps already avadable tn the oxtde can contrtbute to ESD breakdown Hence the rlev•ce sensttJVJtV ~n ESO would be a functton of the number of electron-traps tn the oxtde. Thts has far reach1.ng 1mpl1catLOns when constdertng devtce relJ.abtltty at the fabrtcatton stage. It LS tmportant to reduce the number of traps 1n an oxtde at thiS stage and processtng techntques such as those used tn the manufacture of radtatl.on hardened devtces along wtth thermal annealtng techntques, may provtde the solutior

7•8

However, processtng tec~ntques such as 10~

tmolantatlon may result tn a ~1gh number of electron traps betng created Ln the oxtde Energtes 1n the range 20keV to lOOkeV are presently qu~te common Wtth the requtrements for hlgher ton tmplant doses at htgher energ1es betng used tn the manufacture of sub­micron devtces, Lt LS posstble that the number of traps thus created could have a stqntf1cant effect on devtce •el1abtl1ty.

5. CONCLUSIONS

1 A large dtspartty was observed Ln the breakdown voltages of MOS capac1tors c~e to (a) Electrostat1c Otscharce puls~ng {200Vl (b) Cont1nuous d c voltase stress (36Vl

2 A strong temperature dependence was observed for ox1de breakdown under cont­inuous voltage stress compared wtth earlter results show1ng that oxtde break­down under ESD pulstng was not teMperature dependent.

3. It LS therefore concluded that two dtf:er­ent mechan1sms are responstble for oxtce breakdown due to ESO puls1ng and contiruous voltage stress

4. The ttme-tndependent prooerty of the ESD pulse suggest~ that tmpact ~on1zat1on iS the mechanLsm through whiC, bred~~own ta~e~ place High localtzed electrLc-~lelos caused by electron traps already tn exist­ence wtthtn the ox1de enhance the prosoect of breakdown taktnq place. Thls has ot .. ect impltcatlons on dev1ce fabrLcatton tech­nLques Lnvo!vlng hlqh enerqy iOn tmpliirt­itiOO.

330 EA Amerasekera and D S Campbell

5 rt 15 pOStulated that OXld~ breakdown under conttnuous voltage stress LS

related to the generatton of new electron traps wtthtn the oxtde The electrtc ftelds requtred for breakdown are, there­fore, not as great as those requtred tn the case of ESD

6. ACKNOWLEDGEMENTS

Thanks are due to Plessey Research (Caswell) for the wafers used tn the study. Thts work has been carrted out wtth the support of the Procurement Executtve, Mlntstry of Defence

REFERENCES

1. E.A. AMERASEKERA, 0 S. CAMPBELL, Electro­stattc Pulse Breakdown tn NMOS Devtces. {To be publtshed) Qualtty and Reltabtltty Engtneertng Journal, 1986.

1. J J O'DWYER, The Theory of Electrtcal Conductton and Breakdown tn Soltd Otelectrtcs Clarendon Press (Oxford), 1973.

3 E HARARI, Dtelectr~c Breakdown tn Elec­trtcal1y Stressed Thtn Ftlms of Thermal StOz J App1 Phys , 49(4), pp 2478-2489, Aprt1 1978.

4 A.J JONSCHER, R M HILL. Electr~ca1 Con­ductton tn Otsordered Non-Metalltc Ptlms Phystcs of Thtn Ftlms (Ed. G. Hass, ~ H. Francombe and R.W Hoffmann.) ~. pp 169-249, 1975

5 P. OLIVO, B. RICCO, E. SANGIORGI. Electron Trapp~ng;Detrapptng wtth~n Thtn St02 Ftlms tn the ~Lgh Fte1d Tunne1ltng Regtme. J.Appl Phys., 54(9), pp 5267-5276, September 1983

6 H FROHLICH; ~heory down of Iontc Crystals pp 230-241, 1937.

of Electrtcal Break­Proc. R.Soc , A ~.

7 S S COHEN, Electrtcal Properttes of Post­Annealed Thtn StOz Ptlms J.Electrochem. Sec 12£. pp 929-932, 1983.

8 P. BALK, M. ASLAM, O.R. YOUNG, Htgh Temp­erature Annealtng Behavtour of Electron Traps tn Thermal StOz. Sol St Elec., 27, pp 709-719, 1984. -

BIBLIOGRAPHY

AJITH AMERASEKERA Rece1ved a 8 S~ (Hens) degree 1n Electrontc Engtneertng and Physt~s from Loughborough Untverstty 1n 1983 Is at present resear~htng 1nto the phys1cs of fadure~ of small dtmenston semtconductor devtces at Loughborough Un1vers1ty, UK, leadtng to a Ph.D tn 1986.

OAVID S. CAMPBELL After a career 1n tndustry over 17 years, culmtnattng tn betng the Techntcal Manager of a large capacttor factory wtthtn the Plessey Group of compantes, he has been Professor of Electrontc Component Technology tn the Depart­ment of Electrontc and Electr1cal Engtneertng at Loughborough UntversttY of Technology stnce 1971. He ts now Ln charge of an acttve group 1n thts area whtch has spec1al tnterests tn Interc-onnect 10n "~"echnology .. part tcu lar ly thtCK ftlm systems and also Reltabtltty Analysts The reltabLl1ty work tnvolves a maJOr study on Fteld Pa1lure of Electrontc Components 1n Equ1pment, a study whtch tnvolves the Unlverstty Wlth maJor electron1c compantes tn the U K and also wtth compantes tn Denmark through the 1nvo1vement of the Dantsh Engtneertng Academy at Lyngby. Also studtes are tn hand on the reltab1l1ty of components whtch are only now comtng tnto use and these tnclude Surface Mountlng, Electrostattc Break­down tn ~OS Slltcon, the effect on Fatlure Mechanisms of ust~g Submtcron S1l1~on Oevtces and ftnally GaAs structures.

' '\

\

STOR-A-FILE IMAGING L TD ~-------------------------------------------------------

DO,CUMENTS ·oF POOR

ORIGINAL HARD COPY

!

Date 12102/08 Authonsed by Stmon Cockbtll Issue 2 Page I of I

Ii m itarri cooy, tnJS page IS UNCONTROLLED and only vahd on date oi ISsue 16-May-08

APPENDIX 8

A Comparison Between GaAs MESFET and Si NMOS ESD Behaviour - Proc. ERA Seminar on ESD in Electronics

pp. 4.3.1. - 4.3.14, London, 1986.

175

A COMPARISON BETWEEN GaAs MESFET AND Si NM0S ESD BEHAVIOUR

A.J. Frankl1n, E.A. Amerasekera and D.S. Campbell Department of Electron1c and Electr1cal Eng1neering,

Un1vers1ty of Technology, Loughborough, Le1cestershire, UK

ABSTRACT

Work 1S in progress at Loughborough to 1nvest1gate ESD sens1t1v1ty of GaAs D-MESFETs and unprotected enhancement mode NMOS structures.

The work to date has revealed that NMOS structures can be severely degraded w1th ESD pulse above 200V as compared w1th 600V for GaAs MESFETs. It has also been shown that both NMOS and GaAs structures are polar1ty sens1t1ve.

The breakdown of the ox1de for NMOS devices can be expla1ned by impact 10n1sation. The effect of the Schottky barr1er to expla1n the polar1ty behav1our of GaAs 1s d1scussed.

1 INTRODUCTION

It has been recogn1sed for some t1me that one of the maJor fa1lure mechan1sms in semiconductors was electr1cal overstress (EOS) wh1ch 1ncludes dev1ce fa1lure due to Electrostat1c d1scharge pulses (ESD).

Equ1pmcnt manufacturers, users and jem1conductor manufacturers now est1mate that 60% of sem1conductor fa1lures can now be attr1buted to EOS, a large percentage of th1s be1ng due to ESD.

In order to 1dent1fy the failure mechan1sms assoc1ated with unprotected MESFET and NMOS FETs, an 1nvest1gat1on has been carr1ed out and the results are presented 1n th1s paper.

2 BASIC STRUCTURE -The two bas1c structures that have been 1nvest1gated are n-channel, depletion mode metal-sem1conductor GaAs FETs and n-channel, enhancement mode metal­ox1de-sem1conductor S1 FETs. F1gure la and b, shows the structures and 1t can be seen that they are rad1cally d1fferent.

The D-MESFET has a n-doped channel and the source and dra1n contacts are made us1ng an ohm1c metal. The gate contact 1s formed Wlth a metal la1d d1rectly onto the surface of the GaAs form1ng a Schottky deplet1on reg1on beneath the area of the gate contact.

The NMOS dev1ce has a l1ghtly p-doped channel and has n wells d1ffused to form the source and dra1n contacts. An ox1de of 400A 1s grown on the wafer, and the gate is formed w1th n+polys1l1con la1d on the ox1de.

Electr1cal modulat1on of the dra1n current is fundamentally d1fferent 1n each case.

Deplet1on MESFET operation uses the action of the Schottky depletion region, under negat1ve voltage b1as, to deplete the channel of carriers and hence decrease the current flow. An enhancement device can be ach1eved using a

4.3.1

shallow ~mplant of the n-typc channel or by a rccc~vcd gate structure.

The enhancement NMOS dev~ce is modulated by a pos~t~ve voltage on the gate wh~ch ~nduces an ~nvers~on layer beneath the gate ox~de whLch electr~cally connects the source to the dra~n, allow~ng current to flow.

3 EXPERIMENTAL WORK

3.1 INTRODUCTION

The present study has been concerned w~th ESD pulses applLed to the gate of the dev~ce under ~nvestigat~on, resultLng in a breakdown wh~ch w~ll have d~fferent causes ~n the two dev~ces. The subJect of ESD modell~ng has become of maJor ~mportance, since var~ous research centres have d~ffer~ng v~ews on the model to be adopted.

In the present war~ the ESD pulses are der~ved us~ng the MIL-STD-883C, "Human body model". The human body model compr~ses of a c~rcu~t ~n wh~ch a h~gh voltage supply charges a lOOpF capacitor through a lMQ res~stor.

The d~scharge ~s through a 1.5Kll (body) res~stance ~n ser~es w~th the f dev~ce under test. The charge/d~scharge c~rcu~ts are selected by means of a mercury wetted 2 pole relay.

The pulse generated us~ng the human body model ~s of the shape shown ~n

F~gure 2 as observed on an osc~lloscope and us~ng a low capacitance probe. The r~se time of the pulse, tRISE ~s less than 500ns, and the decay ~s approx~mately l~s. In pract~ce th~s value will vary dependLng on the load offered by the dev~ce to the d~scharge circuLt.

3.2 RELATED DEVICE GEOMETRIES

The GaAs MESFET geometry ~s shown in F~gure 3. It compr~ses of two AuGeNi ohm~c constants and a CrAu gate of d~mensLons l x 150~m. The gatejsource­dra~n d~mens~ons were l~m and 2~m respectLvely. They are fabrLcated on a 2" S~-Lon ~mplanted GaAs LEC wafer which contaLns 1500 D-FET structures. In the ma)or~ty of cases the whole actLve area was overlayed w~th poly~m~de.

The NMOS structures are fabr~cated as 3" p-type Si wafers whLch contaLned vary1ng gate d1mens1on transistors, MOS capacitors and 1ntegrated c1rcu1ts. The FETs have polys~hcon n+ gate and alloyed AlS~Cu dra~n and source contacts. gate.

They are set 1n rows, each w1th a common source and a common

3.3 PROCEDURE

The ma~n part of the experLmental programme cons~sted of puls~ng the gate(s) w~th varyLng polarLty voltages. The source and dra~n electrodes were e~ther earthed (GaAs) or left floatLng (NMOS), w~th the substrate grounded.

The gate was pulsed w~th voltages between ±50 up to ±lkv, and ~n both cases th1s gave a spread of breakdown charactcr1St1cs.

After the appl~cat~on of each pulse the dev~ces were analysed electr~cally for any change ~n the ID vs V

5 (I/V) characterist~cs. The MESFETs were

also examLned with an opt~ca~ microscope mounted on the wafer prober. F~nally the MESFETs were examined for detailed breakdown changes with the scann1ng electron microscope.

4.3.2

4 RESULTS

4.1 CHARACTERISTICS

In both cases the dcgradat~on after the appl~cat~on of one ESD pulse to the gate could be class~f~ed into one of 4 fategories, although w~th the NMOS dev~ces the behav~our is more complex. These categor~es are based on the electr1cal I/V curves for the trans~stors before and after each pulse.

4.1.1 Category l - No change

All clcctrJ.cal parameters rema1.n unaltered and the I/V curves, as seen 1.0

F1gure 4a and b rema1.n the same.

4.1.2 Category 2 - Degraded Character~st~c

Typ~cal I/V curves are shown in F~gure Sa and b. J.tsclf as a decrease 1.0 g and an 1ncrease current to source or dra1.n. m

4.1.3 Category 3 -Total Burnout

The degradat~on man~fests ~n IGL' the gate leakage

Th~s state ~s reached ~n the case of the MESFET when the I/V curves show constant res~st~ve properties as in F1gure 7. In the case of the NMOS structures total burnout ~s def~ned when ID = 0 for all values of VDS and VGS' or constant res1.st1.ve propertl.CS for all draJ.n/source confJ.guratJ.ons.

4.1.4 Category 4 - Part~al Burnout

Th~s category ~s part way between category 2 and 3. In both dev~ces the same I/V curves are encountered, an example of wh1ch .l.S g1ven in F1gure 6a. If the dra~n and source voltages are reversed the curves ~n F~gure 6b arc obtaJ.ncd.

4.2 VOLTAGE EFFECTS

The voltages appl1ed to the gate have a s1gn~ficant effect on the degradat~on of the dev~ces. It should be noted that 1 t was not found poss1ble to pred~ct the exact behav~our of any one dev~ce and the f1gures g1ven must be ~nterpreted as stat~st~cal results found by measur~ng large numbers of dev1.ces.

At voltages between +200 and +800v the MESFETs fall ~nto category 2, a degraded character~st~c after the appl1cat~on of a s~ngle pulse. The NMOS FETs fell ~nto category 2 between +50 and +200v. In both cases voltages lower than the stated m~n~mum put the dev~ces ~n category 1. (No change observed.)

Category 4, partial burnout, was encountered for the MESFETs between +800 and +lkv and for the NMOS FETs between +200 and +300v.

F~nally, category 3, total burnout, was observed at voltages greater than +lkv (MESFETs) and +300v (NMOS FETs).

4.3.3

---------------------------------------------------------------------------------------------

4.3 TEMPERATURE EFFECTS

No detal.led studl.es of the effect of temperature on changes l.n the I/V characterl.stl.c caused by a Sl.ngle ESD pulse have ~een made for the MESFETs. However for the MOSFET devl.ces l.t has been shown that temperature change has a negll.gl.ble effect on the voltage degradat1.on behavl.our as described l.n paragraph 4.2.

4.4 CUMULATIVE PULSE EFFECTS

The cumulatJ.ve effects of puls~ng the gates of the devJ.ccs resulted J.n degradatl.on (category 2), eventually leadl.ng to partl.al burnout (category 4) and l.n some cases total burnout (category 3). The extent of degradation could not be predl.cted but there was an overall dependence on the voltage magnl.tude and polarl.ty of the pulse. Figure Sa, b, and c shows the degradatl.on of MESFETs subJect to +600v pulses on a functl.on of the number of pulses appll.ed. It can be seen that the transconductance l.S decreasl.ng and l.n many cases the transistors degraded to the Sl.ngle I/V curve normally assocl.ated Wl.th zero VGS' for all values of VGS" The NMOS FETs degraded to zero IDS for all VDS' VGS' or degraded until total burnout was obtal.ned.

4.5 POLARITY EFFECTS

In both cases a polar1.ty effect was evl.dent. In sectl.on 4.2 the voltage magnl.tudes quoted for a g1.ven degradatl.on category can be roughly halved for negatl.ve polarl.ty pulses (l..e. partial burnout l.S encountered at voltages between -400 and -500 (MESFETs) and -lOO and -150 (NMOS FETs). Thl.s polarl. ty effect l.S shown l.n F1.gure 8 as a functl.On of pulse number and polarl.ty. It can be seen that the cumulat1.ve fa1.lure rate l.S greater for the ncgatJ.ve pulses.

4.6 PHYSICAL CHANGES AFTER THE APPLICATION OF AN ESD PULSE

After the appll.catl.on of an ESD pulse to the gate of the MESFET any changes l.n appearance along the gate or l.n the channel was noted. Due to the vertl.cal nature of the NMOS FETs thl.s was not possl.ble. After the appll.catl.on of a pulse of suffl.cl.ent magnl.tude to cause severe degradatl.on, or partJ.al burnout, a dJ.scolouratJ.on of the gate/source regJ.on occurred. If total burnout was encountered the dl.scolouratJ.on extended across the channel regJ.on from draJ.n to source. In general, PartJ.al burnout resulted J.n the d~scolouration between source and gate, but sometJ.mes J.t occurred between gate and dral.n. Thl.S was traced to ml.sall.gnment of the gate, movJ.ng the gate nearer the draJ.n than the source.

~CM analysJ.s of the channel regl.on, after removal of the polyJ.rnl.de, revealed greater damage to the source electrode for a negat~ve pulse, and the gate electrode for a pos~t~vc pulse.

5 DISCUSSION

5.1 DEGRADATION CHARACTERISTICS

In both dev~ccs, degraded character~stics were man~fested as a decrease ~n transconductance. Thl.S can be explal.ned by a leakage path exl.stl.ng in:-

(a) The channel between gate and source (MESFET)

(b) The OXl.de el.ther to the source, dral.n or channel (NMOS FET)

4.3.4

In the MESFET the leakage res1stance acts l1ke a potent1al d1v1der and a proport1on of the voltage wh1ch would act on the gate depletion reg1on 1s dropped across th1s leakage res1stance. Hence pinch-off of the dev1ce rcqu~rcs a greater voltage. The degraded transconductancc 1s therefore a measure of the magn1tude of the leakage path.

The NMOS FET breakdown is more complex, and the degradation character1st1~ (1.e. category 2, 3 or 4) will depend on the pos1t1on of the leakage path 1n the ox1de. If the breakdown was between oxide and the dra1n or source then part1al burnout would be obta1ned. If the breakdown was d1rectly over the channel then total burnout would be obta1ned. In the later case the presence of the leakage path in the ox1de w1ll not allow the 1nvers1on layer to form. In the former case, the leakage path w1ll s1mply drop a proport1on of the gate voltage as 1n the MESFET case.

In both cases, after a s1nglc low voltage pulse, the dcv1ces that show 'degraded characterl.Stl.cs' would st1ll be capable of d1g1.tal operat1on. They would, however, be potent1al fa1lures later 1n hfe. Such dev1ces are thus often referred to was "walk.lng wounded". In such cases, the leakage res1stance of both types of dev1ces w1ll st1ll be relat1vely large and, therefore, dev1ce operat1on is st1ll poss1ble.

5.2 CUMULATIVE PULSE EFFECTS

In both devices cumulat1ve degradat1on effects were present. It 1s post­ulated that the MESFETs degraded because the leakage path res1stance decreas­ed w1th each pulse. Hence the voltage dropped across th1s leakage res1stance 1ncreased w1.th each pulse, thus decreas1ng the transconductance.

The NMOS FETs degraded as expla1ned 1n sect1on 5.1 but the degradat1on category depended on the nature of the leakage path w1th1n the ox1de.

5.3 POLARITY EFFECTS ON ESD SENSITIVITY

In both types of dev1ces 1t was found that a negat1ve polar1ty would tend to degrade the dev1ce to a greater extent than a pos1t1ve pulse.

In the MESFET case, the act1on of the Schottky barr1er under voltage stress 1s d1fferent for each polar1ty. Th1s would account for the observed effect. ~the case of the NMOS FETs the breakdown 1s through the ox1de and 1s s~£posedly polar1ty 1ndependent. Stud1es on MOS capac1t£o structures has lead to the conclus1on that surface charge effects under the gate ox1de w1ll affect the extent of breakdown for a g1ven voltage and th1s w1ll 1nvolve polarity behav1our.

5.4 PHYSICAL CHANGES DUE TO ESD BREAKDOWN

The GaAs MESFETs burnt out between gate and source and th1s can be expla1ned by cons1der1ng the geometr1cal arrangement of the channel/gate reg1on. (The gate/source spac1ng 1s l~m wh1le the gatejdra1n 1s 2~m.) S1nce both of these electrodes are earthed then the h1ghest f1eld w1ll be created between gate and source. It 1s postulated that the ohm1c contacts have uneven edges wh1ch may also extend 1nto the channel reg1on creating local1sed h1gh f1eld reg1ons. The breakdown w1ll 1n1t1ate at the oppos1te electrode to the current 1nJect1on as observed 1n the SEM m7c9ographs. Th1s effect 1s also reported w1th D.C. dra1n/source breakdown.

• Th<' NMOS FETs showed no observable changes after puls1ng.

4.3.5

--------------------------------

5.5 SCHOTTKY BARRIER EFFECTS

A deta1led understand1ng of the part played by the Schottky barr1er 1n the degradation of MESFET dev1ces subJect to ESD pulses, 1s being evolved. However, data 1s needed on both temperature and cont1nuous voltage effects before a cons1stant model can be presented. Deta1led results 1n th1s area w1ll be presented shortly.

5.6 OXIDE BREAKDOWN

Analys1s of the results that have been obta1ned ind1cate that leakage paths created 1n the ox1de can account for the changes in the I/V curves obtained. The pos1t1on of the breakdown in the ox1de w1ll determ1ne the changes in breakdown character~stics.

4 5 6 8 PrcvJ.ous work ' ' ' 1nd1cated that OXJ.de breakdown under trans1ent h1.gh voltage stress was due to an electron cascade caused

3by avalanche breakdown

(1mpact 10n1sat1on) w1th1n the oxide. Ox1de defects, present after growth, w1ll 1nfluenc'\

0the po1nt of breakdown with1n the ox1de and also surface

charge effects w1ll affect the breakdown po1nt.

6 CONCLUSIONS

Degradat1on and burnout character1st1cs of GaAs MESFETs and S1 NMOS FETs have been J.nvestJ.gatcd.

It 1s concluded that degradat1on 1n the MESFETs 1s due to a leakage path form1ng at a h1gh f1eld po1nt 1n the gate/source region. The probab1l1lty of fa1lure is d1ctatcd by the polarity and magn1tude of the apphed ESD pulse.

In the NMOS FETs, degradat1on 1s due to ox1de breakdown by impact 10n1sat1on w1th1n the ox1de. The pos1t1on and probab1l1ty of fa1lure mode 1s also 1nfluenced by polar1ty and magn1tude of the appl1ed ESD pulse but for d1fferent causes.

7 ACKNOWLEDGEMENTS

We w1sh to thank Plessey Research (Caswell) Ltd. for supply1ng the NMOS test wafers and STC Components Ltd. for the GaAs MESFET wafers.

One of us (AJF) 1s grateful for support from STC Components Group and the other (EAA) 1s grateful for support from the MOD Procurement Execut1ve (DCVD) .

In deta1l we would l1ke to thank B1ll Holt, Ray Oakley and N1ck Armstrong from Plessey and R1chard Butl1n, Ron Eggar and Steve Bland from STC Ltd. for the1r support and advice.

8 REFERENCES

1 Amerasekera, E.A. Campbell, D.S: Fa1lure Mechanisms 1n sem1conductor Dev1ces, In the press, John W1ley, 1986.

2 MIL Standard Handbook, Method 3015.2, Sens1t1v1ty Class1f1cat1on, MIL STD 883C,

4.3.6

Electrostatic Discharge p l, August 1983.

3 Amerasekera, E.A., Campbell D.S: Electrostat1c Pulse Breakdown 1n NMOS Dev1ces. (To be published.) Qual1ty and Rel1ability Engineer1ng Journal, 1986.

4. D1Stefano, T.H., Shatzke, M: Dielectr1c rnstab1lity and Breakdown 1n W1de Bandgap Insulators, J.Vac.Scl..Technol., 12, no. 1, p 37, 1975.

5.

6

7

Klein, N: Electrl.cal Breakdown 1n Thl.n 01electric Films, 116, no. 7. p 963, 1969.

Ferry D.K: Electron Transport and Breakdown 1n Si02

, SO, no. 3, p 1422, 1979.

Ir~e, T., Nagasako, I., Kohzu, H., Sek~do, K: Reliab~lity Study of GaAs MESFETs, IEEE Trans. Ml.cro. Theo. and Tech., MTT24, No. 6, p 321, 1976.

8 Hararl., E: D1electr1c Breakdown in Electrically Stressed Thin Fl.lms of Thermal Si0

2, J.Appl.Phys., 49, no. 4, p 2478, 1978.

9 Wemple, S.H., NJ.ehaus, W.C .. , et al, Long Term and Instantaneous Burnout l.n GaAs Power FETs: Mechanisms and Solutl.ons, IEEE Trans. Elec.DevJ.ces, ED-28, no. 7, p 834, 1981.

10 Amerasekera, E.A. Campbell, D.S: Oxl.de Breakdown 1n MOS Structures Under ESD and Cont1nuous Voltage Stress Cond1t1ons, to be publJ.shed.

11 Amerasekera, E.A., Campbell D.S: ESD Pulse and Contl.nuous Voltage Breakdown l.n MOS Capac1tor Structures, to be publ1shed.

4.3.7

c

DRAIN I"" AuGcN~ Polv.~m~dc

CrAu liU

~ 0-."J ~ ... ____

-#

Schottky Deplct~on Rcg1on

ScmL-LnsulatLng Substtatc

FLgurc la MESFET Cross-scctLonal Structure

GATE

DRAIN

n+ polys~ s~o 2 (ox~dc)

Sl.lox

l

SOURCE

~

I N-type

l SOURCE

I

~--------- --i- -#1'---J, __ __,) '-------~ 1nvcrs1on 1

layer n+ rcgl.on

P-typc Substrat~

F~gutc lb N-MOSFET Czoss-scct~onal Structure

4.3.8

(

L

Volts

= SOOns

F~gure 2 "'yp~cal ESD "Human Body Pulse"

2~m

t l~m

F~gure 3 GaAs MESFET Plan Geometry

4.3.9

(t~me)

I

l~m

' t

Poly~m~de

Dra~n

(AuGeN~)

Gate (CrAu)

Source (AuGeN~)

MESFET MOSFET

ID V = Qv GS ID

(mAl (mAl

= +llv 5

5

4

3

2

1 V = -0.5v

0 () (

2 4 2 4 6 8 10

VDS (v) VDS (v)

F~gurc 4 Typ~cal I/V Plot for Both Dcv~ccs

ID MESFET ID MOSFET

(mAl VGS = Ov (mA)

5 ( 5

4

VGS = +llv 3

VGS = -0.5v 2

1

V

0 0

2 4 2 4 6 8 10

"J (v) VDS (v) DS

F~gutc 5 Dcgradat1on (Category 2) I/V Plot for Both Dcv~ces

4.3.10

ID

(mA)

so

a - As normal

so

= -0. 7v

1 2 3 4

b - W1th dra1n/source terminals reversed

V =Ov GS

V = - 0 Sv GS •

o.s 1.0 l.S 2.0 VDS (v)

F~gurc 6a, b Part~al Burnout Charactcr1st~cs

a - As normal ID b - W1th dra1n/source (mA) term~nals reversed

VGS = Ov VGS = Ov

VGS -O.Sv VGS = -O.Sv

50

0 0 o.s 1.0 l.S 2.0

VDS (v) o.s 1.0 l.S 2.0

V OS (V)

F1gure 7 Full Burnout Charactcrist1cs

4.3.11

.... ..,

.... N

a - Before b - After 10 c - After 20

ID I ID I ID V = Ov <mA> I VGS = Ov

(m A) GS (mA) VGS = Ov --5 .. J' _....--- 5"1 ~ 5

•• ~ .. - . ~ ~ VGS = -0.7v

-0. 7v 0 r= VGS

I I o.._---.----....--VGS =-0. 7v

0 2 4 2 4 2 4

VDS (v) VDS (V) VDS (v)

Figure 8 Degradation of the transconductance for a GaAs MESFET as a funct1on of the number of ESD pulses appl1ed to the gate.

10

9

+300v Pulses

8~:-------------------

6

+500v 5

4 -300v Pulses

3

2

1

oL-----~---------------------------5

F~gure 9

10 20 30 50 Number of Pulses appl~ed to gate

Transconductance degradat~on (g ) as a m

funct~on of voltage and polar~ty for a GaAs MESFET

4.3.13

APPENDIX 9

ESD Pulse and Continuous Voltage Breakdown in MOS Capacitor Structures - Proc. EOS/ESD Symposium,

Las Vegas, September 1986.

176

ABSTRACT

ESO PULSE AND CONTINUOUS VOLTAGE BREAKDOWN

IN HOS CAPACITOR STRUCTURES

E.A. Amerasekera and D.S. Campbell

Department of Electron~c and Electr~cal Eng1neer1ng

Loughborough Un>vers>ty of Technology

Loughborough Le>cestersh>re U K

Telephone >n U K 0509 222811

Telephone outs>de U K 44 509 222811

Prev>ous reported work by the authors on ESO pulse and D.C.

breakdown >n unprotected NMOS and PMOS structures has been extended by

study~ng unprotected s>ngle n and p type MOS capac>tor structures.

The effect of polar>ty on the breakdown of both n and p structures has

been exam>ned and the results have been analysed and compared w>th

ESO. A model has been developed to phys>cally expla>n the results.

1. INTRODUCTION

As dev1ces get smaller 1n s1ze, and the dev1ce dens1ty per 1.c.

1ncreases, the problem of EOS/ESD becomes s1gn1hcant to the dev1ce

manufacturer. The ex~st~ng solut1on of prov1.d1ng protect1on c1rcu1try

aga1nst overstress voltages uses up an 1ncreas1ngly larger proprt1on

of the ch1p area and can become a l1m1t1ng factor 1n Ultra Large Scale

Integrat1on (ULSI) . It 1s therefore 1mportant to obta1n an understand1ng

of the phys1cs of the breakdown process under h1gh stress cond1t1ons.

Ident1f1cat1on of poss1ble weak po1nts can then be made and by alter1ng

the fabr1cat1on process or chang1ng the dev1ce structure, less sens1t1ve

dev1ces can be manufactured.

Prev1ous work publ1shed by the authors [1,2) has shown that:-

(a) The ESD sens1t1v1ty of NMOS trans1stors 1s not temperature

dependent, but that ox1de breakdown 1s h1ghly temperature depend­

ent when subJected to cont1nuous voltage stress1ng.

(b) The voltages requ1red for breakdown w1th an ESD pulse 1s almost

a factor of f1ve greater than the breakdown voltage 1n the d.c.

case.

Hence, 1.t was suggested that ESD pulses resulted 1n breakdown

through 1mpact 10n1zat1on w1th1n the 5102

, a process wh1ch 1s a1ded by

ex1st1ng electron traps 1n S102

• Cont1nuous voltage stress1ng generated

electron traps w1th1n the ox1de wh1ch encouraged hopp1ng conduct1on

through the ox1de and eventual term1nal breakdown.

In th1s paper, further exper1.ments carr1ed out on MOS capac1tor

structures are descr1.bed. Both n and p-type capac1.tors were subJected

to pos1t1ve and negat1ve polar1ty voltage stresses. Pulsed vel tages

(s1mulat1ng ESD cond1t1ons) and cont1nuous voltages (s1mulat1ng EOS

cond1 t1ons) were apphed to these dev1ces. As a result of these

exper1ments 1t has been poss1ble to 1dent1fy the pr1nc1ple features of

the gate-ox1de capa1.ctor structures wh1.ch 1nfluence the ox1de breakdown

process under EOS/ESD cond1t1ons.

1

2. THE EXPERIMENTS

2.1 The Capacitors

The MOS capa1ctors used 1n these exper1ments were fabr1cated on

p-type and n-type s1ll.con substrates, w1th an ox1de th1ekness of

400!1.. The p-type substrates had both enhancement (E)-type capac1tors

and Oeplet1on

E-type cases

(D)-type capac1tors; 1..e. the s1.l1.con surface 1.n +

was preferent1ally doped w1th p (Boron), wh1le 1n

the

the

0-type cases the s1l1con surface was doped n (Phosphorous). Then-type

substrates only supported E-type capac1tors. Therefore, the three

capac1tor structures were;

(a) + + n polys1l1con on 510

2 on p (F1gure l(a))

(b) + n polys1l1con on 5102

on n-51 (F1gure l(b))

(cl + +

n polys1l1con on 5102

on n -51 (F1gure l(c))

The dopant concentrat1ons as follows;

(1) +

p -51 = 4.0 X 1011cm - 2

(11) 8.5 X 1011 -2

n-51 = cm

(111) +

10.0 1011 -2 n -s1. = X cm

Dev1.ce d1.rnens1.ons were;

For p-substrate capac1.tors,

Area 49 X 103 2

= ~m

Per1phery = 910 ~m

For n-substrate capac1.tors,

3 2 Area = 4.9 X 10 ~m

2

Per1phery = 280 ~m

A total of 10 capac1tors of each type were subJected to each

voltage stress ..

2.2 The Procedure

2.2.1 ESD

The ESD pulse was generated us1ng the "human-body .. model c1rcu1t

as descr1bed 1n MIL-STD-883C, Method 3015.2 [3]. S1ngle voltage pulses

of magn1tudes rang1ng from 50 volts to 250 volts of both polar1t1es

were appl1ed to the dev1ces. The parallel res1stance across the cap­

ac1tor was measured before and after appl1cation of the pulse.

A typ1cal gate-ox1de res1stance 1s of the order of 10 14n.

The res1stance br1dge used 1n th1s experunent however had a

max1.murn measur1ng capac1tance of 109n. Breakdown was deemed to have

occurred when a f1.n1.te parallel res1.stance was measured across the

capac1tor. A typ1cal value of such a res1stance 1s of the order of 5

10 Q wh1ch 1s very much less than that of an undamaged capac1tor.

2.2.2 EOS

The MOS capac1tor structures were subJected to a voltage of

1ncreas1ng magn1tude of the form shown 1n F1gure 2. Each voltage step

lasted approx1mately 5 m1nutes. Plots were made of the gate leakage-

current as a funct1on of the appl1ed voltage.

3

3. RESULTS

3.2 ESD

Table 1 presents the results of the E5D exper1ments on E-type

and D-type p-51 and E-type n-51 M05 capac1tors. Values of capac1tance

and res1.stance are g1.ven for a typ1.cal capac1tor 1.n each category ..

However, some capac1.tors d1.d show res1.stance values as low as lkil w1th

a capac1.tance of ~ 0 pF when damaged. The upper res1.stance l1.m1t was

about 300 kG.

Breakdown of the E-type p-51 capac1tors cons1stently occurred

upon appl1cat1on of a s1ngle pos1t1ve pulse of +200 volts, or a s1ngle

negat1ve pulse of -100 volts. W1th aD-type p-51 capac1tor the d1spar1ty

was less, negat1.ve pulse breakdown st1.ll occurred at around -100 volts,

w1th pos1t1ve pulse breakdown at 175 volts. E-type n-51 capac1tors

showed no polar1ty dependence. Because of the structural d1.fferences

between the p-51 and the n-51 capac1tors 1t 1s not poss1ble to compare

d1rectly the absolute values of the respect1ve breakdown voltages.

However, the relat1.ve d1.spar1.t1es 1.n the pos1.t1.ve and negat1.ve polr1.ty

breakdown voltages are comparable.

C-V curves were made before and after the dev1.ces were subJected

to an E5D pulse. F1.gure 3 shows a C-V curve for an E-mode p-Sl.

capac1tor before and after appl1cat1on of a +150 volt E5D pulse.

F1gure 4 shows a C-V curve for an E-mode n-S1 capac1tor before and

after appl1cat1on of a +50 volt pulse. The p-51. capac1.tor appears

unaffected by the sub-breakdown threshold voltage wh1le the n-51 cap­

ac1tor 1s s1gn1f1cantly affected.

3.2 EOS

The gate-ox1de leakage current (I 1 k), as a funct1on of the g ea appl1ed voltage, 1s shown for p-51 capac1tors 1n F1gure 5 and for n-51

capac1.tors 1.n F1gure 6 .. It must aga1n be emphas1sed here that the

p-S1 capac1tors d1ffer 1n s1ze from the n-51 capac1tors. The absolute

values of the leakage currents and breakdown voltages of the two d1ffer­

ent structures cannot be d1rectly compared. What 1s 1mportant are the

rates at wh1ch I 1 k 1ncreases at the onset of breakdown. g ea

4

In F1gure 5, the curve for an E-type capac1tor shows a large

polar~ty effect. A sharp ~ncrease ~n I 1

k ~s observed at around g ea

-30 volts, compared w~th a much more gradual ~ncrease ~n I 1

k w~th g ea pos1t1ve voltage stress. Th~s asymmetry ~s less obv~ous for D-type

p-S 1 capac1 tors, where the rate of 1ncrease ~n Ig leak at negat~ve

voltages ~s s~m~lar to that for E-type capac~tors, but the pos~t~ve

voltages show a much sharper 1ncrease 1n

show great symmetry between pos~t~ve

I 1

k. E-type n-S~ capac~tors g ea

and negatJ.ve I 1

k values, g ea ~nd~cat~ng that the polar~ty of the apphed voltage had an almost

negl~g~ble effect on the breakdown threshold voltage of these structures

l.n compar~son to the p-S~ capac~tors.

Typ~cal c-v curves as a result of pos~t~ve and negat~ve D.C.

voltage stresses are shown ~n F~gures 7 and 8 respect~vely for E-type

p-s~ capac~tors. A pos~t~ve voltage stress of +36 volts l.S seen to

1ncrease the capac~tance m1n1ma and d1stort the well of the C-V curve

but no lateral sh~ft along the voltage ax~s ~s observed. By compar~son

a negat~ve voltage stress of -30 volts resulted ~n a large lateral

sh1ft 1n the negat~ve d1rect~on along the voltage ax1s, but otherw1se

no d1stort1on of the C-V curve was observed.

4. DISCUSSION

4.1 Introduction

The maJOr po1nt 1n sect~on 3 above, was the extent of the

polar~ty effect on the breakdown thresholds of d1fferent MOS capac~tor

structures under stress cond1t1ons s~mulat1ng both EOS and ESD.

Prev1ous workers have observed that MOS structures w1th n-type

surfaces had

There 1s also

lower breakdown thresholds than p-type surfaces [4, 6]. +

ev~dence to show that the breakdown threshold w1th an n

polys1l1con gate as cathode 1s lower than when a less n-type surface

1s the cathode [7]. Th1s d1spar1ty between the breakdown thresholds

of the p and n-type structures has been attr1buted to 1ntr1ns1cally

h1gher defect dens1t1es 1n S102

f1lm grown on n-type wafers, and the

use of d1fferent ox1dat1on furnaces for n and p-type mater1als [ 5] •

However th1s explanat1on 1s not cons1stent w1th both the d.c. and

pulsed voltage stress observat1ons outll.ned 1n Sect1on 3, wh1ch 1nd1cate

that the 1n]ect1on of electrons 1nto the S10 2 must be cons1dered [8].

5

4.2 Continuous Voltage Stress Breakdown

Electrons can be ~nJected across the 5~-5~0 2 potent~al barr~er 3.leV) e~ther by Poole-Frankel (P-F) em~ss~on [9, 10] or by ~uantum

mechan~cal tunnell~ng [ll, 12].

In the case of P-F em1SS10n, trapped charge-carr1ers ga1n

suff~c~ent thermal energy from the external appl~ed electr~c f~eld to

overcome the potent1al barr1er at the 1nterface. S1nce the mechan1sm

1s therm1on1c, 1t must be s1gn1f1cantly affected by temperature.

Exper1mental observat1.ons, descr1.bed 1n an earl1er paper, do show th1s

to be true for MOS capac1tor structures under cont1nuous voltage stress

cond~t~ons [2]. The effect of the stress voltages both pos~t~ve and

negat1.ve on the C-V curves 1.nd1.cate that 1.nterface states are be1.ng

f~lled or empt~ed depend~ng on the polar~ty of the appl~ed voltage and

the ~n~t~al cond~t~on of the state [9, 13]. Charge movement across

the ~nterface may therefore, be cons~dered to be tak~ng place under

D.C. stress condltl.ons.

The tunnelhng current at the ~nterface ~s dependent on the

electron dens~ty at the surface by means of the supply funct~on N(E ), X

s1nce

where

transm.lSSl.On

E X

~

J = ej D(E )N(E )dE Am-2

X X X

0

Eq. (1)

~s the energy of the ~nc~dent electron, D(E ) ~s the X

probab~l~ty and N(E ) ~s the number of electrons ~n the X

energy range E to E X X

+ dE X

ava~lable for tunnelhng through the

barr~er. N(E ) ~s based X

on occupat~on stat~st~cs [14,

surface under the ~nfluence of a h~gh electr~c f~eld

16]. An n-type -1 ("' 10 MV cm )

would have a h~gher supply funct~on than a p-type surface ~n the same

electr~c held. Also the h~gher number of occup~ed states ~n the

n-type surface would ~mply a h~gher D(E ) compared to a p-type surface X

[8]. Hence, the tunnell~ng current for electrons at the s~-5~0 2 ~nter-face would be greater for an n-type accumulat~on surface compared to a

p-type tnvers1on surface under the same b1.as1.ng condl.tlons.

6

---------- --------- - - --- --

In summary therefore EOS breakdown l.S 1n1t1ated by electrons

be1ng l.n]ected from the S1 1nto the S102

• The h1gher the concentrat1on

of electrons 1n the s11lcon (N0

) , the greater the leakage current,

g1v1ng r1se to the I 1

k vs V 1

curves obta1ned for the three MOS g ea app

capacJ.tor structurese

4.3 Pulsed Voltage Stress Condl.tl.ons

The result of the ESD exper1ments showed that the breakdown

thresholds for p-type MOS structures w1th pos1t1ve voltages were almost

tw1ce as much as the negat1ve voltage breakdown threshold. Th1s dl.ffer­

ence became less as the s1l~con surface was made more n-type, aga1n

suggest1ng a charge 1nJeCt1on effect. However, the effect of the

voltage pulse on the surface must be cons1dered 1n the analys1s [18].

When a large pos1t1ve pulse 1s appl1ed across an n-type capac1tor

structure, the surface

The maJOrJ.ty carr1er

accumulates maJOrJ.ty carr1ers (J..e. electrons). -12

response t1me 1n S1l1.con 1.s about 10 secs

[17], hence the surface has t1me to go 1nto strong accumulatJ.on w1th1n

the n.se t1me of the applled pulse (<500 ns). Electrons, lnJected

from the strongly accumulated SllJ.con surface, together w1th electrons

from traps and 1mpur1ty s1tes already 1on the S102

, tunnel through to

the S 10 2

conductl.on band. Here 1mpact J.OnlzatJ.on takes place and

results 1n ox1de damage [2]. In the case of a negat1ve polar1ty ESD + pulse, the n polys1l1con gate becomes the 1n]ect1ng electrode. Th1s

surface has a large enough concentrat10n of electrons to be able to

match the process descr1bed for a pos1t1ve ESD pulse. The breakdown

thresholds are, therefore, very s1m1lar 1n the two cases for an n-type

surface.

In a p-type surface, an 1nvers1on layer cons1st1ng of electrons

1s 1nduced by a large pos1t1ve voltage. Here

carr1ers and the1r response tLme 1s of the

the electrons are m1nor1ty -2 order 10 secs to 1 sec,

wh1ch 1s outs1de the 500 ns r1se t1me of the applled pulse. In1t1al

1nJect10n of charge carr1ers 1nto the S102

conduct1on band, therefore,

takes place from 1mpur1ty and trap Sl.tes 1n the S102

l.tself. However,

dur1ng the decay t1me of the pulse (dependent on the res1stance and

capacJ. tance of the ox1de) the surface has t1me to go 1nto strong

1nvers1on .. By th1s t1me, though, the electrl.c f1eld across the OXJ.de

would have decreased thereby affect1ng the charge 1n]ect1on current.

7

The consequence 1s that p-51 capac1tors would have a h1gher breakdown

threshold than n-51 capac1tors. A negat1ve voltage pulse would have a

breakdown threshold s1m1lar to that of an n-type structure because the + 1nJeCt1ng electrode would be the n poly 51 gate. Therefore, the

pos1t1ve voltage breakdown threshold for p-51 capac1tors 1s h1gher

than the negat1ve voltage breakdown thresholds. The more p-type the

s1l1con surface, the h1gher the breakdown threshold 1s l1kely to be.

8

5. CONCLUSIONS

(1) A s1gn1f1cant polar1ty effect was observed for the ox1de break­

down thresholds of p-51 and n-51 MOS capac1tors under both

cont~nuous and pulsed votage stress cond1t1ons, s1mulat1ng EOS

and E5D respect1vely.

(2) Under E05 cond1t1ons 1t was found that the more p-type the

s1l1con surface, the lower the gate leakage current w1th appl1ed

voltage.

(3) Under ESD condltlons n-Sl. MOS capac1tors were shown to be more

sens1t1ve to damage than p-Sl capac1tors. Polar1ty effects

were negl1g1ble on n-Sl capac1tors, wh1le the breakdown threshold

of p-51 capac1tors w1th negat1ve E5D pulses was almost half the

magn1tude (100 volts) of the pos1t1ve breakdown threshold (200

volts).

(4) A model of ox1de breakdown based on charge 1n]ect1on processes

at the 51-5102

1nterfaces has been proposed.

(5) For E05 cond1t1ons, the 1n]ect1on current 1s proport1onal to

the electron supply funct1on wh1ch 1ncreases w1th more n-type

dop1ng.

(6) For ESD condltlons, the maJOrlty and m1norlty carr1er 1n

accumulated and 1nvested surfaces, respect1vely, must be con­

S1dered. When electrons are ma]or1ty carr1ers (1.e. 1n n-type

surfaces), the response t1me to the appl1ed pulse 1s fast enough

to respond 1mmed1ately to the voltage. On the other hand, when

electrons are m1nor1ty carr1ers (1.e. p-type surfaces) the

response t1me l.S much slower than the pulse r1se t1me. As a

consequence, strong 1nvers1on only occurs w1th1n the decay t1me

of the pulse, and therefore the effect1ve electr1c held 1s

lower than that appl1ed to the dev1ce. Hence, p-51 capac1tors

have a h~gher ox1de breakdown threshold from n-51 capac1tors.

(7) These conclus1ons are exper1mentally JUSt1f1ed.

9

6. ACKNOWLEDGEMENTS

We thank Roger Tomllnson for hl.s help l.n sett1ng up some of the

experl.mentatl.on. Plessey Research (Caswell) Ltd., provl.ded the wafers

used ~n th~s work and we are grateful to them.

Thl.s work has been carrl.ed out Wl.th the support of the Procurement

Execut~ve, M1n1stry of Defence, U.K.

10

7. REFERENCES

1. AMERASEKERA E.A., CAMPBELL D.S., Electrostat1c Pulse Breakdown

1n NMOS Dev1ces, Qual. and Rel. Eng. Int., .!_, pp. 107-116,

1986.

2. AMERASEKERA E.A., CAMPBELL D.S., Ox1de Breakdown 1n MOS

Structures Under ESD and Cont1nuous Voltage Stress Cond~t~ons,

Proc.European Rel.Con (RELCON), pp. 326-330, 1986.

3. MIL-STD-883 c, Test Methods and Procedures for M1croelectron1cs,

U.S. Department of Defense, Wash1ngton D.C., August 1983.

4. OSBURN C.M., ORMOND D.W., D1electr1c Breakdown 1n S1l1con D1ox1de

F~lms on S~l~con 1. Measurement and 1nterpretat1on, J.Electro­

chem.Soc., 119, pp. 591-597, 1972.

5. OSBURN C.M., ORMOND D.W., D1electr1c Breakdown 1n S1l1con D10x1de

Fl.lms on SJ.l1.con. 1.1. Influence of process1.ng and materJ.als,

J.Electrochem.Soc., 119, pp 597-603, 1972.

6. OS BURN C .M., WEITZMANN E .J., Electr1cal conduct10n and d1electr1c

breakdown 1.n Sl.l.tcon Dl.OXl.de f1.lms on Sl.ll.con, J .Electrochem.

Soc., 119, pp. 603-609, 1972.

7. CHEN H-C, HOLLAND S. E. , HU C. , Electr1cal Breakdown 1n Th1n

Gate and Tunnell1ng Ox1des, IEEE Trans.Elec.Dev., ED-32, pp.

413-422, 1985.

8. AMERASEKERA E.A., Fa1lure Mechan1sms 1n MOS Dev1ces, Ph.D.

Thes1s, Loughborough Un1vers1ty, U.K., 1986.

9. SZE S.M., Phys1cs of Sem1conductor Dev1ces, 2nd Ed1t1on, W1ley

(New York), 1981.

10. JONSCHER A. K., E1ectron1c Propert1es of Amorphous D1electr1c

F1lms - Th1n Sol1d F1lms, l• pp 213-234, 1967.

11. FOWLER R.H., NORDHEIM L., Electron em1ss1on 1n 1ntense electr1c

f1elds, Proc.Roy.Soc., A 119, pp. 173-181, 1928.

11

12. STRATTON R., F1eld Em1ss1on from Sem1conductors, Proc.Phys.Soc.,

B, 68, pp. 746-757, 1955.

13. MANY A., GOLDSTEIN Y., GROVER N.B., Sem1conductor Surfaces,

North Holland Publ1sh1ng Company (Amsterdam), 1965.

14. PENLEY J .C., Tunnelllng through th1n fllms w1th traps, Phys.Rev.,

128, pp 596-602, 1962.

15. DUKE C. B., Tunnell1ng 1n Sol1ds, SoLSt.Phys.Supp., 10, (Ed.

Se1tz F., Turnbull D., Ehrenre1ch H), 1969.

16. KRIEGER G., SWANSON R.M., Fowler-Nordhe1m electron tunnelllng

1n th1n 51-5102-Al structures, J.App.Phys., ~. pp. 5710-5717,

1981.

17. NICOLLIAN E.H., BREWS J.R., MOS (Metal Ox1de Sernconductor)

Phys1cs and Technology, W1ley (New York), 1982.

12

TABLE 1

RESULTS OF ESD EXPERIMENTS USING POSITIVE AND NEGATIVE

VOLTAGE PULSES ON E-TYPE AND D-TYPE NMOS AND E-TYPE DMOS CAPACITORS

CAPACITOR NO: OF APPLIED TYPICAL TYPICAL TYPE DEVICES VOLTAGE CAPACITANCE RESISTANCE COMMENTS

(V) (pF) (kQ) before after before after

E-TYPE NMOS 10 +150 20.0 20.0 0/C 0/C O.K.

E-TYPE NMOS 10 +200 20.0 16.5 0/C 150 BREAKDOWN

E-TYPE NMOS 10

I -75V 20.0 20.0 0/C 0/C O.K.

E-TYPE NMOS 10 -100V 20.0 17.0 0/C 65 BREAKDOWN

D-TYPE NMOS 10 +150 13.0 13.0 0/C 0/C O.K.

D-TYPE NMOS 10 +175 13.0 9.0 0/C 50 BREAKDOWN

D-TYPE NMOS 10 -75V 13.0 13.0 0/C 0/C O.K.

D-TYPE NMOS 10 -100V 13.0 9.0 0/C 50 BREAKDOWN

E-TYPE PMOS 10 +50 V 11.5 11.5 0/C 0/C O.K.

E-TYPE PMOS 10 +75V 11.5 7.0 0/C 75 BREAKDOWN

E-TYPE PMOS 10 -5ov 11.0 11.0 0/C 0/C O.K.

E-TYPE PMOS 10 -60V 11.5 6.0 0/C 2.16M BREAKDOWN

-----<.\ POL YSILICON n· ) FIELD

-, __________ _., OXIDE

___ I + Arsen1c 1rnp1ant (n ) 11 -2

10.0 x 10 cm

F1gure 1(c) An E-Mode n-51 MOS Arsen~c ~mplant at

(c)

+ Capac~tor, ~nd~cat1ng the n -type the Sem1conductor Surface

Applied t voltage I

o <~V~ 1V ~ t > 60 secs

~vi.__...,..... __________ _ 1""-C.t--j

t (secs l

ig 2 - Form of the cont1nuous voltage stress as applied to MOS structures.

F>gure 3(a) C-V Curve of E-Mode p-5> MOS Capac>tor, undamaged.

~-

F1gure 3(b) C-V Curve of E-Mode p-S1 MOS Capac1tor after appl1cat1on

of a s1ngle ESD pulse of +l50V

-.

F1gure 4(a) C-V Curve of an Undamaged E-Mode n-51 MOS Capac1tor

I '

F1gure 4(b) C-V Curve of an E-Mode n-51 Capac1tor after appl1cat1on

of an ESD Pulse of + sov

----E-mode

--- D-mode

I g leak I (nA)

40

30

20 I I

10 ,

/ ./

-40 -20 -10 10 20 30 40 50

-10 ... I -20

Vappl C volts

I -30

I -40

I I

F1gure 5 Graph of ox1de leakage current (Ig leak) as a funct1on of

the appl1ed stress voltage for p-S1 MOS Capac1tors

F1gure 6

I i (nA)

4.0

3.0

2.0

1.0

-so -40 -30 -20 -10 10

-1.0

20 30

Graph of Ox1de

«f the Appl1ed

-2.0

-3.0

-4.0

-s.o

-6.0

Leakage Current (I 1

kl as g ea

Stress Voltage for an E-Mode

40 so

a Funct~on

n-S1 capac1tor

---Before Capac1.tance

:::;;--. -'- • -After

-2V 0 +2V

Ul

" 0

" c ,;

" c 0 u

" "' " ... "' " 0

" ,; 0

"' a. "' u

Ul

~ ,; Ul I a. Q)

"' 0 :.: I

"' ... 0

Q)

> " " u ::> I u

::>

"' M +

" "' Ul Ul Q)

" " Ul

Ql

"" "' " .... 0 ::>

Capac1tance Before

"' " 0 After c ...

w c 0 u ... QJ w ..... ~

... 0 w ... u ~ a. ~ u \/) 0 >: ... Ul I > a. 0

M QJ I '0 0 w >: ~ I w "' "' ""' QJ 0 ...

'"' QJ Ul

-4 -2 > ... "' 0 +2

" "' u ~ '-'

> ~

I 0 u >