failure analysis of sram devices

Sarma S. GunturiOperations Engineering,

Texas Instruments Inc. Dallas, Texas, USA

FAILURE ANALYSIS OF FAILURE ANALYSIS OF SRAM DEVICESSRAM DEVICES

1

• Provide understanding of the components of memories with SRAM

• Review the operation of SRAM

• Introduce the Electrical Fail Signature

• Understand Interaction of Testing and PhysicalFailure analysis

• Explain the role of electrical fail signature inyield loss due to design,test and processsensitivity

• Explain the method of physical failure analysisfrom electrical fail signature

PurposePurpose

2November 16,2004 ISTFA2004

• Introduction• Devices ,Physical and Electrical layout• SRAM Components and Circuit • Operation of SRAM • Testing of SRAM and Electrical fails• Electrical fail signature and physical failure analysis

• Case study 1 Process Sensitivity• Case study 2 Test and Process Sensitivity• Case study 3 Design Sensitivity• Case study 4 Process,Design and Test Sensitivity

•New Failure Analysis Challenges for 90 nm and beyond

OutlineOutline


PROBE DATA

PROCESS DATA

DESIGN

FUNCTION

TEST

FUNC

TION

PROC

ESS

FUNC

TION

ELECTRICAL

BIT SCOPE

PHYSICALPHYSICALFAILUREFAILURE

ANALYSISANALYSIS

Introduction


Read / WritePrecharge

Write PrechargeWrite Nchannel

Decode

Read 4:1Local mux “LO”

Local muxHigher Order

Local SensePrecharge

PchannelsenseNch sense

Pull Down

SRAM Array

Devices ,Physical and Electrical layout


SRAM CONSTRUCTIONAL ANALYSIS



7

Vdd

Vss

T1 T2

T3 T4

T5T6

Pass Transistors (Accessing cell for read & write)CMOS 6T SRAM Electrical Circuit

Inverter 1 Inverter 2


November 16,2004 ISTFA2004

T3 T4

T2T1

T5 T6


8

Vdd

Vss

T1T2

T3 T4

T5T6



9

Vdd

Vss

T1 T2

T3 T4

T5T6

T3 T4

T2T1

T1T1

T6T5



10

Vdd

Vss

T1 T2

T3 T4

T5T6



11

Vdd

Vss

T1 T2

T3 T4

T5T6

T3 T4

T2T1

T6T5

T3 T4


T1 T3

T2T4T5

T6

Vdd

Vss

T1 T2

T3 T4

T5T6



Vdd

Vss

T1 T2

T3 T4

T5T6

T1

T3

T2

T4

T5

T6



Bit

Bitbar

N3(P)

N4(P)N1

N2

P1

P2

Word Word

Vss

Vss Vdd

Vdd



13

5A66A

7

8 9

10

14

12

11

5

4B

4A

4

3C

3B

3A

3

21

15

16

RPDIFF5 RPDIFF6

RCT7

MP5

MN1

MN3

MN2

MN4

MP6

RCT3RCT1

RD1

RBIT

RCT8

VEE1

VEE1

RCT8A

RBIB

RCT2

RCT4RCT5

RS4

RD2

RP1

RP3

RCT6

VEE2

VEE2RS3

BIT BIB

VCC

RP2

Single Bit Cell SchematicDevices ,Physical and Electrical layout


PROBE DATA

PROCESS DATA

DESIGN

FUNCTION

TEST

FUNC

TION

PROC

ESS

FUNC

TION

ELECTRICAL

BIT SCOPE


ANALYSISANALYSIS

SRAM Components and Circuit


Precharge

Word Line

Write Select

VDD VDD

Multiplexer

Bit

line

Bit

line

bar

Enable

Sense AmplifierD D bar

SRAM Components and Circuit


VDD VDDPrecharge

Word Line

Multiplexer

Bit

line

Bit

line

bar

Enable

Sense Amplifier

Write Select

DATA DATA bar

Operation of SRAM ------ WRITE


VDD VDD

Precharge

Word Line

Multiplexer

Bit

line

Bit

line

bar

Enable

Sense Amplifier

Write Select

D D bar

Operation of SRAM ------ READ


Vdd VddVdd

Wordline = Vdd

Vss

BITBIT

T1 T2

T3 T4

T5 T6D

Logic “1” is T1 is OFF and T2 is ON

Operation of SRAM


Vdd VddVdd

Wordline = Vdd

Vss

BITBIT

T1 T2

T3 T4

T5 T6DD

Logic “0” is T1 is ON and T2 is OFF

Operation of SRAM


PROBE DATA

PROCESS DATA

DESIGN

FUNCTION

TEST

FUNC

TION

PROC

ESS

FUNC

TION

ELECTRICAL

BIT SCOPE


ANALYSISANALYSIS

Testing of SRAM and Electrical fails


DC PARAMETER TESTINGDC PARAMETER TESTING

SRAM TESTING

Laser Repair

Processing

TESTING

Fab Processing



Types of Fail Categories during Test

REPAIRABLEFAILS

NOMINALGEC

GROSSFAILS

DC / PARMFAILS

(shorts opens)

GOALMove REP die to NOM die

GROSS die fail is extrapolated from REP die



ELECTRICAL FAIL SIGNATURE

SBIT – Single Bit SPC – Single Partial ColQBIT – Quad Bit MPC – Multiple Partial ColDBIT – Double Bit SPR – Single Partial RowDBRE/O – Double Bit Row Even / OddMPR – Multiple Partial RowDBCE/O – Double Bit Col Even / Odd

Electrical fail Signature and Physical FA

SBIT – Single Bit DBIT – Double Bit MPC – Multiple Partial ColMFC – Multiple Full Col


PROBE DATA

PROCESS DATA

DESIGN

FUNCTION

TEST

FUNC

TIO

N

PRO

CESS

FUNC

TIO

N

ELECTRICAL

BIT SCOPE


ANALYSISANALYSIS

26

Electrical fail signature and physical failure analysisCase Study 1 Process Sensitivity


All Other Contact Reticles

Repeater Defect Electrical Fail points towards a CONTACT issue

Contact Reticle XXXXXXX



Significantly higher percentage fallout for COL 127 and Row 458 on Block 1 --> repeater defect


All Other Contact Reticles Contact Reticle XXXXXXX


Electrical Fails INDICATED MBIT FAILS PFA LED TO MISSING VIAS

Case Study 1 Process Sensitivity


Electrical Fails MPC FAILS PFA LED TO BLOCKED MET 4



Electrical Fails SBIT FAILS PFA LED TO BLOCKED POLY GATE




Electrical Fails DBIT FAILS PFA LED TO MISSING CONTACTS


MISSING CONTACT

VDD CONTACTS

QBIT (Quad bit)


Electrical Fails QBIT FAILS PFA LED TO BLOCKED VDD CONTACT


COL. 141 COL. 142

Row 8


Electrical Fails DBIT FAILS PFA LED TO MISSING Vss CONTACT



Electrical Fails DBIT FAILS PFA LED TO MISSING Vss CONTACT


PROBE DATA

PROCESS DATA

DESIGN

FUNCTION

TEST

FUNC

TION

PROC

ESS

FUNC

TION

ELECTRICAL

BIT SCOPE


ANALYSISANALYSIS

Electrical fail signature and physical failure analysisCase Study 2 Test and Process Sensitivity


Problem: Multi Probe fallout for a Test Electrical fails catching ~50% of fails SBIT

Solution: Change the test methodology to catch 100% fails



Failed Bit

Bit1 Bit2 Bit3T1 T2 T1 T2 T1 T2

H L H L H L“0” “0” “0”

L H H L H L“1” “0” “0”

Write

L H L H L H“1” “1” “0”

Read

VSS

VSS

Vdd



Electrical Fails SBIT FAILS PFA LED TO MISSING SALICIDE

39



Electrical Fails SBIT FAILS PFA LED TO MISSING SALICIDE

40



PROBE DATA

PROCESS DATA

DESIGN

FUNCTION

TEST

FUNC

TION

PROC

ESS

FUNC

TION

ELECTRICAL

BIT SCOPE


ANALYSISANALYSIS

41

Electrical fail signature and physical failure analysisCase Study 3 Design Sensitivity


Fail Distribution by Column

0%5%

10%15%

20%

0 1 2 3 4 5 6 7Column Number

% O

ccur

ranc

e



Col 0 1 2 3 4 5 6 7



WRITE” 0” P-channel

FA Methodology: Technique selection criticalCan only find this fail with backside etch



FAILED DIE

GOOD DIE

FAILED DIE

GOOD DIE


FA Methodology: FIB45November 16,2004 ISTFA2004

PROBE DATA

PROCESS DATA

DESIGN

FUNCTION

TEST

FUNC

TION

PROC

ESS

FUNC

TION

ELECTRICAL

BIT SCOPE


ANALYSISANALYSIS

Electrical fail signature and physical failure analysisCase Study 4 Design, Test and Process Sensitivity


47


Increase VOLTAGE and SBIT fails decrease

0.94V test 2.4V test


48


Summary:Fails are row dependent – ESDA lists fails as ROW ODDBut on the array…the rows are actually EVEN ROWS

Wafer 10 Wafer 11

0 – 506 0 - 2201 – 25 1 – 142 – 586 2 - 2153 – 20 3 - 6

Data for 0.94VROW modulated by 4Data above screened for SBIT fails only

Observations:Fails are Row dependentNo Column dependencyChanges from lot to lot.Present theories:O Gate misalignment and trenching at SWN Etch.O Ct misalignment


49


R13 C156

R137 C168R145 C139

R201 508

12/12 fails wereBULLET HOLES inNMOAT across the VSS CNT.

9/12 were DBIT3/12 were SBIT

SBIT

SBIT

DBIT

DBIT


50


BULLET HOLES in NMOAT across the VSS CNT.November 16,2004 ISTFA2004

51


R219 C265 R349 C507

R503 C161R5 C154R373 C500

R25 C8

R509 C256R509 C140SBIT DBIT

DBITDBIT

DBITDBIT

DBIT

DBIT


Bit

Bitbar

N3(P)

N4(P)N1

N2

P1

P2Word

Word

Vss

Vss Vdd

Vdd

New Failure Analysis Challenges for 90 nm and beyond


gnd

gnd

vdd

vdd

bit

bitb

T gateT gate

1/2

1/21/2

1/2 1/2

1/2

1/2

1/2



Per Cell2 Non Shared - Stretched Contacts2 Non Shared S/D Contacts2 W/L Row Shared Cont/Via12 VSS Col Shared Contact2 VSS Quad Shared Via1/Via22 B/L Col Shared Cont/Via1/Via22 VCC Col Shared Cont/Via1/Via2Normalized Per Cell4 + 8 Shared = 8 Contacts 6 Shared + 2 Quad = 3.5 Via1’s 4 Shared + 2 Quad = 2.5 Via 2’sNormalized ESDA FailSBIT – Cont x 2 + 2 Stretch Cont.DBC – Cont x 3/Via1 x 2/Via2 x 2DBR – Cont x 1/Via1 x 1QBIT – Via1 x .5/Via2 x .5Poly to Gate Contact Like FailMetal 1 Via 1 Like Fail + SBIT

VIA 2:

DBC: ½ x 4 = 2QBIT: ¼ x 2 = ½ QBIT / DBC = .25VIA 1:DBC: ½ x 4 = 2QBIT: ¼ x 2 = ½DBR: ½ x 2 = 1QBIT / DBC = .25QBIT / DBR = .5CNT:DBC: ½ x 6 = 3BIT: 1 x 4 = 4DBR: ½ x 2 = 1DBC / BIT = .75DBR / BIT = .25DBR / DBC = .33




NANO PROBE PLAN VIEW TEM55November 16,2004 ISTFA2004

PASS GATE

Blocked Poly EtchRetro grated Etch profile

56



Provided an understanding of the components of memories with SRAM

Reviewed the operation of SRAM

Introduced the Electrical Fail Signature

Understood Interaction of Testing and Physical Failure analysis

Explained the role of electrical fail signature in yield loss due to design,test and process sensitivity

Explained the method of physical failure analysisfrom electrical fail signature

What we have coveredWhat we have covered


Michelle Boyer, Mark Dexter,,John Masnik,Patrick Miller,Jose Ramon, Trevor Tarsi

For providing valuable inputs

Special Thanks to Special Thanks to


failure analysis of sram devices

Documents