facilitating cross-fpga platform designs using “virtual...
TRANSCRIPT
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Facilitating Cross-FPGA Platform Designs Using “Virtual” Platforms
Angshuman ParasharMichael Adler
Joel Emer
VSSAD, Intel
{angshuman.parashar, michael.adler, joel.emer}@intel.com
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Outline
• History and Motivation• Virtual Platforms• Hybrid Hardware/Software Modules• Demo
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History and Motivation
Model
XUP BoardLEDs and Switches
(image source: xilinx.com)
Top Level Wires
BDPI
Software SimulatorProcesses
(image source: intel.com)
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History and Motivation
XUP Model “Sim” ModelTop Level Wires BDPI
XUP BoardLEDs and Switches
(image source: xilinx.com)
Software SimulatorProcesses
(image source: intel.com)
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History and Motivation
Platform Independent Model
XUP Front PanelTop Level Wires
“Sim” Front PanelBDPI
front_panel.writeLED()
Plug N Play
Virtual Platform
XUP BoardLEDs and Switches
(image source: xilinx.com)
Software SimulatorProcesses
(image source: intel.com)
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Virtual Platform
• Set of Abstractions– Provide common set of functionalities across multiple
physical-platforms• Intel FSB• Bluesim/Vsim• PCI-express• XUP
– Leverage Asim Plug N Play• Minimize module replacements/recoding while moving across
platforms
– Functionality + Efficiency
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Virtual Platform
Channel IO
Exe
Decode
Device 1
Virtual Devices
Fetch
Mem
Timing + Functional Modules
Virtual PlatformPlatform Interface
Physical Platform
Device 2Device 0
Soft Connections
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Virtual Platform on XUP
Exe
Decode
VGA
Virtual Devices
Fetch
Mem
Timing + Functional Modules
Virtual PlatformPlatform Interface
LEDsSwitches
MemoryFront Panel
Soft Connections
VGA On-BoardMemory
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Virtual Platform on Simulator
Channel IO
Exe
Decode
VGA
Virtual Devices
Fetch
Mem
Timing + Functional Modules
Virtual PlatformPlatform Interface
Bluesim
MemoryFront Panel
Soft Connections
Std. I/O
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Virtual Platform on Intel FSB
Channel IO
Exe
Decode
VGA
Virtual Devices
Fetch
Mem
Timing + Functional Modules
Virtual PlatformPlatform Interface
FSB
MemoryFront Panel
Soft Connections
SoftwareSupport
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Hybrid Hardware/Software Modules
• Split module functionality between FPGA and software
• Leverage Virtual Platform Infrastructure
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Hybrid Modules
Channel IO
HRRR Client + Server
FPGA Modules
Virtual Platform
Platform Interface
Channel IO
HRRR Client + Server
Hardware Software
Software Modules
MemoryFront Panel
ExeDecodeFetch
FuncModelControl Decode
Front Panel Memory
HAsim Remote Request/Response (HRRR)HAsim Remote Request/Response (HRRR)
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HRRR: Intel FSB
Channel IO
HRRR Client + Server
FPGA Modules
Virtual Platform
Platform Interface
Channel IO
HRRR Client + Server
Hardware Software
Software Modules
MemoryFront Panel
FSB Driver
ExeDecodeFetch
FuncModelControl Decode
Front Panel Memory
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HRRR: Simulator
Channel IO
HRRR Client + Server
FPGA Modules
Virtual Platform
Platform Interface
Channel IO
HRRR Client + Server
Hardware Software
Software Modules
MemoryFront Panel
UNIX pipe
ExeDecodeFetch
FuncModelControl Decode
Front Panel Memory
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Hybrid Modules• Server module
– Publishes the following:• init() method name (e.g. fetch_server_init())• RRR service string (e.g. “FETCH”)
– Build process collects these and generates global services table– Server main reads services table (during pre-processing) and
registers all service modules by calling init()• Client module
– Reads global services table– serviceID = serviceTable.search(“FETCH”);– reqID = RRRClient.sendReq(serviceID, params…)– result = RRRClient.getResp(reqID);
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Hybrid Modules (cont.)• Module definition
– hybrid_fetch_unit.awb• %sources –t BSV –v PUBLIC hardware_fetch_unit.bsv• %sources –t CPP –v PUBLIC software_fetch_unit.h• %sources –t CPP –v PRIVATE software_fetch_unit.cpp
• Build process– Collects BSVs and generates “hardware” bitfile or
simulation binary– Collects CPPs and generates “software” binary
• Runtime– Software binary loads bitfile onto FPGA, or forks off
simulation “hardware” binary– Software sends “start” HRRR request to Hardware
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Demo
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Backup Slides
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“Sim” Front Panel
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Hybrid Front Panel
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Running on Bluesim…