fabrication technology pixel designece434/winter2008/imaging2.pdf · 2008-04-03 · r.i. hornsey,...

1R.I. Hornsey, University of Waterloo

Fabrication TechnologyandPixel Design


CCD Operation

• The CCD is operated by “pouring” charge from

one potential well to the next

» using appropriately pulsed electrodes

• That article also discussed the ways in whichCCD arrays can be scanned

• However, it did not really address theimplications of the technique

» what we will find is that the CCD needs a number ofspecial features in order to work effectively

» this is reasonable; CMOS designs are optimised forlow power consumption, speed and flexibility, whileCCDs are optimised for CCD imaging

• The advantages of CCDs include

» large fill factor (no “opaque” transistors)

» high sensitivity

» low noise levels

» large-area formats (e.g. DALSA 4096x4096)


Charge Transfer Efficiency

• The essential part of the CCD operation is thatall the charge must be transferred from gate togate

» well, 99.999% anyway!

» the completeness of this charge transfer is dictated bythe number of steps required to get the charge out ofthe array ...

• We define the charge transfer efficiency (η) to bethe fraction of the well charge that is transferredat each step

» in the worst case, the charge from the shaded pixelabove is transferred (n + m) times

vertical transfer (m)

horizontal transfer (n)outputnode


• So the fraction of the original charge thatremains is given by

≈ η(n + m)

» the fraction of the original charge collected as afunction of CTE is

• CCDs are able to achieve the required chargetransfer efficiency

» but it needs specialised techniques

» and it makes the sensor susceptible to, for example,radiation damage

array size

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

1E-2

1E-1

1E+0

0.95

0.95

50.

96

0.96

5

0.97

0.97

5

0.98

0.98

5

0.99

0.99

5 1

Fra

ctio

n c

olle

cted

CTE

256x256

512x512

1024x1024

4098x4098


Why is η ≠ 1?

• There are two main causes for loss of charge inthe transfer

» lack of time to complete the transfer

» charge trapping

• Of course, this means that the next chargepacket may gain charge left behind by theprevious one

• Charge transfer occurs by a combination of

» carrier diffusion

» carrier drift

• Charge transfer by carrier diffusion ismaximised by

» short gates

» a high diffusion coefficient

» for electrons in p-type, the diffusion coefficient is about3x that for holes in n-type

drift

diffusion


• The drift is assisted by careful design of thetransfer gates

» to achieve a fringing field so that carriers are sweptinto the next well

» the fringing field is larger for lower substrate dopingand closer, shorter gates

• So the time required to get 99.99% transferefficiency as a function of gate length, for 3substrate doping levels (i.e. fringing fields), is

Yang fig 13.10

E = 0 E ≠ 0

no fringing field with fringing field


Overlapping Gates

• The requirement for gates that are closertogether (to assist fringing fields) is tough tomeet

» the spacing must be sub-micron

» but CCD processes usually have feature sizes of 2µmor so (because of large area, deep diffusions etc)

• Therefore gates are made so that they areoverlapping

• Such a process requires the deposition of atleast two separate layers of poly-Si gates

» unlike a conventional digital CMOS process whichuses only one

» and appropriate isolation processing

gate 1

gate 2


Charge Trapping

• Charge trapping causes electrons to get “stuck”in the well

» thereby removing them from one charge packet

» and releasing them at into another packet at a latertime

» they cause both transfer inefficiency and image lag

• Trapping occurs because there are defects inthe c-Si at the interface with the SiO2

» energy levels are created within the Si bandgap

» electrons “fall” into these traps

» the only way out is back up again (may be a largeenergy difference)

• The time constant for trapping << time constantfor release

» ttrap ≈ 10-9s (depends on electron concentration

» trelease ≈ 10-11 – 10-3s (depends on trap depth)

SiO2 Si

surface states

Ec

Ev


Reducing Charge Trapping

• One way to reduce the effects of chargetrapping is to keep the traps permanently filled

» so-called “fat zero”

» giving Qtotal = Qfz + Qsignal

» Qfz ≈ 20% of full-well capacity

• This works well, but has the disadvantage ofreducing the dynamic range

» because some of the well is always filled

• Modern processing technology is quite good atminimising surface states

» but there are always some left

• So the best way of reducing their effect is to

» remove the interface

» or at least move the charge storage away from theinterface

• The result is known as a buried channel CCD


Buried Channels

• The surface states affect

» charge transfer efficiency

» dark current (more easily generated when there aremid-gap states)

» noise

• So buried channel devices use extra implants tomove the “active” area of the CCD away fromthe Si-SiO2 interface

• The doping is such that the n-type is fullydepleted

» the exposed Nd+ ions enhance the positive potential

from the gate

» and creates a potential minimum that is away from thesemiconductor surface

» typically the n-type is 0.3µm thick & Nd ≈ 3.1016 cm-3

n-type

p-type

channel


• The potentials for empty and partially full wellsare as follows

• As the well fills, the channel moves closer to thesurface

» and eventually the charge packet interacts with theinterface, as before

VG

M O S

Qn = 0

Qn ≠ 0

φs

φs

VG

M O S

p-Si p-Sin-Si

φch

φch

VG

VG

VG

VG


• In addition to the reduction of charge trapping,BCCDs have another advantage

» fields increase more with depth below the surface

• Hence, the charge transfer is both morecomplete and faster

» provided you have enough voltage on the gates toachieve the greater depletion depth

• However, the main drawback of the buriedchannel approach is that the total charge-handling capability is reduced

» because the “capacitor” on which the charge is storedis smaller, since the “plates” are further apart

» this difference may be about a factor of 3

• While we have now covered some of the basicbackground of the CCD, two more additions areneeded

» something to stop the charge spilling sideways out ofthe CCD

» something to handle charge when the well overflows

in out

channel definition


Channel Definition

• There are two common methods for channeldefinition

• Channel-stop implants

» the threshold voltage for channel formation isincreased beyond the gate voltage by the p+ implants

» so the channel only forms in the region in-between

• Stepped oxide isolation

» the gates are moved further away from the substrate,thereby reducing the field underneath

» called LOCOS (LOCal Oxidation of Silicon)

p+ implants

p-Si

+10V

p-Si

+10V


Vertical Anti-Blooming

• Remember that one of the image artifacts –blooming – was caused by charge from onebrightly illuminated pixel spilling intoneighbouring pixels?

• Vertical antiblooming is a compact method bywhich to drain away excess photo-generatedcarriers

» in cross section, the device has the p+ channel stops

» and the n- buried channel layer

» a non-uniform p-implant, leading to a “weak” point atwhich the spill-over will occur

p+

n-Si

n-p+

p-

“weak” spot in net p-implant

VG = 8V

p-n-

spill-over

depth

potential


Charge Readout

• The clever part about using charge as the signal(rather than voltage or current) is that we canconvert charge to voltage with a high degree ofsensitivity

» by using a capacitor; V = Q/C

• So if we make C small enough, we get a largevoltage for a small charge

» typically 10µV per electron

» so a full well of 105 electrons gives an output of 1V

• The corresponding capacitance is about 16fF

» so the diffusion must be small and lightly doped

• So now the tactic of waiting longer to integratemore charge on the pixel makes sense

» we pass on discretised packets of charge, rather thana continuous current

» because the conversion method is more sensitive

n+ floatingdiffusion

p-Si

Vout


Fabrication

• Having seen how a CCD works, we can now lookat what fabrication processes must be optimised

• We will find that a good CCD demands aprocess that is substantially different from otherfabrication technologies, notably CMOS

» and the trends of “mainstream” technologies areexactly to opposite to those required for CCDs

» indeed, some trends are also bad for CMOS imagerstoo – see later!

• The main issue is that CCDs are, by today’sstandards, macroscopic devices

» and need to be that way for effective imaging &charge transfer

• While CMOS technology, with its standardlibraries and wide availability is getting evermore microscopic

» for higher speed

» and lower power consumption

• CCD fabrication is complex with typically 15 - 25masks

» so we will only look at a the basic features


Requirements

• We can already summarise some of mainconditions

• Double (or more) poly-Si process

» for overlapping gates

• Deep, complex implants which define

» buried channel and p-well (with VAB)

» channel stops

• Relatively high operating voltages

» to get a good potential well in the buried layer

» typically 10 - 20V

• The serial nature of the CCD means that,conventionally, all of the video data passesthrough a single output node

» this is good because it reduces errors due tocomponent mismatch

» but the subsequent electronics has to able to copewith the video-rate data

» which is tough without speed-optimised devices

• To reduce this problem some CCDs are sub-divided and have several outputs


p-Well• The p-well is formed from implanted B ions

» ~100keV & ~1012 cm-3

• Under the photo-sensitive elements, the locationof the well “weak” point is defined by maskingout the implant

» a thin SiO2 layer is used to protect the surface fromdamage due to the implantation

• Implantation is followed by “drive in”

» the wafer is heated to ~1100°C for 10 hours

» the dopants diffuse downwards and laterally

» Llateral ≈ 0.75Ldownwards

» this fills in the gaps between the implants to give the“weak” point required for VAB

• The final depth of the p-well is ~2.5µm at theshallow point and 3.0µm elsewhere

maskB+

as-implanted

after drive-in


Channel Stop Implant

• The p+ channel-stop regions are again formedusing ion implantation

» B+ ions at 50keV and 2 x 1013 cm-3

• This implant is driven in during the hightemperature cycle (>1000°C) used next to growthe gate oxide

» to a final depth of about 1µm

• A trade-off here is that driving the p+ implantdeep enough also causes it to spread sideways

» taking up valuable space between the rows of pixels

• An important fact to note is that there areseveral high temperature process steps, eachrequiring temperatures in excess of 1000°C, e.g.

» p-well drive in

» channel drive-in

» gate oxide

» inter-poly oxides between gates

• So the final depth of the implants is a function ofthe cumulative effects of all these steps


Gate Oxide Thickness

• The oxide layer that isolates the gates from thechannel is grown using the same high-temperature step that drives in the channel stop

• The original protective SiO2 layer is removedand the wafer cleaned

» thermal oxide offers the best Si – SiO2 interface

• A typical gate oxide is 80nm thick

• Compared with values for modern CMOSprocesses (< 10nm), this is very thick

» and is needed because of the higher CCD operatingvoltages

» 10V as opposed to 3.3V (or less)

• Later fabrication stages include

» deposition and patterning of several poly-Si layers andinter-poly dielectrics

» (this gets tricky because of the surface topography)

» metal layers and contact vias

» n+-implants to make source/drain regions at the CCDinput and output

» colour filters and/or microlenses


CMOS technology

• In this section we will take the ideas of opticaldetection and examine how they can be appliedto practical optical detectors

• We also need to know how the fabricationtechnology influences the performance of thesensors

• So we will first look briefly at CMOS technology,and then dwell longer on how the futuredevelopment of CMOS will affect image sensors

• In the second half of the section, we will discussthe four basic types of CMOS pixels

» passive pixel photodiode

» linear active pixel photodiode

» logarithmic active photodiode

» photogate active pixel


Fabrication of CMOSImagers• The first part of the idea of using “standard”

CMOS technology for imagers is to use awidespread, accessible process

» with well-developed design tools

» standard design libraries

» fast turn-around time

• The second part is that fully integrated camerasystems can be built on a single chip, featuring

» low power consumption (low voltage operation)

» small, robust, and inexpensive

» integrated clocking and addressing

» focal-plane image processing

» A-D conversion, signal encoding

• We will find that, while the second part isbecoming true, there may be some problemswith the first part

• Here, we examine the trends of CMOStechnology and their implications for fabricatingimagers

» we will also compare briefly CCD and CMOStechnologies, and consider the hybrid CCD/CMOS


Features of Sub-micronCMOS Technology• In the following few pages, we will examine the

evolution of CMOS technology

• A simplified cross section through a sub-micronCMOS process is shown below to illustrate therelevant features

fieldoxide

substrate

epitaxial layer

gateoxide n & p wells

interconnectsand plugs

source/drainjunctions

Ti, W, or Cosilicide layer

Lgate


Effects of TechnologyScaling• One of the “selling points” for the surge of

interest in CMOS imagers has been theattraction of using standard processing to

» reduce development costs

» reduce fabrication costs

» reduce dependence on a single supplier

• However, the question was naturally askedabout how the rapid development of these“standard” processes would influence theimager performance

• The following pages are based on the 1994Semiconductor Industry Association roadmap

» the updated 1997 version applies even more so!

• Each aspect of scaling will be consideredindividually, along with the potential impact onCMOS imagers

» the seminal work on the subject is by Wong, from IBM(see references)


Feature Size• A new generation of CMOS devices is developed

every three years, or less

» device dimensions are less than 0.7 times those of theprevious generation

» 0.25µm technology is in production

• This is driven by the desire for

» lower power consumption

» higher speeds

» increased functionality

• Additional impact on CMOS imagers

» improved fill factor

» improved conversion efficiencies

BBBBB

BB

B

B

B

B

0

0.4

0.8

1.2

1.6

2

1980

1985

1990

1995

2000

2005

2010

Min

imu

m f

eatu

re s

ize

(µm

)

Year

good forintegratedcameras too!


Lower VDD• Partly forced by reduced dimensions

» because electric fields cannot be too high

» e.g. hot carrier effects & tunneling

• Partly for lower power consumption (P ∝ VDD2)

• The curve below clearly shows the trendtowards VDD ≈ 1V

• Impact on CMOS imagers

» reduced analog voltage swing, VDD - VT

» hence, reduced dynamic range

» analog signal processing becomes difficult

BBB

BB

B

B

BBBB

0

1

2

3

4

5

1980

1985

1990

1995

2000

2005

2010

Su

pp

ly v

olt

age

(V)

Year


Brews’ Rule

• When the channel lengths of MOSFETs becometoo short, so-called short-channel effectsbecome apparent

• The main effect of this scaling is to reduce thecharge under the gate

» which ideally is a function just of the gate potential

» but changes due to the depletion width at the drain,and hence with VDS

• Short- and long-channel effects can besummarised as follows

source drain

gate

increasing VDS

IDS

VDS

VGS

short channel

long channel


• A rule of thumb for determining the minimumacceptable device length has been developed byBrews

• Where

» xj is the junction depth in µm

» tox is the oxide thickness in Å

» and Ws and Wd are the source and drain depletionwidths in µm, respectively

• Impact of short channel effects on CMOSimagers

» increased off-current of MOSFETs (increasesexponentially as VT is reduced) is a potential issue forsome architectures

» p-n junction tunnelling current adds to the pixel darkcurrent arising from thermal generation

logIDS

VGS

high VDS

low VDS

logIDS

VGS

high VDS

low VDS

Lmin ≈ 0.4 x jtox Wd + Ws( )2[ ]1 3

long channel short channel


Substrate Doping

• WS,D are dependent on the substrate doping ofthe wafer

» this is increasing over the years in order to minimiseshort-channel effects

• Impact on CMOS imagers, due to associatedreduction in minority carrier diffusion length, Ln

» good – reduces crosstalk between pixels

» bad – reduces effective volume for photo-chargecollection

B

BB

BB

B

BB

B

B

B1E+16

1E+17

1E+18

1E+19

1980

1985

1990

1995

2000

2005

2010

Su

bst

rate

do

pin

g (

cm-3

)

Year


Oxide Thickness

• As the supply voltage decreases, so too mustthe threshold voltage

» although this is also affected by substrate doping

• VT is dependent on 1/Cox, and therefore tox mustbe reduced, since Cox = εSi/tox


» reduced voltage swing, as before, since VDD scalesfaster than VT (see later for plot of trend in VDD - VT)

» gate tunnelling current potentially important for someMOS capacitor devices

Year

BBBBB

BB

B

B

B

B

JJJ

JJ

J

J

J

J

J

J

0

10

20

30

40

0

0.2

0.4

0.6

0.8

1

1980

1985

1990

1995

2000

2005

2010

Min

imu

m o

xid

e th

ickn

ess

(nm

)

Th

resh

old

vo

ltag

e (V

)


Source/Drain JunctionDepth• Source and drain junction depths are important

in determining the influence of the draindepletion region on the MOSFET characteristics

» as indicated in Brews’ rule

• More lightly doped n- and p-wells may be a fewtimes deeper than the junction depths

» so, ~ 0.5µm at the moment


» reduces the effective volume for collecting photo-charge, hence reduced quantum efficiencies

» possible increase in surface effects

BBBB

B

B

B

B

BBB

0

0.1

0.2

0.3

0.4

0.5

1980

1985

1990

1995

2000

2005

2010

So

urc

e/d

rain

d

epth

(µ

m)

Year


New materials

• One major change that has been made in thematerially-conservative semiconductor industryis the introduction of silicide layers

» to reduce contact and sheet resistances ofsource/drain regions and gates, respectively

» usually WSi2, TiSi2, CoSi2

• This is important for imagers because silicidesare relatively opaque to visible light

• At the 0.5µm technology level, silicide layers canbe optionally masked out

» but it is not clear whether this will continue to be thecase in future technologies

• Mendis has reported that a pixel’s sensitivity isreduced to 20% of its former value in thepresence of the silicide layer

» which is consistent with the silicide transmissionspectrum


Conclusions

• Wong’s conclusions may be summarised asfollows

» full integration offered by CMOS devices is stilladvantageous

» sub-0.5µm technology will not be optimal for imagingwithout some process changes

» other costs (packaging, testing) are more importantthan the extra costs incurred by using a slightly non-standard process

• While Wong’s conclusions may be technicallycorrect, it is still not clear what influencetechnology scaling will actually have

» cheaper and wider access to older technologies mayremain more attractive

» process tweaks do not just raise costs, but alsoreduce second sourcing options and portability

» even if advanced technologies are used, the systemdesign may mitigate many disadvantages without theneed for tweaking

• In the end, the balance depends on theapplication

» and it is likely that a continuum of techniques willdevelop between pure CCD and pure CMOS


Comparison of CMOS &CCD Technologies• We can write down broad requirements for each

technology

• CCD

» gate oxide thickness ≈ 800Å

» p-well depth > 2.5µm

» channel stop depth ≈ 1µm

» channel depth ≈ 0.8µm

» typical operating voltage ≥ 10V

» several poly-Si and inter-poly dielectrics needed

• CMOS

» gate oxide thickness ≈ 50Å

» well depths ~ 0.5µm

» source/drain implants ≈ 0.1µm

» operating voltage ≤ 3.3V

» digital process has 1 poly, analog has 2 polys

• A comparison of these figures makes clear whyit is difficult to integrate the two technologies

» essentially, a full-featured combination would requirealmost all the stages from both processes

» which means maybe > 30 masks


Combined CMOS/CCD

• To date, the reduced yield and increased costshas not made a combined CMOS/CCD processviable

• The combined process is neither standardCMOS nor standard CCD, and so requiresextensive development expenses

» and the frequent result is that neither part will workparticularly well

• Several processes have been reported whichclaim to preserve the quality of each technology

• Suni Imaging Microsystems are advertising ahybrid process which has

» only “3 or 4” more masks than standard CMOS

» 5V operation

» and works by separating out CCD and CMOS regionson the chip

» CCDs can run satisfactorily at 5V provided their areais enough to ensure a reasonable full well capacity

» for high resolution – small pixel area – higher voltagesare generally required to achieve the full well, so somecompromise must have been made here


• The alternate approach is to start with a CCDprocess and add in extra process modules

» e.g. that reported by Eastman-Kodak

» extra CMOS steps added

• Such a process required 4 additional masks and3 extra implants

» a BiCMOS process is also demonstrated, with 3additional masks and 3 implants for a NPN transistor

• Despite the demonstrated feasibility ofCMOS/CCD hybrids, the idea has not yet takenoff

» possibly because few places have access to both setsof fabrication facilities and design experience

substrate active area poly 1 poly 2 n+ source& drain

annealing photo-diode

isolation metals 1,2

n-well Vt adjust

p+ source & drain

extra CMOS steps


CMOS Photodiode Pixels

• We have already seen something about how wemight build pixels using CMOS technology

• Now we will look in more detail at the differentdesigns of pixels that have been fabricatedusing CMOS

• Although there is one dominant sensor type –the photodiode – there are several possibleimplementations

• And there are additional topologies which drawon CCD ideas

• Here, we will not dwell greatly on either the restof the in-pixel circuitry or on the support circuits

» these will be the topic of a future section

• In passing, we will mention some of the sourcesof noise in the imaging arrays

» these too will be drawn together later


“Photon Flux IntegratingMode”• The operation of a photodiode in the “charge

integration” mode discussed earlier is notrecent

» it was proposed in 1967 by Gene Weckler

• In the original proposal, the circuit waspresented much as we did before

» although Weckler also demonstrated that a MOSFETcould serve adequately as the switch

• We can follow a simple analysis for the outputvoltage of the diode as a function of time, afterthe diode has been reset

• Here, we note that the current in the capacitormust be equal and opposite to the photocurrent

» because the diode is isolated

» and we will ignore the dark current

resetVdd

V

0C

diodeiphoto + idark


• Hence

• For a n+p diode, the capacitance is

» where A is the diode area, and NA is the acceptorconcentration in the substrate

• So we find

» where V0 is the diode built in voltage, and Vreset is thereset reverse bias

• And thus

• While this expression includes a term in A, thediode area, this cancels out because

» where I0 is the incident flux of photons

C j V( ) = A2

2qεSiNA

V t( )

12

C V( ) dV t( )dt

= −iphoto

A2

2qεSiNA( )1 2 2 V[ ]Vreset +V0

V t( )+V0 = −iphotot

V t( ) = Vreset1 2 −

iphotot

A 2qεSiNA( )1 2

2

iphoto ∝ I0A


• So the collected voltage is independent of thediode area for a given photon flux

» if we think of V = Q(A)/C(A), then both Q and C areproportional to area so the voltage is unchanged

• If we calculate V(t) as a function of time for

» A = (10µm)2, Vreset = 5V, NA = 1016 cm-3 , and iphoto =1pA (small), we find the following curve

• The voltage drop is almost linear for short times

» which is what we want!

» remember this does not include dark current

0

1

2

3

4

5

6

0 20 40 60 80 100120140

Vo

ltag

e (V

)

Time (ms)


Fill Factor

• So why are we worried about the fraction of thepixel that is light-sensitive – the “fill factor” – ifthe area cancels out?

• This is because the foregoing analysis is onlypart of the story

» capacitance does not come just from the pixel area

» and we must consider sources of capacitance externalto the pixel

» and there are other unwanted sources of charge

• Firstly, capacitance arises both from the “floor”(the area capacitance) of the implanted regionand from the “wall” (the periphery)

CA

CPCPCP

CA


• For a 0.5µm process, the capacitances at zerobias are

» Cja = 4.7 x 10-4 F/m2

» Cjp = 3.2 x 10-10 F/m

• For a (30µm)2 pixel, the periphery represents0.08 of the total capacitance

» but this rises to 0.3 for a (7µm)2 pixel

• Alternatively, the area has scaled by 0.05 from(30µm)2 to (7µm)2

» but the capacitance has only scaled by 0.07

• Thus the smaller pixel generates less voltagethan does the larger one

» because iphoto/Ctotal has scaled by 0.05/0.07 = 0.7

• Secondly, the photodiode is connected to theoutside world

» either to the column bus or to an in-pixel voltage buffer

Cnode

Cpixel(A)


• Hence, there is a fixed capacitance

» i.e. not dependent on the pixel area

» so Vout = Q(A)/[Cpixel(A) + Cnode]

» which falls as A decreases

• Thirdly, there will be sources of unwantedcharge that are non-linearly dependent on pixelarea

» e.g. dark current comes from both area and periphery

» and/or “reset” noise

» so Vout = [Q(A) + Qnoise]/Cpixel(A)

» therefore as A falls, the signal-to-noise ratio falls

• Fill factor is particularly important for CCDsbecause the sensing capacitance is external tothe pixel

» so the more charge you collect during the integrationtime – i.e. the larger the photosensitive area – thebetter

• A larger photosensitive area also gives a largerfull well capacity

» which should give a larger dynamic range

» provided the limiting factor on the minimum resolvablesignal does not depend on pixel area

» usually, it is later elements that limit the dynamicrange


• Weckler’s method for reading out the integratedcharge was to measure the voltage across aload resistor required to reset the pixel

» switch, S, is closed to reset the pixel to a reverse biasof V

» for a period of tint, S is opened, allowing thephotodiode to discharge at a rate approximatelyproportional to the incident illumination

» when S is closed again, the total charge that must flowthrough R to reset the pixel is equal to that “lost”during the integration period

» and the signal across R is a measure of the voltage onthe photodiode after the integration time

• Weckler also reported the first picture from aphotodiode array (a 200-element linear array)

» he named it a reticon and founded the company of thesame name (now EG&G Reticon)

» and he holds the first patent on photodiode arrays

Passive Pixel Sensors(PPS)

hfS R

VVd


• To integrate this into an array, the suggestionwas to use a single load resistance at thebottom of a column of pixels

• One of the disadvantages of this readouttechnique (especially for large arrays) was thetime required to reset the diode fully through theresistor

» incomplete reset reduces the dynamic range of thesensor

• Hence, readout via a charge amplifier wassuggested

out

R


Charge Amplifier

• An alternative to the resistor readout scheme isto supply and measure the reset charge using acharge amplifier

• As proposed, for example by Noble (1968), therewould be one charge amplifier per array

• In the ideal case, the virtual earth of theamplifier would supply the current needed torecharge the diode

» once the appropriate addressing transistors are turnedon

• This current would be integrated and convertedto a voltage

» Vout = vi.Cd/Cf

columnselect

rowselect

Vout

Cf

virtual earth

Cd

vi


• This charge is stored on Cf after the column orrow transistors are turned off

» and the amplifier and the whole line must be resetbetween pixels by shorting Cf

• While this approach is simple in principle, it isalmost useless in practice

» owing to parasitic capacitances, CL, of all the datalines, since all diodes are connected to the one input

• This is bad because Cd can charge from CL

instead of Cf – charge is shared between CL & Cf

» and so Cf will not record the full charge required toreset the diode

• The effective value of Cf at the amplifier input is

» C´f = (1 + A)Cf (from Miller’s theorem)

» and only C´f/(C´f + CL) of the reset charge comes fromthe charge amplifier

» hence the value of Vout can be significantly reduced

Cf

Cd CL

A+-

C´f


• Many research groups and companies haveused PPS

» we will consider the pros and cons below

• The modern implementation reduces thecapacitance problem by

» using one charge amplifier for each column in thearray

• And use just one addressing MOSFET

Modern Implementation

row m

row m+1

Vref

reset

Cf

+

–

to reset diodes to reverse bias


• When the address transistor is switched on

» a current flows via the resistance and capacitance ofthe column bus because of Vref - Vdiode

» this total charge required for this reset is integrated bythe capacitor Cf, and output as a voltage

» so the final bus and diode voltages are returned to Vrefby the charge amplifier

» the address FET is turned off, and the voltage acrossCf is removed by the reset FET

• The column bus R & C is still important becausethey affect

» the speed at which the pixel can be read out

» and the noise associated with the readout (see later)

• Thus the use of PPS these days is limited tosmall array sizes and slow readout

» typically the “quality” is about 1/10 that of a CCDdetector of similar dimensions

» and PPS are generally out of fashion

• Two problems arise from the use of one chargeamplifier per column

» differences between amplifiers

» reset speed is limited by the maximum size of FETsthat can fit into the limited space available in the widthof a column


• A typical 0.5µm process has a metal-1 tosubstrate capacitance of 50aF/µm2

» leading to the capacitance of a 3µm x 10mm bus ofnot less than 1.5pF

» and there is extra capacitance due to the devicesattached to the bus, say 2pF

• Recall that the (30µm)2 pixel capacitance isabout 0.15pF

» so about 10% of the bus capacitance

• A typical value for Cf is 0.2pF

» which gives an effective value of C’f ≈ 20pF at theinput to the charge amplifier

• This means that only ≈ 90% of the chargerequired to reset the diode comes from theintegrating capacitor

» this represents a significant loss of sensitivity

Typical Values


Advantages of PPS

• Despite the drawbacks in the readout techniqueof PPS, they have some advantages

• The main advantage is that the fill factor ismaximised

» because there is only one transistor

• This allows the pixels to be smaller for a giventechnology

» which keeps die sizes smaller

» and devices cheaper

• It is also argued that the simplicity also enablesa higher yield to be achieved

» which would also keep costs down

» but this is less important in these days of high qualityfabrication

• In common with other photodiode-basedsensors, the quantum efficiency is high

» because there are as few layers as possibleoverlaying the device


Hitachi R&D Effort

• One of the few companies to carry out seriousR&D into CMOS image sensors in the yearsbetween ~1970 and ~1990 was Hitachi Ltd.

» seeking alternatives for colour hand-held videocameras

• In a series of papers, Hitachi researchersreported essentially complete single-chip colourcameras

» at relatively low 484 x 384 resolutions

» but the fabrication technology was 3µm NMOS

» this type of integration has only been achieved incommercial products in the last few years

• These Hitachi sensors were still the passivepixel arrangement

• Hitachi abandoned their efforts in the late 1980s

» but they hold several vital patents for active pixels andnoise reduction circuitry

» these patents are still in force today, so othercompanies are having to take these into account


Active Pixel Sensors (APS)• In the same 1968 paper, Noble shows the first

use of a MOSFET buffer amplifier in the pixel

» this has become known as an active pixel sensor(APS), which Noble also considered to be superior tothe PPS

» and an improved study and analysis was reported byChamberlain shortly afterwards

• In these early devices, variations between theindividual diodes and MOSFETs were significant

» variations in diode dark currents and MOSFETthreshold voltages

» variations in leakage, capacitance etc. in circuitry

• Overall signal-to-noise ratios were only about 1

• It was these variations, due to the immaturefabrication technology, that allowed CCDs togain the dominance that still exists

» CCDs had a smaller fixed pattern noise

» and a smaller pixel size because there were no (large)transistors in the pixel

• Relatively little APS research was carried out foranother 10 years, and it took 20 years for majorinterest to be renewed


Modern APS• With improvements in the CMOS fabrication

process brought about by the computerindustry, CMOS imagers have again becomeviable

» these improvements have reduced device-to-devicevariations to manageable levels

» while they are not yet as good as CCDs, the otheradvantages of CMOS imagers frequently make theperformance penalty worthwhile

• The basic form of APS employs the familiarphotodiode, and a readout circuit of threetransistors

Vbiasload

transistor

Vout

reset

VDD rowselect

n+

p-sub

pixel

column bus

M

L


• Here, the idea is that the photodiodecapacitance just includes

» the diode itself

» the source of the reset transistor

» and the gate of the MOSFET, M

• M acts as a voltage buffer to drive the outputindependently of the diode

• There is a single load transistor for each column

» this minimises pixel area

» minimises pixel-to-pixel variations

» and works because only one row of the array isactivated at any time

• A typical pixel layout would look like

reset

row selectcolumnVDD

VDD

substrate

n+


Reset

• Fabrication usually takes place into a p-typesubstrate

» and the n+ source/drain diffusions of the NMOStransistors are used for the photodiode

» n-type device wells are needed for PMOS transistors

» and there needs to be space both between thedevices and the well, and between the well and otherthings

• Hence NMOS transistors are most space-efficient because they do not need a separatedevice well

» which takes up valuable pixel area

» and NMOS reset transistors are currently almostuniversal

S D

G

n-wellp-sub

clearance

clearance

S D

G


• However, this has an important drawback

» an NMOS transistor with VDD on both G and D canonly get to a source voltage of VDD - VT

» before it switches off, because VGS < VT

• Therefore, the photodiode can only be reset to avoltage of (VDD - VT)

» this limits the dynamic range of the sensor

» and introduces a major source of non-uniformity

» the trend with device scaling is shown below

• Maybe it is time to re-assess the use of PMOSreset transistors

» since device scaling reduces the impact of includingthe n-well

BBB

BB

B

B

BBBB

00.5

11.5

22.5

33.5

44.5

1980

1985

1990

1995

2000

2005

2010

Year

VT falling, butVDD held at 5V


Readout• If we consider the readout circuit for an

individual pixel

» ignoring the row select transistor for the moment

• Provided that Vout > Vbias - VTL, L is in saturationand can be idealised by a current source, i

» Vbias ≈1.5V, so Vbias - VTL ≈ 0.5V

» M is always in saturation, if Vdiode -Vout > VTM andignoring any body effect

• For transistor M

• Rearranging gives

M

L

Vdiode

Vbias

Vout

MVdiode

I

VDD

0V

Vout = Vdiode − VTM + iK

where K = 12

µCoxWL

i = K VGS − VTM[ ]2 = K Vdiode − Vout − VTM[ ]2


• The maximum possible Vout = Vdiode - VTM

» or, including the reset voltage, Vout < VDD - (VTM + VTR)

» but this is only if i = 0

• But otherwise, the output is linearly proportionalto the diode voltage

• So the maximum practical output swing is

» Vbias - VTL < Vout < VDD - (VTM + VTR)

• Hence, the bias voltage should be minimised,while still keeping the load , L, turned on

• From the above, we can now see that the rowselect transistor does not add any furthervoltage drop

» even when Vout is at its maximum, VGS for the rowselect is still greater than VT so there is no further lossof signal

VDD

(Vdiode)max = VDD - VT

VDD

Vbias

(Vout)max ≈ VDD - 2VT

Vmax ≈ VDD - 2VTM

L

row select


Typical Figures• For photodiode APS, the typical fill factor is

about 20 – 35%

» taking into account the photosensitive area as afraction of the total pixel area

» pixel area = (total sensor area)/(n x m pixels)

• The real pixel size is called the “pixel pitch”

» and is the (array width) / (n columns) or (arrayheight)/(m rows)

» which are not necessarily the same

• Typically the pixel pitch ~ 15 x min. feature size

• The peak quantum efficiency (QE) is ~40% atgreen wavelengths

• Conversion gain ~ 3µV/e-

» which is quite low compared to CCDs and photogate

• Saturation signal ~ 300,000 e-

• Dynamic range ~ 6000:1 (75dB)

• The maximum commercial array size is currentlyabout 1024 x 1024

» although larger experimental devices have beenreported


Log. Photodiode APS

• An interesting variant on the basic 3-transistorAPS circuit allows for a logarithmic responsefrom the sensor

• If the dynamic range is limited by voltageswings in the circuit, and not by the full-well ofthe diode

» then logarithmic encoding of the photo-signal allowsfor a much wider dynamic range

» i.e. same voltage swing for a wider range ofillumination

• This can be achieved very simply

• Because iphoto is very small, the apparentresistance of the photodiode is large

» and the voltage at A is only slightly lower than VDD

» in fact, just low enough so that iDS = iphoto

iphoto

VDD

rowselect

A

iDS


MOSFET in Sub-threshold

• The bias conditions of the MOSFET aresomewhat unusual

• Now VGS < VT and the FET is officially off

» except that a small “sub-threshold” current can flow

» the FET is in inversion, but not the strong inversionrequired for above threshold operation

• In weak inversion, current flow is dominated bythe diffusion of minority carriers (e- here)

» where n(0) and n(L) are the electron concentrations atthe source and drain, respectively, A is the area forconduction, and L is the channel length

» Jdrift ∝ n, but Jdiff ∝ dn/dy, which can be large even forlow n

iDS = −qADndndy

= qADnn 0( ) − n L( )

L

VDD

VDD - ∆V

VDD

iDS


• The electron concentrations are

» where ψs is the surface potential, given by[(Ei)bulk–(Ei)interface]/q

• At the surface of the semiconductor, the electricfield is

• In the equation above, the area for current flow,A, equals the width of the FET x channelthickness, tchan

» tchan is defined by the point at which the electronconcentration falls to 1/e of its value at the surface

» i.e. where ψs is decreased by kT/q

• This occurs at tchan = kT/qEs

Es = −Qdepletion

εSi=

qNAWdepl

εSi

=qNA

εSi

2εSiψ s

qNA

=2qNAψs

εSi

n 0( ) = np0 expqψ skT

n L( ) = np 0 expqψ s − qVDS

kT


• By substitution, and without doing muchsimplification, we get

• Now, if VDS > 3kT/q (≈ 75mV), the last term in theabove equation ≈ 1

» and the exp(ψs) term dominates, so iDS = const. xexp(qψs/kT)

• The surface potential, ψs, is given by (VGS -constant terms)

» and in our circuit, VGS = VDS

» so we find iDS = i0 exp(qVDS/kT)

» where the i0 incorporates all the constant terms

• Finally, by rearranging, we obtain

• So as the illumination (and hence iphoto)increases linearly

» the output voltage decreases logarithmically

iDS = DnWL

ni2

NA

kT2qNAψ s

εSi

e

qψ s

kT 1 − e−

qVDS

kT

VS = Vout = VD − kTq

lniDS

i0

= VD − kT

qln

iphoto

i0


IMEC Log APS

• Logarithmic pixels have been promoted inparticular by the Inter-UniversityMicroelectronics Centre (IMEC) in Belgium

» in the introduction, we saw pictures taken by an IMECcamera in space

• IMEC is one of the leading APS laboratories andhave made innovative devices such as

» a “circular” foveated camera

» a 2048 x 2048 array

» a “time-to-crash” sensor

• Below is a typical output characteristic for oneof the IMEC logarithmic sensors

B

B

B

B

B

BBB

0.8

0.85

0.9

0.95

1

1E-5

1E-4

1E-3

1E-2

1E-1

1E+0

1E+1

1E+2

Ou

tpu

t vo

ltag

e (V

)

Light intensity (W/m2)


Advantages of Log APS

• The much-sought-after advantage of the logcompression is that the sensor measuresillumination over a range of > 5 orders ofmagnitude

» the dynamic range is ~100,000:1 (100dB)

» i.e. an order of magnitude more than ordinary APS

» remember that an office scene may have a range ofillumination of 106

• In addition, the log pixels do not need a resetline

» so the operation is simpler

» and the fill factor is higher

• Because they use no integration time, the pixelcan be read out at any time as well as in anysequence

» so they are truly randomly accessible

• So why doesn’t everyone use them?


Disadvantages of Log APS• While the dynamic range is large, the log pixels

suffer from several serious drawbacks arisingfrom the sub-threshold operation of the FET

• In the iDS expression is the term in exp(qψs/kT)

» in ψs are factors such as the threshold and flatbandvoltages, which depends on the interface conditions,and the oxide thickness, as well as the gate voltage

» therefore the output characteristics are sensitive tosuch variations at a similar level to the signal

• The kT/q term leads to a significant temperaturedependence of the output

» about 8mV/°C, according to IMEC

» this could be a problem for large arrays wheresignificant temperature gradients are possible

• But the main difficulties arise because of the lowswing of the output signal

» only about 0.15V for 5 orders change in illumination

• For example, FET threshold voltages can have avariation of ± 5 - 10%

» i.e. about 0.1V

» comparable with the recorded signal levels


• These variations appear as fixed pattern noise

» and are so severe for log pixels that some subtractionof stored “background” signals is essential

» and owing to the continuous output, a correlateddouble sampling approach (see later) does not workand a whole array’s worth of reference values must bestored somewhere

• Moreover, the small signals make the sensorssusceptible to other noise sources

» a signal-to-noise ratio of 45dB (~180:1) is typical

» an integrating photodiode pixel may get 55-60dB(1000:1)

• All of this means that a fully integrated camerasystem using the log pixels is hard to implement

• The remaining issue with the logarithmic pixelsis their speed at low light levels

» since the only way of charging/discharging thesensing node is by means of the photocurrent

» which can take a long time at low iphoto

• Say Cd = 2pF, iphoto = 10pA, and ∆V = 0.1V

» so ∆Q = Cd∆V = 2.10-12 x 0.1 = 10-13 C

» at iphoto = 10-11 C/s, it takes ~10ms per pixel to removethe charge (i.e. 100 pixels/s maximum readout rate)


Photogate APS

• Photogate Active Pixel Sensors were developedin the early 1990s by workers at the JetPropulsion Laboratory (JPL), part of NASA

• The design of photogates owes a lot to CCDtechniques

» indeed, the photogate looks just like the final stage ofa CCD register

• The structure and operation are more complexthan for the photodiodes, but they offeredseveral advantages:

» not previously patented!

» (now patented by Eric Fossum of JPL)

» allows improved noise suppression (see later)

» and a greater Q → V conversion efficiency, due to itsseparate output node

• The main disadvantage is that their quantumefficiency is reduced by the use of an overlyingpoly-Si gate

» the advantage of conversion efficiency is almostexactly offset by the reduced QE


• The schematic of the photogate pixel is asfollows

• The photogate (PG) is biased positively, therebycreating a potential well in the deep-depletedsubstrate

» thereby providing storage for the photo-generatedcharge

• A transmission gate (TX) is dc biased duringintegration and acts like a surface-channel CCD

» when the PG is pulsed to 0V, charge is transferredunder the TX gate to the floating diffusion output node

» ideally, the TX gate should overlap the PG to ensureeffective charge transfer (i.e. a double-poly process)

Operation of Photogate

VDD

PG TXRST

FD

RS

p-subn+

VDD

column


• The floating diffusion (FD) acts as the charge-voltage conversion node

» and the signal is read out using the conventionalsource-follower circuit

» a typical capacitance is 10fF, giving a conversionefficiency of 10–20 µV/e-

• This floating diffusion is reset (RST) by theneighbouring reset FET

• The added complexity of the pixel reduces theminimum dimensions to ~20 times the processfeature size

» so 10µm for a 0.5µm process

» with a fill factor that is somewhat lower than that for aphotodiode

• Because of the overlying poly-Si gate, thequantum efficiency is lower than a photodiode,especially at the blue end of the spectrum

» typically the peak value ~20%

» compared with 35-40% for photodiode

• A typical operating sequence for the photogatepixel is described below


1. Signal Integration

• TX and RST are biased lower than PG to providefor some lateral antiblooming control

» both from PG to FD

» and from FD to VDD

• This ensures that any charge spilling over froma full well is not allowed to flow into adjacentpixels

5VPG

2.5VTX

2.5VRST

FD5VVDD


• RST is pulsed to 5V, in order to reset the FD to~3.5V

• The final reset voltage is VT lower than VDD

• FD is reset immediately before the signalreadout because this allows improved noisereduction

5VPG

2.5VTX

5VRST

FD5VVDD

2. Reset


3. Charge Transfer

• Now, PG is pulsed to 0V to transfer the chargevia TX onto the FD

• Calculated full well capacities are on the orderof 106 e-

» although this, of course, depends on the gate area

» but the realisable value depends on the outputcircuitry, such as the transistor biasing

• The signal charge is added to any chargeremaining after the reset operation

0VPG

2.5VTX

2.5VRST

FD5VVDD


Single-poly Photogate

• While double-poly is a feature of many analogCMOS technologies, its use does restrict thegenerality of the design

• However, the need for overlapping gates can beremoved by adding an intermediate “bridging”diffusion

• Save for the possible introduction of someimage lag, the use of this extra diffusion haslittle affect on the performance of the pixel

VDD

PG TXRST

FD

RS

p-subn+

VDD

column


Pinned Photodiode

• While the pinned photodiode is not strictlyrelated to the photogate, it bears some similarityin operating principle

» and was originally developed with CCDs in mind

• This structure is intended to give an improvedquantum efficiency in the blue region of thespectrum

» and a lower dark current

• The device uses additional implantation steps tothe standard CMOS process to optimise theperformance of the photodetector

» and has been commercialised by Eastman-Kodak andMotorola under the name of ImageMOS™

» and patented

» it is this kind of “tweaking” of the standard CMOSprocess that Wong believes will become the norm forintegrated image sensors

• Pinned photodiodes were first proposed forCCD sensors in the early 1980s and applied to acombined CMOS/CCD structure in 1995 in aJPL/Kodak collaboration


Structure of Pinned PD

• The pinned photodiode is just like a regularphotodiode

» except for an additional p+ surface implant

• The p+ implant acts rather like a self-biased,internal photogate

• Doping levels and implant depths must becarefully controlled

» to deplete the n-region fully

» to ensure effective charge transfer from the diode tothe floating diffusion

• The name “pinned diode” arises because the p+

implant pins the potential at the surface to thatof the substrate

TX RST

RS

VDD

p-subn+

p+


• So the potential, as a function of depth, lookslike

• The operation of the pixel is similar to that of thephotogate

» the FD is reset

» TX is used to transfer the signal charge onto the FD

» the diode itself is reset through RST and TX

• The ImageMOS™ process is based on a 3.3V0.6µm CMOS technology

» the output voltage swing at the output is ~650mV, andis the limiting factor on the dynamic range

log (depth)

potential

0

edge of p+

region(< 0.1µm)

edge of nregion

(~0.5µm)

empty well

full well

surface


• Part of the purpose for using pinned diodes is toincrease the pixel responsivity at shortwavelengths

• This is mainly as a result of a reduced surfacerecombination of photo-generated e-h pairs

» arising from the doping profile a short distancebeneath the surface

» which creates a field favourable for e-h pair separation

Spectral Response

VLSI Vision photodiode

0

0.2

0.4

0.6

0.8

1

1.2

400

500

600

700

800

900

1000

1100

Wavelength (nm)

ImageMOS™ pinned photodiode

No

rmal

ised

res

po

nse


Dark Current

• Dark current in the depletion region of aconventional p-n junction is dependent on thevolume of material in which thermally generatede-h pairs can be collected

• So the width of the depletion region is important

» as determined by np0 and pn0, the minority carrierconcentrations

» which are in turn affected by the dopingconcentrations

» so the depletion region is smaller for higher doping

• And the rate and distance of the diffusion ofminority carriers

» which also decrease for higher doping

• In general, however, the same volume must alsobe maximised to achieve the efficient collectionof photo-generated charge

• Although geometrical effects, perimeters etc.also influence Jdark

Jdark =qDppn 0

Lp+

qDnnp 0

Ln


• But if we can tailor the sensor such that thedepletion region is at the correct depth forefficient optical absorption

» the depletion region does not have to be so large

» and the dark current can be reduced

• For the ImageMOS™, the dark current is betterthan for a regular photodiode

» by a factor of ≥ 2

• The profile of the p+ implant right at the surfacealso reduces the collection of dark currentgenerated at the surface states at the Si-SiO2interface

• Fill factor is reduced by the transmission gate,but this also provides some anti-bloomingfunction

• It is not yet clear how “revolutionary” the use ofpinned diodes will be for CMOS image sensors

» technology is less widespread

» more complex pixels


Summary• This has covered all of the common CMOS

compatible photosensors

• In the search for the perfect performance, othersensors have been proposed

» such as lateral BJTs, fabricated using CMOStechnology

» charge injection devices (CID)

» charge modulation device (CMD) which haveachieved success for HDTV cameras

• But the photodiode and charge-transfer basedpixels are by far the most widespread

» the “specialised” designs are frequently promoted bysingle companies

» either for proprietary reasons or for specialisedapplications

• It is likely that new designs will proliferate as therigid link to standard CMOS is severed

» either by choice for performance enhancements

» or forced by the continued scaling of the CMOSprocess


References – Part II

» E. Yang (1988), “0Microelectronic Devices”, McGraw-Hill

» S. Campbell (1996), “The Science and Engineering ofMicroelectronic Fabrication”, Oxford

» Paul Suni, “Advanced design creates single-chipimage systems”, Laser Focus World April 1997, p.73

» C. Matsumoto, “Startup develops CCD-CMOS hybrid”,Electronic Engineering Times, January 1997

» R.M. Guidash et al. (1995), “A modular high-performance 2µm CCD-BiCMOS technology forapplication specific image sensors and image sensorsystems on a chip”, SPIE vol. 2415, 256

» E.R. Fossum (1993), “Active pixel sensors: Are CCDsdinosaurs?”, SPIE vol. 1900, 2

» H-S Wong (1996), “Technology and device scalingconsiderations for CMOS imagers”, IEEE Trans.Electron. Dev. 43, 2131

» G. Weckler (1967), “Operation of p-n junctionphotodetectors in a photon flux integrating mode”,IEEE J. Solid-State Circuits SC-2, 65

» R. Dyck & G. Weckler (1968), “Integrated arrays ofsilicon photodetectors for image sensors”, IEEETrans. on Electron Devices, ED-15, 196


» P. Noble (1968), “Self-scanned image detectorarrays”, IEEE Trans. on Electron Devices, ED-15, 202

» S. Chamberlain (1969), “Photosensitivity and scanningof silicon image detector arrays”, IEEE J. Solid-StateCircuits SC-4, 333

» N. Koike et al. (1980), “MOS Area Sensor, part I”,IEEE Trans. on Electron Devices, ED-27, 1676

» S. Ohba et al. (1980), “MOS Area Sensor, part II”,IEEE Trans. on Electron Devices, ED-27, 1682

» M. Aoki et al. (1982), “2/3 inch format MOS single-chipcolor imager”, IEEE Trans. on Electron Devices, ED-29, 745

» E. Fossum (1997), “CMOS image sensors: Electroniccamera-on-a-chip”, IEEE Trans. on Electron Devices,44, 1689

» B. Dierickx et al. (1996), “Random accessible activepixel image sensors”, Proc. SPIE 2950, 1

» S. Mendis et al. (1997), “CMOS active pixel sensorsfor highly integrated imaging systems” IEEE J. Solid-State Circuits 32, 187

» E. Fossum (1993), “Active pixel sensors: Are CCDsdinosaurs?”, Proc. SPIE 1900, 2

» P. Lee et al. (1995), “An active pixel sensor fabricatedusing CMOS/CCD process technology”, 1995 IEEEWorkshop on CCDs and Advanced Image Sensors,Dana Point, CA


» B. Burkey et al. (1984), “The pinned photodiode for aninterline-transfer CCD image sensor”, InternationalElectron Devices Meeting technical digest, 28

» R. Guidash et al. (1997), “A 0.6µm CMOS pinnedphotodiode color imager technology”, InternationalElectron Devices Meeting technical digest, 927

fabrication technology pixel designece434/winter2008/imaging2.pdf · 2008-04-03 · r.i. hornsey,...

Documents