ezvid256 video controller datasheet

Rev A 11/2009

FEATURES Straightforward host interface consisting of 8 data and 6 addressable control lines.

Dedicated video memory address and data lines minimize the usage of other system buses.

Ideal for embedded microcontroller and microprocessor systems.

Screen resolutions of 256 by 200 (NTSC) and 256 by 240 (PAL).

On-board color generation.

Border surrounding video display with independent color control.

Up to 8 pages of video memory can be controlled at once.

User settable raster indicator.

Auto-incrementing X & Y registers for quick screen reads and writes.

Operates from a single clock source.

Fast host pixel write and read times.

Sync and blanking signals automatically done on-board.

All video memory read and writes automatically synchronized on-board.

Requires only a single 10nS SRAM memory for operation.

Single 3.3V Supply with 5V tolerant inputs.

Reno, NV 89521 ● TEL: (775) 852-7430 ● FAX: (775) 852-7430 ● WEB: www.multilabs.net

ezVID256 VIDEO CONTROLLER

ezV

ID2

56

VID

EO

CO

NT

RO

LL

ER

GENERAL DESCRIPTION The ezVID256 Video Controller is designed for color video graphics applications that require display on NTSC/PAL compatible monitors and displays. It provides all the circuitry needed to control the video memory and generate screen resolutions of 256 by 200 (NTSC) and 256 by 240 (PAL) with 256 colors (8-bit pixel depth) while offering a straightforward host interface making it ideal for embedded microcontroller and microprocessor designs where cost effective video generation is required.

ezVID256 PIN CONFIGURATION

76

51

26

1 ●

ezVID256

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

VA7 VA7

NC

VA8

VCC

VA8

VA9

VA9

NC

NC

NC

NC

NC

NC

NC

NC

Y0

Y1

Y2

Y3

GND

CSYNC

C1

C0

NC

VC

C

CLO

CK

CE

D5

A3

GN

D

A2

A1

A0

R / W

D7

D6

VC

C

CE

D4

D3

D2

D1

GN

D

NC

D0

NC

NC

RA

S

VA

0

VCC

VA0

VA1

VA1

VA2

VA2

VCC

VA3

VA3

VA4

VA4

GND

VD0

VD1

VD2

VD3

VWE

VA18

GND

VA18

VA17

VA17

VA16

VA16

GND

VA

15

VA

15

VD

7

VD

6

VD

5

VA

4

VA

14

NC

GN

D

VA

14

VA

13

VA

13

VC

C

VA

12

VA

12

VA

11

VA

11

VA

10

VA

10

VA

5

VA

5

VA

6

VC

C

VA

6

GN

D

Copyright © Multilabs – 2009 All rights reserved

THIS PAGE LEFT BLANK INTENTIONALLY


SECTION 1

OPERATION

About the ezVID256 Video Controller

Operational Description

Display Control Operations

Power Supply Requirement


ABOUT THE ezVID256 VIDEO CONTROLLER

The ezVID256 Video Controller is a cost effective and straightforward way to implement NTSC/PAL color video in any application. It generates all necessary video, control, and synchronization signals and also controls the storage and retrieval of display data in the external video memory. The interface between the ezVID256 and the display device requires a minimum of components for both S-Video and composite video outputs making it an effective solution for video generation. The interface between the ezVID256 and the host is done via 8 data and 6 addressable control lines. Having addressable control lines also allows the ezVID256 to share a common system data bus with other devices if required. The host creates texts and graphics by writing individual pixels to the screen. The screen pixel color data is stored in an external video memory which serves as the video frame buffer. This memory is automatically controlled by the ezVID256 and is invisible to the host. This leaves the controller/processor free to run the host application while the ezVID256 controls the aspects of video generation. Screen refreshing, sync signals, blanking signals, and video memory management are all handled automatically by the ezVID256. Besides writing pixels the host can also read any pixel on the screen and also control the X and Y position registers that determine the pixel position. During reading or writing of a pixel there is the option of having the X and Y position registers automatically increment afterwards. This allows the host to perform fast writes and reads of the entire screen. Other features of the ezVID256 include multiple video pages, video borders, and raster interrupting. Depending on your requirements the ezVID256 can control up to 8 independent video pages. Switching between them is as easy as setting the page control register. What's more is that one page can be displayed while another page is being written. This allows video page construction that is invisible to the viewer. The video display is surrounded by a border on the top, bottom, left, and right. The border has its own color register which allows customization of the border color by the host. The display line can be known by the host via the raster pin (RAS). By loading a line number into the raster compare register the ezVID256 will signal the host when the line has started to be drawn and when it has been completed. This can be used in many ways including moving characters around the screen when the screen draw has been completed to avoid flickering.

OPERATIONAL DESCRIPTION

Figure 1 shows a block diagram of the ezVID256 Video Controller.


Figure 1

When first powered up all registers are cleared to zero. During continuous operation the Horizontal Dot Counter and Vertical Line Counter keep track of which pixel to load and display on the screen. The addresses generated by these two counters are sent through the Output Buffer to the external video memory. The pixel color data then appears on the VD data bus which is latched into the Pixel Latch register. If the pixel is outside of the video area then the color data is ignored and the color stored in the Border Register is displayed instead. The video area for NTSC is 0 to 255 horizontal and 0 to 199 vertical. For PAL it is 0 to 255 horizontal and 0 to 239 vertical. The border covers the rest of the screen outside of these areas. The Horizontal Dot Counter and Vertical Line Counter registers are also responsible for generation of the horizontal and vertical sync and blanking signals to keep all of the frames synchronized and the Pixel Latch cleared during certain times. The sync signals are combined together to form a composite sync signal. All of this is clocked via the Clock Circuit. The data that appears on the Y3, Y2, Y1, Y0, C1, and C0 pins represent the pixel color. These signals are combined together via simple resistive ladder digital-to-analog converters to generate the analog voltage signal needed for the display device. The Csync, Y3, Y2, Y1, and Y0 pins are combined together to form the luminance (Y) signal with composite sync. The C1 and C0 pins are combined together to form the chrominance (C) signal. These two signals can be used to drive an S-Video input. The Y and C signals can also be mixed together to form a composite (CVBS) signal as well. Refer to the reference design later in this document for more information on these circuits. The host interface is via the data and addressable control lines on the left-hand side of the block diagram. There are two chip enable (CE) pins, one active low and one active high. The active low pin is designated with a line over it. These pins must be at the correct logic level before the ezVID256 can be controlled. If not properly selected no data can be written to or read from the ezVID256 and the data lines will remain in a high-impedance input state. The enable lines can be used however needed. If the ezVID256 is to be constantly selected then they can be tied off to the proper logic level. If part of a system that uses a common data bus they can be used to ensure that the ezVID256 is only selected when needed. If only one enable line is needed then the other can be tied off to the proper logic level while the other is used to control when the ezVID256 is enabled.

CE CE A3 A2 A1 A0 R / W

Horizontal Dot Counter

Vertical Line Counter

X Position Register

Ou

tpu

t Bu

ffers

VA18 - 0

Csync

Y2

Y1

Y3

C0

Re

ad

Co

lor

Re

gis

ter

Write

Co

lor

Re

gis

ter

VD7 - 0

H

ost I/O

Inte

rface

Circ

uit

D7 - 0

Control Signals

VWE

Clock Circuit

Clo

ck

Y0

C1

Master Clock

Subcarrier

Dot Clock

Y Position Register

Page Control Register

Co

mp

are

Circ

uit

RA

S

Border Color Register

Pixel Latch

Color Generator

Color Selector


The 4 address lines (A3 – A0) are used to select what operation to perform. The R/W (Read/Write) pin controls the bi-directional data flow of the ezVID256. With this pin logic low the data pins are in high-impedance input mode. If the pin is logic high then the data pins will be driven as outputs when a read operation is selected. If any operation other than a pixel read is selected than the data pins will remain in a high-impedance state even with the R/W pin logic high. The host interface is asynchronous to the internal operation of the ezVID256. Data can be passed to and from the ezVID256 at any time. The X and Y Position Registers are where the host stores the pixel position to be written to or read from. These registers can be automatically increment each time a pixel read or write command is completed such that the X position register is incremented and if the end of the line is reached the X position register is reset back to 0 and the Y position register is incremented. Should the Y position register be on the last line when it is incremented it will also automatically reset to 0. This is called progressive incrementing. This allows for fast whole screen reads and writes. When a pixel read or write is executed the address in the X Position and Y Position Registers is passed through the Output Buffers to the external video memory. If the instruction is a write the VWE (Video Write Enable) pin will go low to place the external video memory in write mode. The data in the Write Color Register will appear on the VD pins to be latched into the external video memory. For a read instruction the data from the external video memory is latched into the Read Color Register. Up to 8 pages of video memory can be controlled. The amount of pages available is dependant on the amount of video memory used. The minimum amount of video memory required is 64K connected to address pins VA0 through VA15. This only allows for a single page. A 128K memory connected to VA0 through VA16 allows for 2 pages, a 256K memory connected to VA0 through VA17 for 4 pages, and a 512K memory connected to VA0 through VA18 for 8 pages. If more than one page is available the ezVID256 gives you the ability to control the pages independently. Any of the pages can be displayed while any other page can be written to or read from. This means that a screen can be constructed on one page while another is being displayed. The construction of the page is invisible to the viewer. The host has the option of monitoring the RAS pin to determine which line is currently being drawn. The line to monitor is loaded into the Compare Circuit and that line is compared with the one being drawn by the Vertical Line Counter. When they are equal the RAS pin will go logic high to indicate the line draw has begun. When the line draw is complete the pin will go logic low. The ezVID256 is clocked from a single clock source. There is no internal oscillator drive circuitry so a LVTTL level clock source must be provided. The main clock is 28.63636MHz for NTSC and 35.46895MHz for PAL. This is fed into the Clock pin.

DISPLAY CONTROL OPERATIONS The ezVID256 can perform 9 different operations. The operation to be performed is selected by the 4 address lines (A3 – A0) as shown in the following table.


A3 A2 A1 A0 OPERATION

0 0 0 0 Load X position register

0 0 0 1 Reserved for future use

0 0 1 0 Load Y position register


0 1 0 0 Write pixel without auto-incrementing X & Y position registers

0 1 0 1 Read pixel without auto-incrementing X & Y position registers

0 1 1 0 Write pixel and auto-increment X & Y position registers

0 1 1 1 Read pixel and auto-increment X & Y position registers

1 0 0 0 Load border color register

1 0 0 1 Load page control register

1 0 1 0 Load raster compare register






For each operation it is assumed the ezVID256 is properly selected. Refer to the timing diagrams for proper data and address timing when writing to and reading data from the ezVID256. Load X Position Register Operation: With the ezVID256 addressed for this operation the data on the data bus (D7 – D0) will be written to the X position register when the R/W pin is brought logic low and then brought back to logic high. The allowed values of the X position register are 0 to 255 for a total of 256 horizontal pixels.

Figure 2

Load Y Position Register Operation: With the ezVID256 addressed for this operation the data on the data bus (D7 – D0) will be written to the Y position register when the R/W pin is brought logic low and then brought back to logic high. For NTSC the allowed values of the Y position register are 0 to 199 for a total of 200 vertical lines. For PAL it is 0 to 239 for a total of 240 vertical lines.

Figure 3

D7

D6

D5

D4

D3

D2

D1

D0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y Position Register

D7

D6

D5

D4

D3

D2

D1

D0

X7

X6

X5

X4

X3

X2

X1

X0

X Position Register


Write Pixel Without Auto-Incrementing X & Y Position Registers Operation: With the ezVID256 addressed for this operation the data (pixel color) on the data bus (D7 – D0) will be written to the video memory. The position of the pixel is taken from the X and Y position registers. To execute the write the R/W pin is brought logic low and then brought back to logic high.

Figure 4

Read Pixel Without Auto-Incrementing X & Y Position Registers Operation: With the ezVID256 addressed for this operation the data bus (D7 – D0) will output data (pixel color) from the video memory. The position of the pixel is taken from the X and Y position registers. This operation is automatically executed when properly addressed and the R/W line is logic high.

Figure 5

Write Pixel and Auto-Increment X & Y Position Registers Operation: With the ezVID256 addressed for this operation the data (pixel color) on the data bus (D7 – D0) will be written to the video memory. The position of the pixel is taken from the X and Y position registers. To execute the write the R/W pin is brought logic low and then brought back to logic high. After this the position registers are automatically incremented as previously explained.

Figure 6

Read Pixel and Auto-Increment X & Y Position Registers Operation: With the ezVID256 addressed for this operation the data bus (D7 – D0) will output data (pixel color) from the video memory. The position of the pixel is taken from the X and Y position registers. This operation is automatically executed when properly addressed and the R/W line is logic high. To signal the end of the operation the address must be changed or the ezVID256 de-selected. After this the position registers are automatically incremented as previously explained.

D7

D6

D5

D4

D3

D2

D1

D0

C7

C6

C5

C4

C3

C2

C1

C0

Read Color Register

D7

D6

D5

D4

D3

D2

D1

D0

C7

C6

C5

C4

C3

C2

C1

C0

Write Color Register

D7

D6

D5

D4

D3

D2

D1

D0

C7

C6

C5

C4

C3

C2

C1

C0

Write Color Register


Figure 7

Load Border Color Register Operation: With the ezVID256 addressed for this operation the data (border color) on the data bus (D7 – D0) will be written to the border color register when the R/W pin is brought logic low and then brought back to logic high.

Figure 8

Load Page Control Register Operation: With the ezVID256 addressed for this operation the data on the data bus (D5 – D0) will be written to the 6-bit page control register when the R/W pin is brought logic low and then brought back to logic high. The page control register is broken into two 3-bit sections. The lower three bits (V2 – V0) controls which page is being viewed. The upper three bits (H2 – H0) controls which page the host is writing to or reading from. Both have a value of 0 to 7 for a total of 8 pages. They can either be the same page or different pages.

Figure 9

Load Raster Compare Register Operation: With the ezVID256 addressed for this operation the data on the data bus (D7 – D0) will be written to the raster compare register when the R/W pin is brought logic low and then brought back to logic high. The number loaded will cause the ezVID-ND to signal when that particular line is being drawn and when it has been completed.

D5

D4

D3

D2

D1

D0

H2

H1

H0

V2

V1

V0

Page Control Register

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

Border Color Register

D7

D6

D5

D4

D3

D2

D1

D0

C7

C6

C5

C4

C3

C2

C1

C0

Read Color Register


Figure 10

POWER SUPPLY REQUIREMENTS All VCC power inputs should be provided with individual bypass capacitors placed as closed to the power pins as possible. These capacitors should have a low internal inductance, low equivalent series resistance, and good frequency characteristics. All of the GND pins should be connected to a low-impedance ground plane for best performance. The ezVID256 can create high-speed switching signal noise. A good low-impedance ground source is necessary to minimize noise and ground bounce. All ground connections in the final design should be connected to the same low-impedance ground plane for best operation.

D7

D6

D5

D4

D3

D2

D1

D0

R7

R6

R5

R4

R3

R2

R1

R0

Raster Compare Register


SECTION 2

CONNECTIONS AND TIMING

Pin Descriptions

Timing Diagrams


NC

76

51 26

1 ●

ezVID256

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

VA7

NC

VA8

VCC

VA8

VA9

VA9

NC

NC

NC

NC

NC

NC

NC

Y0

Y1

Y2

Y3

GND

CSYNC

C1

C0

NC

VC

C

CL

OC

K

CE

D5

A3

GN

D

A2

A1

A0

R / W

D7

D6

VC

C

CE

D4

D3

D2

D1

GN

D

NC

D0

NC

NC

RA

S

VA

0

VCC

VA0

VA1

VA1

VA2

VA2

VCC

VA3

VA3

VA4

VA4

GND

VD0

VD1

VD2

VD3

VWE

VA18

GND

VA18

VA17

VA17

VA16

VA16

GND

VA

15

VA

15

VD

7

VD

6

VD

5

VD

4

VA

14

NC

GN

D

VA

14

VA

13

VA

13

VC

C

VA

12

VA

12

VA

11

VA

11

VA

10

VA

10

VA

5

VA

5

VA

6

VC

C

VA

6

GN

D

VA7

PIN DESCRIPTIONS

Figure 11 The ezVID256 is provided in a 100-pin TQFP package. The following is a table of each pin’s description:

PIN NAME PIN NUMBER FUNCTION

VA0 50 52

Address A0 of the external video memory. These two pins must be tied together for proper operation.

VA1 53 54


VA2 55 56


VA3 58 59


VA4 60 61


VA5 95 96


VA6 97 Address A6 of the external video memory. These two pins must be



99 tied together for proper operation.

VA7 1 2


VA8 4 6


VA9 7 8


VA10 93 94


VA11 91 92


VA12 89 90


VA13 86 87


VA14 82 85


VA15 76 77


VA16 73 74

Address A16 of the external video memory. This address is only used with memory sizes of 128K, 256K, and 512K for multiple video pages. If unused they can remain unconnected. If used these two pins must be tied together for proper operation.

VA17 71 72

Address A17 of the external video memory. This address is only used with memory sizes of 256K and 512K for multiple video pages. If unused they can remain unconnected. If used these two pins must be tied together for proper operation.

VA18 68 70

Address A18 of the external video memory. This address is only used with a memory size of 512K for multiple video pages. If unused they can remain unconnected. If used these two pins must be tied together for proper operation.

VD0 63 External video memory data bit 0.








VWE 67 Write enable line of the external video memory.

NC 3 9 10 11 12 13 14 15 16 25 45 47 48

No connection.



83

VCC 5 26 38 51 57 88 98

+3.3V Power supply.

GND 21 31 44 62 69 75 84 100

Power supply common return ground.

CLOCK 27 28.63636MHz (NTSC) or 35.46895MHz (PAL) LVTTL level clock input. Minimum ±100ppm and 45%/55% duty cycle or better.

CE 28 Chip enable active high input.

CE 29 Chip enable active low input.

A0 34 Address line 0.




R/W 35 Read/write input. Low keeps the data line in high-impedance state for writes to the ezVID256. High turns on the output drivers while enabled and addressed for a pixel read.

D0 46 Data bus bit 0.








CSYNC 22 Composite sync output.

Y0 17 Bit 0 of luminance level.




C0 24 Color burst signal output.

C1 23 Color signal output.

RAS 49 Raster compare output. Goes logic high at the beginning of the line draw and goes logic low at the completion of the line draw.


CE

CE

R/W

A3 – A0

1

4

3

ADDRESS VALID

D7 – D0 DATA VALID

2

TIMING DIAGRAMS X Position, Y Position, Border Color, Page Control, and Raster Compare Register Writes:

Figure 12

NUMBER ITEM SYMBOL MIN TYP MAX UNIT

1 Address and data setup time TADS 0 nS

2 Data stable before R/W rising edge TDSRW 13 nS

3 R/W hold time TRWH 13 nS

4 Address and data hold time TADH 8 nS

NOTES 1. To avoid writing to the incorrect register the address should be made stable before or at the

same time as the R/W line is brought low.


CE

CE

R/W

A3 – A0

1

4

3

ADDRESS VALID

D7 – D0 DATA VALID

2

Pixel Write:

Figure 13


1 Address and data setup time TADS 0 nS

2 Data stable before R/W rising edge TDSRW 9 nS

3 R/W hold time TRWH 175 nS

4 Address and data hold time TADH 8 nS

NOTES 1. To avoid writing to the incorrect register the address should be made stable before or at the

same time as the R/W line is brought low. 2. After the rising edge of R/W a wait time of a minimum of 362nS must be observed before

performing another operation.


CE

CE

R/W

A3 – A0

1

ADDRESS VALID

D7 – D0 DATA VALID HI-Z HI-Z INVALID DATA

2 3

4

Pixel Read:

Figure 14


1 Time till output is active after valid address TOVA 11 nS

2 Time till data is valid after valid address TVDVA 175 nS

3 Address hold time after valid data (see notes) TAHVD -- -- -- --

4 Time till high-z after invalid address THZIA 11 nS

NOTE 1. Hold time is dependant on the amount of time the host needs to sample the data after it is valid.

Once sampled the address may be changed or the ezVGA256 deselected. 2. After completion of the read operation a wait time of a minimum of 188nS must be observed

before performing another operation.


RAS

1

VALID LINE

2

Raster Compare Output:

Figure 15


1 Time from valid line begin to logic high TVLBH 12 nS

2 Time from valid line end to logic low TVLEL 12 nS


SECTION 3

APPLICATION

Sample Application

Video Quality

Electrical Characteristics


SAMPLE APPLICATION Figure 16 shows the schematic for the ezVID256 demo board. The ezVID256 (U1) is the center of this design. Starting with its power supply all VCC power inputs should be provided with individual bypass capacitors placed a closed to the pins as possible. These capacitors should have a low internal inductance and good frequency characteristics. All of the GND pins should be connected to a low-impedance ground plane for best performance. The ezVID256, along with the video memory, creates a lot of high-speed switching signals. A good low-impedance ground source is necessary to minimize noise and ground bounce. All ground connections in the design should be connected to the same low-impedance ground plane for best operation. As is evident from the schematic the majority of the pins of the ezVID256 are dedicated to the external video memory. Here the video memory is designated U2. The ezVID256 has been optimized for the pin layout of the Cypress CY7C1049DV33-10ZSXI 10nS 512K x 8 Asynchronous Fast SRAM which gives the maximum of 8 video pages. However, depending on your needs, any memory from 64K to 512K can be used. There are two points to be made about the memory. The first is the access time speed. A minimum of 10nS is needed to meet the timing requirements of the ezVID256. Secondly, the ezVID256 pin-outs are positioned to interface to this memory easily as is shown with the PCB layout figures. However, this is a center power design that is common in the industry and is used by other manufacturers. Any memory pin layout will work but be sure to observe the length of the traces. All traces connecting the ezVID256 with the video memory should be as short as possible with minimal impedance and a minimum of vias in each trace. The video memory should be as close to the ezVID256 as possible and provided with its own bypass capacitors as shown in the schematic. The schematic shows that the ezVID256 has two sets of memory address line outputs. These must be tied together for proper operation. The memory is wired so that it is constantly selected. Only the Write Enable line is used by the ezVID256, all other lines are grounded for constant selection. Power traces should be wide enough or have enough cross-section to handle several hundred milliamps of current. Just like the ground plane, any power traces or power plane should be as low in impedance as possible, the wider the traces the better. The ezVID256 is clocked from either a 28.63636MHZ for NTSC or 35.46895MHz for PAL clock source, designated as Y1. The ezVID256 does not have any internal oscillation drive circuitry so a LVTTL level clock oscillator must be provided. This clock oscillator should be crystal based and it is recommended that a minimum of ±100ppm stability should be specified with a duty cycle of 45%/55% or better. The clock does not require an enable line as shown in the schematic since operation is continuous. However, if one is provided it should be tied off to the proper logic level. The clock source should be provided with a dedicated bypass capacitor as well. The ezVID256 has two sets of outputs for the video signal. The first set creates the luminance, or Y, signal. The Y signal also contains the composite sync signal. These pins (Csync and Y0 – Y3) need to be changed to an analog signal before being sent to the display. The signal required is 1VP-P into a 75 ohm load with a 0 to 0.7V signal representing the luminance with 0V being black and 0.7V being white. The reference design shows a simple cost-effective resistive ladder digital-to-analog converter that works very well for this application. Note that the resistors of each ladder are all 1% parts. This will keep the variation down to a minimum. The signal gets passed through an emitter-follower amplifier and is set to give a 0 to 1 volt output when loaded by a 75 ohm load impedance. The second set of signals create the chrominance, or C, signal. These pins (C0 – C1) need to be changed to an analog signal before being sent to the display. The reference design shows a simple cost-effective resistive based digital-to-analog converter that works very well for this application. Note that the resistors are all 1% parts. This will keep the variation down to a minimum. The signal gets passed through an emitter-follower amplifier and is set for a 75 ohm load impedance. Both the Y and C signals can be connected directly to an S-Video connector, shown later, and they can be combined together to form a composite video signal known as CVBS (Color, Video, Blank, and Sync). The ezVID256 demo board is provided with both sets of outputs so both can be evaluated. The Y and C


signals are sent through a mixer which inverts the signal. The signal is then inverted back to its original form and then amplified for a 75 ohm load impedance. The reference design shows a simple cost-effective way of doing this that works very well for this application. However, other methods of combining the signals can be done to meet your own needs. Refer to the figures later for proper connection to video connectors.


Figure 16


Connector J2 on the schematic shows three pins that are used for connecting to the display device. Depending on what type of input connectors are on the display device there are two choices. The first is to use the Y (Luminance) and C (Chrominance) signals if S-Video is required. Figure 17 below, and the accompanying table, shows how these pins are connected to a male 4-pin mini-din connector. Both of the grounds (pins 1 and 2) may be tied together.

Figure 17

PIN TYPE NOTE

1 GND Common for Y signal.

2 GND Common for C signal.

3 Y Luminance signal.

4 C Chrominance signal.

The second option is to use the CVBS signal if composite video is required. Figure 18 below, and the accompanying table, shows how this pin is connected to a male RCA style connector.

Figure 18

PIN TYPE NOTE

1 CVBS Composite signal.

2 GND Common ground.

The following three diagrams show the layout for the demo board PCB. These can be used as a reference to aid in your own circuit design.


Top Layer With Overlay:

Figure 19


Top Layer Without Overlay:

Figure 20


Bottom Layer:

Figure 21


VIDEO QUALITY

There are many factors that affect the quality of the video displayed. One factor is the quality of the display device itself and it's settings such as saturation, brightness, tint, etc. The ezVID256 was designed to give the best possible video quality while maintaining cost effectiveness. However, there are some known issues with both the NTSC and PAL video signals themselves that can reduce the video quality. The first is known as 'dot crawl'. Dot crawl is a visual defect of the video signal when transmitting through composite video (CVBS). It results from crosstalk between the luminance (Y) and chrominance (C) signals. Dot crawl gets its name simply from what the effect looks like on the video screen. It will appear that the pixels move from one position to the other making a 'crawling' affect either horizontally, vertically, or both. This is most visible on static images such as still pictures. There are a few ways to minimize or eliminate dot crawl. One method of minimizing dot crawl is to use a high quality comb filter. This will be incorporated into most quality display devices. One method of eliminating dot crawl is to use S-Video instead of composite. Dot crawl does not exist when using S-Video since the luminance (Y) and chrominance (C) signals are separate. Another known problem is called 'color bleeding' or 'chromashifting'. This is most noticeable when strong intense colors seem to 'bleed' into their neighboring colors. The best method to try and eliminate this is by adjusting the user brightness, contrast, and color controls down a bit. Again, this artifact is not as common while using S-Video but it can happen. In the end S-Video provides a better quality signal over composite video which has known artifact issues. S-Video should be used whenever possible for the best video quality. When using composite video be aware that the quality of the filters used in your display device will make a major difference in the quality of the video picture you are viewing.


ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings:

SYMBOL DESCRIPTION VALUE UNITS

VCC Supply voltage relative to GND –0.5 to 4.0 V

VIN Input voltage relative to GND –0.5 to 5.5 V

VTS Voltage applied to 3-state output –0.5 to 5.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TJ Junction temperature +150 °C

Recommended Operation Conditions:

SYMBOL PARAMETER MIN MAX UNITS

VCC Supply voltage for logic, input, and output buffers 3.0 3.6 V

VIL Low-level input voltage 0 0.8 V

VIH High-level input voltage 2.0 5.5 V

VO Output voltage 0 VCC V

DC Characteristic Over Recommended Operating Conditions:

SYMBOL PARAMETER MIN MAX UNITS

VOH Output high voltage (see Figure 19 for output voltage versus current) 2.4 VCC V

VOL Output low voltage 0 0.4 V

IIL Input leakage current - ±10 µA

IIH I/O High-z leakage current (VIN= GND or VCC) - ±10 µA

IIH I/O High-z leakage current (GND < VIN < VCC) - ±50 µA

CIN I/O Capacitance - 10 pF

ICC Operating supply current Typ 70 mA

NOTE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions are not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.


Voltage Out Vs. Current

0

0.005

0.01

0.015

0.02

0.025

0.03

0.035

2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3

Voltage

Cu

rren

t

Figure 22


APPENDICES


APPENDIX A COLORS This is a color swatch of all the available colors. These colors where captured using the circuit shown in Figure 16 from the demo board. Actual colors may vary and will depend on the display devices settings such as brightness, tint, contrast, and other color adjustment controls as well as the digital to analog circuit used. Color variance is also subject to component tolerances of the digital to analog conversion circuitry.

Figure 23

Colors 0 - 15

Colors 16 - 31

Colors 32 - 47

Colors 48 - 63

Colors 64 - 79

Colors 80 - 95

Colors 96 - 111

Colors 112 - 127

Colors 128 - 143

Colors 144 - 159

Colors 160 - 175

Colors 176 - 191

Colors 192 - 207

Colors 208 - 223

Colors 224 - 239

Colors 240 - 255


LIMITED WARRANTY Multilabs warrants to the original consumer purchaser of this product that, for a period of 90 days from the date of purchase, this product will be free from defects in material and workmanship and will perform in substantial conformity to the description of the product in this Owner's Manual. This warranty shall not apply to defects or errors caused by misuse or neglect. If the product is found to be defective in material or workmanship or if the product does not perform as warranted above during the warranty period, Multilabs will repair it, replace it, or refund the purchase price. The repair, replacement, or refund that is provided for above shall be the full extent of Multilabs's liability with respect to this product. For repair or replacement during the warranty period, contact Multilabs customer service by email at [email protected] to receive a return authorization number and return instructions. LIMITATIONS THE ABOVE WARRANTY IS IN LIEU OF AND MULTILABS DISCLAIMS ALL OTHER WARRANTIES, WHETHER ORAL OR WRITTEN, EXPRESS OR IMPLIED, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. ANY IMPLIED WARRANTY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, WHICH MAY NOT BE DISCLAIMED OR SUPPLANTED AS PROVIDED ABOVE SHALL BE LIMITED TO THE 90 DAYS OF THE EXPRESS WARRANTY ABOVE. NO OTHER REPRESENTATION OR CLAIM OF ANY NATURE BY ANY PERSON SHALL BE BINDING UPON MULTILABS OR MODIFY THE TERMS OF THE ABOVE WARRANTY AND DISCLAIMER. IN NO EVENT SHALL MULTILABS BE LIABLE FOR SPECIAL, INCIDENTAL, CONSEQUENTIAL OR OTHER DAMAGES RESULTING FROM THE POSSESSION OR USE OF THIS PRODUCT, INCLUDING WITHOUT LIMITATION DAMAGE TO PROPERTY AND, TO THE EXTENT PERMITTED BY LAW, PERSONAL INJURY, EVEN IF MULTILABS KNEW OR SHOULD HAVE KNOWN OF THE POSSIBILITY OF SUCH DAMAGES. Some states do not allow limitations on how long an implied warranty lasts and/or the exclusion or limitation of damages, in which case the above limitations and/or exclusions may not apply to you. You may also have other legal rights, which may vary from state to state.

ezvid256 video controller datasheet

Documents