Multimedia ExtensionsShort vector extensions in ILP processorsAltiVec, 3DNow!, SSE, etc.Accelerate loops in multimedia & DSP codesNew designs have floating point support

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Multimedia ExtensionsVector resources do not overwhelm the scalar resourcesScalar: 2 FP ops / cycleVector: 4 FP ops / cycleFull vectorization may underutilize scalar resources ILP techniques do not target vector resourcesNeed bothCourtesy of International Business Machines Corporation. Unauthorized use not permitted.

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Modulo Schedulingfor (i=0; i

Traditional Vectorizationfor (i=0; i

Vectorization without Distributionfor (i=0; i

Selective Vectorizationfor (i=0; i

ComplicationsComplex scheduling requirementsParticularly in statically scheduled machinesMemory alignmentExample assumes no communication costIn reality, explicit operations requiredOften through memoryReserve critical resourcesPotential long latencyPerformance improvement still possible

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Tomcatv main loop (50%)

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Tomcatv (SpecFP 95)1.7x Speedup overModulo Scheduling

Issue Width6Memory Units2ALUs4FPUs2Vector Units1Vector Length2*

TechniqueALUMEMFPUVECModulo Scheduling622460

Full Vectorization713046

Selective Vectorization7271927

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Tomcatv (SpecFP 95)

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Selective VectorizationBalance computation among resourcesMinimize II when loop is modulo scheduledCarefully manage communicationIncorporate alignment informationSoftware pipelining hides latencyAdapt a 2-cluster partitioning heuristic[Fidduccia & Matheyses 82][Kernighan & Lin 70]

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Selective Vectorizationscalarvectorcost

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Cost FunctionProjected II due to resources (ResMII)Bin-packing approach [Rau MICRO 94]With some modifications

Can ignore operation latencySoftware pipelining hides latencyVectorizable ops not on dependence cycles

for (i=0; i

EvaluationSUIF front-endDependence analysisDataflow optimization

Trimaran back-endModulo schedulerRegister allocatorVLIW SimulatorAdded vector opsSimulation BinaryC or Fortran

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EvaluationOperands communicated through memorySoftware responsible for realignment

Issue Width6Memory Units2ALUs4FPUs2Vector Units1Vector Length2*

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EvaluationSpecFP 92, 95, 2000Easier to extract dependence informationDetectable data parallelism64-bit data means vector length of 2Considered amenable to vectorization & SWPApply selective vectorization to DO loopsNo control flow, no function calls Fully simulate with training sets

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Traditional Vectorization

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Vectorization without Distribution

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Vectorization + Free Communication

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Vectorization without Distribution

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Selective Vectorization

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Selective Vectorizationtomcatvsu2corswimmgrid

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Communication SupportTransfer through memoryRegister to register copyUses fewer issue slotsFrees memory resourcesShared register fileVector elements addressable in scalar opsRequires no extra issue slots

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Through Memorytomcatvsu2corswimmgrid

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Reg to Reg Transfer Supporttomcatvsu2corswimmgrid

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Shared Register Filetomcatvsu2corswimmgrid

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Related WorkTraditional vectorizationAllen & Kennedy, WolfeSoftware PipeliningRaus iterative modulo schedulingClustered VLIW[Aleta MICRO34], [Codina PACT01], [Nystrom MICRO31], [Sanchez MICRO33], [Zalamea MICRO34]Partitioning among clusters similarOurs is also an instruction selection problemNo dedicated communication resources

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ConclusionTargeting all FUs improves performanceSelective vectorizationVectorization better in the backendCost analysis more accurateSoftware pipeline vectorized loopsGood idea anywayFacilitates selective vectorizationHides communication and alignment latency

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ILP techniques are instruction scheduling techniques vectorization is a type of instruction selection thats why we need both

Mention what the notation in the code meansmention loop distributioncommunication between vector and scalar loopsThis is our contributionExample was very simple, but in reality there are complicationsPlanning to make publicly availablePACTTraditional never beats modulo scheduling for this architectureFree communication is unrealisticMention theoretical maximum for this architectureSay what percentages meanConsider two other design pointsMention theoretical maximum for this architectureSay what percentages meanMention theoretical maximum for this architectureSay what percentages meanMention theoretical maximum for this architectureSay what percentages mean