Experimental results on drain and source on insulatorMOSFETs fabricated by local SIMOX technology

Ping He a,*, Bo Jiang a, Xi Lin a, Litian Liu a, Lilin Tian a, Zhijian Li a,Yemin Dong b, Meng Chen b, Xi Wang b

a Institute of Microelectronics, Tsinghua University, Beijing 100084, Chinab Ion Beam Laboratory, Shanghai Institute of Metallurgy, Chinese Academy of Sciences, Beijing 200050, China

Received 19 September 2002; received in revised form 30 October 2002; accepted 7 November 2002

Abstract

To overcome the floating-body effect and self-heating effect of SOI devices, the drain and source on insulator (DSOI)

structure [IEEE Int. Solid-State Integr. Circ. Technol. Conf. Proc., 1998, p. 575] is fabricated and tested. The recently

developed low dose and low energy local SIMOX technology combined with the conventional CMOS technology is

used to fabricate this kind of devices. Using this method, DSOI, SOI and bulk MOSFETs are successfully integrated on

a single chip. Test results show that the drain induced barrier lowering effect is greatly suppressed and the drain-

to-source breakdown voltage is greatly increased for DSOI devices due to the elimination of the floating-body effect.

And the self-heating effect is also reduced and thus the reliability increased. At the same time, the advantage of SOI

devices in speed is maintained. The technology makes it possible to integrate low voltage, low power, low speed SOI

devices and high voltage, high power, high speed DSOI devices on one chip and it offers option for developing system-

on-chip technology.

� 2003 Elsevier Science Ltd. All rights reserved.

Keywords: SIMOX; MOS devices; Silicon on insulator technology

1. Introduction

The self-heating effect and floating-body effect are the

most important drawbacks of the SOI devices. As the

feature length of device shrinks, the power-density of

the IC increases. However, the low thermal conductivity

of the buried-oxide together with the Si/SiO2 interface

thermal resistance [2] resists heat to transfer to the en-

vironment and thus the working temperature of SOI

devices is greatly increased compared to conventional

bulk devices. This limits the performance and reliability

of the SOI device. Floating-body effect is another im-

portant drawback, which results in severe drain induced

barrier lowering (DIBL) effect and low BVDSS. These

drawbacks restrict the use of SOI device only to low

supply voltage and low power applications. However the

need to integrate low voltage, low power and high

voltage, high power devices on single chip is increasing

[3] especially in the digital and RF mixed systems.

To overcome these drawbacks, the drain and source

on insulator (DSOI) structure [1], only with buried-oxide

under source and drain has been proposed as shown in

Fig. 1(c). Since there is no oxides under the channel, the

floating-body effect and self-heating effect are overcome.

As SIMOX technology develops, low dose and low en-

ergy implantation has been widely used [4]. This makes

it possible to realize DSOI structure by local SIMOX [5]

technology. By this technology experimental DSOI de-

vices have firstly been successfully fabricated and SOI,

BULK and DSOI devices are integrated on a single chip.

It makes possible to test and compare the characteristics

*Corresponding author. Tel.: +86-10-62784684; fax: +86-10-

62771130.

E-mail address: heping98@mails.tsinghua.edu.cn (P. He).

0038-1101/03/$ - see front matter � 2003 Elsevier Science Ltd. All rights reserved.

doi:10.1016/S0038-1101(02)00466-5

Solid-State Electronics 47 (2003) 1061–1067

www.elsevier.com/locate/sse

and performance of these three kinds of devices on a

same die. Only one additional mask is needed to form

the local SIMOX, other fabrication processes are fully

compatible with conventional CMOS technology. The

DIBL effect, output characteristics, drain-to-source

breakdown voltage (BVDSS), working device tempera-

ture and gate delay of ring oscillator of three kinds of

devices are compared and the results are analyzed.

2. Fabrication and test results

The procedure of fabrication is shown in Fig. 1(a)–(c).

First, thick thermal SiO2 about 500 nm is grown on the

wafer as the mask for selective implantation. Then the

windows for implantation are formed and implantation

of oxygen is done. The temperature of the substrate was

set to 600 �C during the implantation. The energy for

implantation ranges from 70 to 140 keV and the dose of

oxygen from 2:5� 1017 to 9:0� 1017 cm�2 for different

wafers (4 in. in diameter). And the wafers were annealed

at 1300 �C for 6 h in Ar/0.5% O2 gas, the thin oxide

formed during this anneal was removed. The routine

material inspections show that the product wafers are

flat and crystal perfect. After that, conventional 0.5 lmCMOS technology is used to manufacture the devices. A

series of structures with varying buried-oxide thickness

and silicon thickness have been made out. The devices

are nMOSFETs with gate oxide thickness 20 nm, junc-

tion depth about 300 nm and W =L from 30/0.5 to 30/30.

For comparison, bulk, conventional SOI and DSOI

devices are made on a same die.

3. Test results

3.1. SEM

The SEM picture of a DSOI device with Si film

thickness of 120 nm and buried-oxide thickness of 55 nm

is shown in Fig. 2. From it, good formation of buried-

oxide under source and drain can be clearly seen. No

lateral expansion of the buried-oxide can be seen. In

fact, the end edge of the buried-oxide is a little apart

from the gate edge. Since at the edge the implanted

oxygen concentration is less than that at the central part

and during the oxide formation in annealing, the buried-

Fig. 2. SEM picture of the DSOI device. Good formation of

buried oxide and smooth transition region can be clearly seen.

Selective Oxygen Implantation

Thermal Oxide as Mask(a)High Temperature Annealing

And Buried Oxide Formation

Smooth transition region

(b)

n+ n+n- n-

Conventional CMOS Technology

Bend of

Gate

Window for body-contact

(c)

Fig. 1. (a)–(c) DSOI device and its fabrication. The floating-body effect is eliminated and the self-heating effect is greatly reduced.

1062 P. He et al. / Solid-State Electronics 47 (2003) 1061–1067

oxide will shrink a little at the edge. This indicates that

the proposed technology can be applied to devices with

much smaller gate length. The source and drain regions

with buried-oxide under it are slightly raised due to the

volume expansion during the oxide formation. But the

transition is smooth. The results of device simulation [6]

show that the existence of the transition region will de-

crease the electrical field near the source and drain edges.

The field lowering at the source end will decrease the

current density with source gate voltages and will in-

crease the parasitic resistance of the shallow junction.

On the other hand field lowering at the drain region is

beneficial to the device reliability and increase the

breakdown voltage. The later is also beneficial to device

for high speed and high power applications. The source

drain elevation shown in Fig. 2 is not so serious as ex-

pected. In fact, during the oxygen implantation, some of

the top silicon film is sacrificed due to oxidation. And

during the annealing process, if the thermal oxide mask

is not removed, some of the top silicon film on source

and drain regions will be sacrificed because of oxygen

existence in the annealing gas. Therefore the elevation of

the implanted region can be technically controlled up to

fully elimination by fairly process design and control.

Source/drain elevation is useful for very short channel

devices to reduce the contact resistance, hence above

result has practical meaning.

3.2. Characteristics and performance

The threshold characteristics and measured threshold

voltage shifts of three kinds of devices with W =L of 30/

0.6 are shown in Fig. 3. The thickness for the silicon film

and buried-oxide is 300 and 90 nm before the CMOS

processes. Under these conditions the SOI devices are

working in the partially depleted state. And this is for all

the test results below. From Fig. 3 we can see that the

DIBL of DSOI is greatly suppressed compared to SOI

device due to the elimination of the floating-body effect

and is even better than the bulk device because of the

elevated drain and source. For amplifying the described

effect a large Vds ¼ 3 V is used here for DVth measure-

ment. Since the CMOS device technology is not opti-

mized here, the DIBL effect is quite larger even for the

bulk device, but the improvement of DSOI still confirms

us its advantage over SOI. Fig. 4 shows the measured

DVth vs. gate length for three different kinds of devices.

The comparison of the BVDSS vs. gate length for three

kinds of devices is shown in Fig. 5 in which significant

improvement of BVDSS of DSOI from SOI can be seen.

The fact that BVDSS of the DSOI devices is even larger

than the bulk devices can be considered as a result of the

raised drain and source.

The output characteristics of the DSOI and SOI de-

vices are shown in Fig. 6. At low gate voltages, the drive

current of the DSOI is a little smaller than that of the

SOI device. This is caused by the bending of the gate of

DSOI. At higher gate and drain voltages, the drive

current of the SOI device is reduced by the self-heating

effect and is lower than that corresponding to DSOI

device, for which self-heating effect is less important. To

clearly demonstrate the impact of the buried oxide to

self-heating effect the working temperature of three

kinds of devices is measured using the method in Ref.

[7], the corresponding result is shown in Fig. 7. It can be

seen that, though the buried oxide is quite thin (90 nm),

Fig. 3. Comparison of the DIBL effect of three kinds of devices. The DIBL effect of the DSOI devices is greatly reduced.

P. He et al. / Solid-State Electronics 47 (2003) 1061–1067 1063

temperature difference between devices is still quite sig-

nificant. With the buried oxide under the channel to be

removed, the working temperature of DSOI device is

obviously lower than that of SOI device and is close to

that of bulk device. Larger thermal resistance associated

with relatively thin buried oxide film partly can be

contributed to the existence of large interface thermal

resistance of Si and SiO2 interface [2].

The gate delays of the NMOS inverter are measured

by use of 101-stage ring oscillators of different devices on

the same chip. The results are shown in Fig. 8. Since the

BVDSS of SOI devices is low, the supply voltage to SOI

devices is set below 4 V. But the supply voltage for DSOI

and bulk devices can be raised to quite a high level. It

can be seen that the gate delay of DSOI device is much

smaller than bulk devices and is only a little bit larger

0.5 0.6 0.7 0.8 0.9 1.0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V ds=0.05 ,3 V

Vth (

V)

Gate Length ( m )

BULK DSOI SOI∆

µ

Fig. 4. Comparison of the DIBL effect vs. gate length of three kinds of devices. The DIBL effect of the DSOI devices is greatly reduced.

1 1 00

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

W = 30 m

BV

DS

S(V

)

G a te L e n gth ( m)

BULK DSOI SOI

µ

µ

Fig. 5. Comparison of the BVDSS of three kinds of devices. The BVDSS of the DSOI devices is greatly increased.

1064 P. He et al. / Solid-State Electronics 47 (2003) 1061–1067

than that of SOI devices at same supply voltage. And

when the supply voltage of DSOI devices increases, the

gate delay can decrease steady until a value much

smaller than that can be achieved by SOI devices. This

implies that DSOI device is useful in high speed and

high voltage applications. It should be noted that the

advantage of the ultimate delay of DSOI over SOI

shown in Fig. 8. The reason is that the inverter used is a

saturation loaded n-type which limits the real working

gate voltage of the drive devices. In other words, the

0 2 4 60

200

400

600

800

V gs=V th

se lf- heating effect

Lm ask=0.6 Wmask= 30

Vgs from Vth to Vth+ 6VStep 1V

Ids

(A

/m

)

V ds (V )

DSOI SOI

µ µµ

µ

Fig. 6. Comparison of output characteristics of DSOI and SOI device. At high gate and drain voltages, the drive currents of the SOI

devices are greatly reduced due to the self-heating effects.

0 10 20 30 40 50 60300

320

340

360

380

400

Tem

pe

ratu

re (

K)

Po wer (mW)

BULK DSOI SOI

Fig. 7. Comparison of working temperature of three kinds of devices with W =L ¼ 0:6. The working temperature of DSOI device is

obviously lower than that of SOI device and is close to that of bulk device.

P. He et al. / Solid-State Electronics 47 (2003) 1061–1067 1065

ultimate delay of DSOI of Fig. 8 corresponds much more

low VDS rather than possible higher values. Further, since

the DSOI device is not optimized, the parasitic resistance

of shallow junction may introduce much delay. We ex-

pect by use of CMOS inverter and good optimized DSOI

device structure, the performance of DSOI at high volt-

age can be made much higher than what SOI can achieve.

4. Conclusions and discussion

Based on the local SIMOX technology, DSOI

structure is realized and is successfully integrated with

SOI and bulk devices on a single die. Regular charac-

teristics and performance of either devices resulted in

experiments show that the proposed process of low dose,

low energy localized silicon ion implanted oxide tech-

nology is applicable for the project. Although the tech-

nology used is far from optimized, test results clearly

show that the floating-body effect and self-heating effect

of DSOI are overcome in DSOI structure. Due to the

expansion of the SiO2, the source and drain region is

slightly raised and a smooth transition regions is ob-

served between the oxide and the bulk silicon. The

performance of the device will be deteriorated a bit by

existence of this transition region, but the reliability is

increased. It is possible to control and eliminate the el-

evation of the implanted oxide region by process regu-

lation. We can use this ‘‘self’’ source and drain elevation

technique in benefit of device characteristics and per-

formance. The success of integrating DSOI, SOI and

bulk devices on a single die makes integrating low

voltage and low power devices and high voltage high

power devices of high speed on a single die possible. The

highest performance of the DSOI devices should be

much higher than its bulk and SOI counterparts due to

the reduced drain and source parasitic capacitance and

use of possible higher supply voltage. This work only

shows the possible advantage of the proposed technol-

ogy. For pushing forward this technology to practical

application, a series researches are needed and rooms for

both technical and structural optimization are existing.

First, a self-aligned technology for CMOS should be

used for deeper submicron devices. Then, the optimi-

zation of the source/drain elevation, the length of the

transition region should be made. These are what we

focus in further investigation.

Acknowledgements

This work is supported by CNNSF-59995550-1 and

the Special Funds for Major State Basic Research Pro-

jects no.G2000036501.

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