use IEEE.std_logic_1164.all;use IEEE.std_logic_ARITH.all;use IEEE.std_logic_unsigned.all;entity afficheur is port(j:in std_logic_vector(3 downto 0); a: out std_logic_vector(6 downto 0)); end afficheur;architecture arch of afficheur is beginprocess(j) begin case j is when "0000" => a a a a a a a a a a a