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Exception and Interrupt Handling

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Presented by:Group#10 1. Ahmad Ibrahim Fayed. 2. Ahmad Mohamed Abd el-Fadeel. 3. Akram Ahmad Mohamed. 4. Hassan Mohamed.

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Agenda Exception handling. Interrupts. Interrupt handling schemes.

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Agenda Exception handling. Interrupts. Interrupt handling schemes.

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Exception handling What is the exception? Any event that can halt the normal sequential execution of instructions. Most exceptions have an associated software called exception handler. Handler is a software routine that executes when an exception occurs.

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ARM exceptions and modes What are the actions made by the processor when an exception occurred? 1. saves the cpsr to the spsr of the exception mode. 2. saves the pc to the lr of the exception mode. 3. sets the cpsr to the exception mode. 4. sets pc to the address of the exception handler.

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ARM exceptions and modes ARM processor has seven different exceptions: 1. Data abort. 2. Fast interrupt request(FIQ). 3. Interrupt request(IRQ). 4. Prefetch abort. 5. Software interrupt(SWI). 6. Reset. 7. Undefined instruction.

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ARM exceptions and modes

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Vector table What is the vector table? It is a table of addresses that the ARM core branches to when an exception is raised,commonly contain branch instructions of one of the following forms: 1. B 2. LDR pc, [pc, #offset] 3. LDR pc, [pc, #-0xff0] 4. MOV pc, #immediate

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Vector table

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Exception priorities

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(1)Reset exception The Reset exception is the highest priority exception and is always taken whenever it is signaled. The reset handler initializes the system, including setting up memory and caches. The reset handler must set up the stack pointers for all processor modes.

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(2)Data abort exception Data Abort exceptions occur when the memory controller or MMU indicates that an invalid memory address has been accessed. When the current code attempts to read or write to memory without the correct access permissions. An FIQ exception can be raised within a Data Abort handler since FIQ exceptions are not disabled.

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(3)Fast Interrupt Request (FIQ) FIQ exception occurs when an external peripheral sets the FIQ pin to nFIQ. An FIQ exception is the highest priority interrupt. The core disables both IRQ and FIQ exceptions on entry into the FIQ handler.

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(4)Interrupt Request (IRQ) IRQ exception occurs when an external peripheral sets the IRQ pin to nIRQ. An IRQ exception is the second-highest priority interrupt. The IRQ handler will be entered if neither an FIQ exception nor Data Abort exception occurs.

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(5)Prefetch Abort exception A Prefetch Abort exception occurs when an attempt to fetch an instruction results in a memory fault. This exception is raised when the instruction is in the execute stage of the pipeline.

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(6)Software Interrupt (SWI) SWI exception occurs when the SWI instruction is executed. The cpsr will be set to supervisor mode. If the system uses nested SWI calls, the link register r14 and spsr must be stored away before branching to the nested SWI.

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(7)Undefined Instruction exception Undefined Instruction exception occurs when an instruction not in the ARM or Thumb instruction set reaches the execute stage of the pipeline. Both the SWI instruction and Undefined Instruction have the same level of priority, since the instruction being executed cannot both be an SWI instruction and an undefined instruction.

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Link registers offsets

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Note ^ symbol !

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Agenda Exception handling. Interrupts. Interrupt handling schemes.

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Agenda Exception handling. Interrupts. Interrupt handling schemes.

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Interrupts Types of interrupts in ARM: 1. FIQ(high priority and less latency). 2. IRQ(less priority and high latency). 3. SWI(call privileged OS routines).

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Interrupt latency Interrupt latency is the interval of time from an external interrupt request signal being raised to the first fetch of an instruction of a specific interrupt service routine (ISR). How to decrease the interrupt latency? 1. Using a nested interrupt handler. 2. Using prioritization.

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Nested interrupt handler

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IRQ and FIQ exceptions 1. The processor enters a mood dependant on the interrupt 2. The previous modes cpsr is saved into the spsr of the new interrupt request mode. 3. The pc is saved in the lr of the new interrupt request mode. 4. Interrupt/s are disabledeither the IRQ or both IRQ and FIQ exceptions are disabled in the cpsr. This immediately stops another interrupt request of the same type being raised. 5. The processor branches to a specific entry in the vector table.

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IRQ

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FIQ

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Enabling IRQ and FIQ

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Disabling IRQ and FIQ

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Interrupt stack design As every mood contain a dedicated register containing the stack pointer, its clear that we can reserve a stack for each mood of the ARM processor. To design any stack we need to know two things: 1. Its location. 2. Its size(depends upon the type of handler, nested or nonnested). We can avoid stack overflow by two methods: 1. Using memory protection. 2. Calling stack check function at start of each routine.

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Interrupt stack design

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Interrupt stack implementation

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Agenda Exception handling. Interrupts. Interrupt handling schemes.

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Agenda Exception handling. Interrupts. Interrupt handling schemes.

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-The interrupts are disabled until control is returned back to the interrupted task or process. -Can only service a single interrupt at a time. -Handlers of this form are not suitable for complex embedded systems that service multiple interrupts with differing priority levels. -High interrupt latency. Non-nested Interrupt Handler

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Advantages: Easy to implement and debug Disadvantages: Cant be used to handle complex embedded systems with multiple priority interrupts. Non-nested Interrupt Handler

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- Allows for another interrupt to occur within the currently called handler. - This is achieved by re-enabling the interrupts before the handler has fully serviced the current interrupt. - For a real-time system this feature increases the complexity of the system but also improves its performance. - Protecting the context restoration from interruption, so that the next interrupt will not fill the stack (cause stack overflow) or corrupt any of the registers. Nested Interrupt Handler

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Advantages: Can enable interrupts before the servicing of an individual interrupt is complete reducing interrupt latency. Disadvantages: Does not handle prioritization of interrupts, so lower priority interrupts can block higher priority interrupts. Nested Interrupt Handler

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- Handles multiple interrupts where interrupts are filtered by priority. - Interrupts are re-enabled early on in the reentrant interrupt handler, which can reduce interrupt latency. -Should swap into SVC or system mode in order not to overwrite the return address (this will happen if any interrupt service routine performs a BL subroutine call instruction). -If interrupts are re-enabled before processing is complete and the interrupt source is not disabled, an interrupt will be immediately regenerated, leading to an infinite interrupt sequence. Reentrant Interrupt Handler

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Advantages: Handles interrupts with differing priorities. Disadvantages: Tends to be more complex. Reentrant Interrupt Handler

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- Low interrupt latency. - Both the non-nested interrupt handler and the nested interrupt handler service interrupts on a first-come-first- served basis. Prioritized Simple Interrupt Handler

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Advantages: Deterministic interrupt latency since the priority level is identified first and then the service is called after the lower-priority interrupts are masked. Disadvantages: The time taken to get to a low-priority service routine is the same as for a high-priority routine. Prioritized Simple Interrupt Handler

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- Low interrupt latency. - The prioritization simple interrupt handler tests all the interrupt to establish the highest priority. - An alternative approach is to jump early when the highest priority interrupt has been identified to a routine that will handle the masking of the lower priority interrupts and then jump again via a jump table to the appropriate ISR. - Handles higher-priority interrupts in a shorter time than lower-priority interrupts. Prioritized Standard Interrupt Handler

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Advantages: Higher-priority interrupts treated with greater urgency with no duplication of code to set external interrupt masks. Disadvantages: There is a time penalty since this handler requires two jumps, resulting in the pipeline being flushed each time a jump occurs. Prioritized Standard Interrupt Handler

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- Some of the processing is moved out of the handler into the individual ISRs. The moved code masks out the lower-priority interrupts. Each ISR will have to mask out the lower-priority interrupts for the particular priority level. - Jumps directly to the appropriate ISR. Each ISR is responsible for disabling the lower priority interrupts. Prioritized Direct Interrupt Handler

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Advantages: Uses a single jump and saves valuable cycles to go to the ISR. Disadvantages: Each ISR has a mechanism to set the external interrupt mask to stop lower-priority interrupts from halting the current ISR, which adds extra code to each ISR. Prioritized Direct Interrupt Handler

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- Lower interrupt latency. - Grouping interrupts together and forming a subset, which can then be given a priority level. - Grouping the interrupt sources together tends to reduce the complexity of the handler since it is not necessary to scan through every interrupt to determine the priority level. - If a prioritized grouped interrupt handler is well designed, it will dramatically improve overall system response times. Prioritized Grouped Interrupt Handler

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Advantages: Useful when the embedded system has to handle a large number of interrupts, and also reduces the response time since the determining of the priority level is shorter. Disadvantages: Determining how the interrupts are grouped together. Prioritized Grouped Interrupt Handler

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- Loads an ISR address from a predefined memory mapped location, which bypasses any software interrupt handler. Advantages: Reduces interrupt latency since there is only a single jump to a specific ISR. Disadvantages: Since the VIC is basically a hardware interrupt handler, the array of ISR addresses must be preprogrammed into the VIC before it is activated. VIC PL190 Based Interrupt Service Routine

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ANY QUESTIONS!

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THANKS