Example 1Program the divisor Latch for 300 baud. Assume Xin=1.8432MHz The Base Address: 0x3F8

0 RX_TX / Divisor.low

1 IER: Interrupt Enable Reg. / Divisor.high

2 IIR: Interrupt Identification Reg.

3 LCR: Line Control Reg.

4 MCR: Modem Control Reg.

5 LSR: Line Status Reg.

6 MSR: Modem Status Reg.

7 -

300*384=115200115200*16=1843200

Example 2Program the divisor Latch for 2400 baud. Assume Xin=1.8432MHz The Base Address: 0x3F8

2400*48=115200115200*16=1843200

Example 3Program 8250 for 2400 baud, 8 data bit, even parity and 1 stop bit. Assume Xin=1.8432MHz The Base Address: 0x3F8

MOV AL,80H ; Accessing DLABMOV DX,3FBH ;Line Control Register AddressOUT DX,ALMOV AX,48 ;baud=2400 115200:48=2400MOV DX,3F8H ;Low byte of DivisorOUT DX,ALMOV AL,AHINC DXOUT DX,ALMOV AL,00011011 ; DLAB,Break,Even,1 stop, 8 dataMOV DX,3FBH ;LCROUT DX,AL

Synchronous Serial Communication

Introduction to USARTIntel 8251

Serial Data Transfer Asynchronous v.s. Synchronous

— Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication — Synchronous transfer does not transfer extra bits. However, it requires clock signal

Frame

Startbit B0 B1 B2 B3 B4 B5 B6

ParityStop bits

AsynchronousData transfer

SynchronousData transfer

clk

dataB0 B1 B2 B3 B4 B5

data

(a) Serial data transmitted at the proper rate. (b) The data rate is too fast. (c) The data rate is too slow.

Serial Frame (Synchronous)

Bit 7 0 1 2 3 4 5 6 7 0

No start or stop bits, timing synchronized with special ASCIIcharacters (SYN)

Time

Synchronous Protocols

CRC

In SDLC:G(X) = x**16 + x**12 + x**5 + 1

8251 Block Diagram

8251 Registers

Mode Register

Mode Instruction (Asynchronous)

Mode Instruction (Synchronous)

Command Register

Status Register

8251 Timing

8251 USART Interface

A7A6A5A4A3A2A1

IO/M

D[7:0]

RD RDWR WRA0 C/D

CLK CLKTxCRxC

TxD

RxD

8251 RS232

Programming 8251 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Stop bits

00: invalid01: 1 bit10: 1.5 bits11: 2 bits

Parity0: odd1: even

Parity enable0: disable1: enable

Character length

00: 5 bits01: 6 bits10: 7 bits11: 8 bits

Baud Rate

00: Syn. Mode01: x1 clock10: x16 clock11: x64 clock

Programming 8251 8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enableDTR: data terminal readyRxE: receiver enableSBPRK: send break characterER: error resetRTS: request to sendIR: internal resetEH: enter hunt mode

Programming 8251 8251 status register

DSR SYNDET FE OE PE TxEMPTYRxRDY TxRDY status register

TxRDY: transmit readyRxRDY: receiver readyTxEMPTY: transmitter emptyPE: parity errorOE: overrun errorFE: framing errorSYNDET: sync. character detectedDSR: data set ready

Simple Serial I/O Procedures Read

start

Check RxRDY

Is it logic 1?

Read data register*

end

Yes

No

* This clears RxRDY

Write

start

Check TxRDY

Is it logic 1?

Write data register*

end

Yes

No

* This clears TxRDY

8251 Reset Sequence• write three successive zeros to control

address to assure writing a reset to the command register.

• write command 40h to reset (reset chip)– After the reset, 8251 expects mode

settings• write the mode settings to control

address– There after 8251 needs command

settings.• write command for command settings.

8251 Coding

• MOV DX,309h• MOV AL,0• OUT DX,AL• OUT DX,AL• OUT DX,AL• MOV AL,40h• OUT DX,AL• MOV AL,4Eh• OUT DX,AL• MOV AL,33h• OUT DX,AL

• Main:• MOV DX,300h• IN AL,DX• MOV AH,AL• MOV DX,309h

• Wait• IN AL,DX• AND AL,01• JZ Wait• MOV AL,AH• MOV DX,308h• OUT DX,AL• JMP Main