evolving large scale quantum computers travis oh …...d-wave one: first commercial sale of quantum...

$: Evolving Large Scale Quantum Computers Travis Oh …...D-Wave One: First Commercial Sale of Quantum Computing System \\Developing Applications for Classically Hard/Intractable Problems$
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Evolving Large Scale Quantum Computers

Travis Oh

D-Wave Systems Inc.

2 © Copyright 2009 D-Wave Systems Inc.

Agenda

• What is Quantum Computer?• What do we do with it?• Applications• How do we Fabricate?

confidential• 3 •

What is Quantum ComputingComputational paradigm shift from binary “bits” of information to “quantum bits”

How well can you draw the sun with black and white color?


Quantum Computing … A New Way of Harnessing Nature


Schrodinger’s Cat Lives!

A macroscopic object in two states at once

The basis of a scalable, macroscopic, quantum proce ssor

7 © Copyright 2007 D-Wave Systems, Inc.

Components Rapidly approaching atomic dimensions - natural limit

1.E+001.E+041.E+08

1.E+121.E+161.E+201.E+241.E+28

1.E+321.E+361.E+40

1 10 100 1000

Scale of Problem

1040

1032

1024

1016

108

1

Re

quire

d N

umbe

rof

Ca

lcul

atio

ns

2N

N5

Intractable

Tractable

Tractable ≡≡≡≡ PetaFLOPS (1015) computer operating for 1 year

Certain Problems Will Remain Beyond The Reach of any Classical Computers

• Simulation of quantum systems – chemistry/Bio

• Complex combinatorial optimization – AI

�Factoring large numbers – code breaking

Classical Computing systems approaching hard limits

Supercomputer Capabilities and Applications


Note: 10MW can power 10,000 homes

Above data from WIKI


The palette of quantum phenomenonHarnessing new resources

Quantum Tunneling

Allows an object to appear on the other sideof a barrier it cannot penetrate

Allows chemical reactions impossibleClassically - speeds evolution

Energy Level Quantization

Superposition

A single quantumobject can evolvealong multiple pathssimultaneously

Allows for massiveparallelism in calculation

Entanglement

Distant, unconnected events are perfectlycorrelated

More information transfer than possibleClassically - greatly improves efficiency

Teleportation

Electrons can only Exist in discrete energyStates

Go from one state to theOther without traversingIntervening space

12

0


Quantum Computers Today

D-Wave has only scalable quantum processor

TODAY: A 2 qubit gold ion trap on aluminum nitride backing. Two ions hover above the middle of the square gold trap, which measures 7.4 millimeters on a side. The ions are manipulated and entangled using microwaves fed into wires on the trap from the three thick electrodes at the lower right1. TODAY: DW-2 Rainier 500-

qubit fully controllable chip.

TODAY: A 10-qubitphotonic chip containing 10 silica waveguide interferometers with thermo-optic controlled phase shifts for photonic quantum gates. Green lines show optical waveguides; yellow components are metallic contacts. Pencil tip shown for scale2.

TODAY: World record of 14 entangled trapped ion qubits. Architecture not scalable.

Trapped ions in linear Paul trap

New trapped ion quantum chip with microwave

coupling

Photonic quantum chip

TODAY: 3-qubitentanglement has been demonstrated in superconducting qubits3.

Conventional superconducting quantum chips

Charge-based qubit

(Schoelkopf)

Flux-based qubit

(Mooij)

Phase-based qubit(Martinis)

few mµ


Processor environment

• 196 lines from room temperature to processor

• 10 kg of metal at 20 milliKelvin; more than 100x colder than interstellar space

• 1 nanoTesla in 3D across processor; 50,000x less than earth’s magnetic field

2.725 K


Footprint

• ~ 200 square feet

• Closed cycle fridge

• Consumes ~ 7.5 kW


Applications examples:

• Machine learning (connection to neural computation) : AI

• Decision problems (NP) – example: factoring (code br eaking)

• Optimization problems (NP-hard): pattern recognitio n, protein folding


Simulating even simple molecules will remain beyond the abilities of any conceivablecomputers that harness only classical information processing

D-Wave One: First Commercial Sale of Quantum Comput ing System\\Developing Applications for Classically Hard/Intractable Problems

Application Areas� Machine Learning

� Hard Optimization

� Reversible computation

� Monte Carlo

Integrated 128 Qubit Computing SystemSold to Lockheed Martin/USC ISI

Google Car Classifier DemoNeural Net Trained with D-Wave QC Processor

Benchmarking D-Wave Processor PerformanceSo far time to solution scales like nothing ever seen

Best classical solver scales exponentially with problem size

D-Wave solver scaling looks linear/sub-exponential so far

Energy Consumption in Classical Computation Prohibitive for hard problemsD-Wave processor power consumption fixed at 7.5kW (cooling cost only)


D-Wave Processor Roadmap

Fabrication



Perspectives on Historical Superconducting Fab Efforts

\\Superconducting Process is just upper wire-up layers in CMOS

CMOS cross-sectionCMOS cross-section

(300 nm)

(300 nm)

(200 nm)

(150 nm)(100 nm)

(200 nm)

1st SiO2dielectric

Silicon wafer

Thermal SiO 2

Niobium WIRA Wire2nd SiO2 dielectric

Niobium WIRB Wire

Nb BASE wire(300 nm)

CE

SIOC

WIRC

SC process cross-sectionSC process cross-section

• Superconducting process extremely simple compared t o standard CMOS

• just CMOS wire-up process (metals/dielectric stack)

• active device (Nb junction) a simple tunnel-junction .. same AlOx barrier employed in MRAM

• all elements are commodity processes in semiconductor industry

• major challenge to realizing large scale superconducting circuits are defect density,

parametric targeting and spreads, going to high yields … all solved by semiconductor industry

Superconductivity



Achieved 512-qubit level of integration in 6 years of process development

– Fully functional ∼∼∼∼50,000 Josephson junctions (active element) SFQ circuits covering 2.8mm x 2.8mm circuit

area

– Areal junction density consistent with 105 JJ/cm2; scalable to 106 JJ/cm2 and beyond for standard RSFQ design

– 6 Nb metal layers

– 1 Ti/Pt Resistor layer (Ti is adhesion layer only)

– 5 Planarized dielectric layers (SiO2)

– High-Ic VIA process (10-40mA/μm2 measured for 0.7x0.7um VIA)

– 105 VIAs and 32,000 resistors in single product die

Current D-Wave Process

\\Level of Integration

Current D-Wave Process Cross-Section

Josephson Junction

Metal

II Metal

insulator


Minimum Critical Dimensions

– 0.25 um Lines and Spaces

– 50nm overlay accuracy

– Josephson Junction (active device) 0.6um +/- 0.2um

Current D-Wave Process

\\Critical Dimensions

0.25µm

ResistorsTunnel junctionNb etches well with “F” based chemistry in RIE Etch er


Room Temperature Testing:

D-Wave utilizes Electroglas 4080 and 4090μ tools for wafer-level yield

characterization

• All wafers are tested after full processing is completed; in-situ wafer level probing

also conducted depending on learning cycle requirements (∼30 wafers per

month)

• Entire wafer lot (up to 25 200mm wafers) loaded and tested in each run

4K Test Infrastructure:

Developed cryogen-based 4K testing infrastructure capable of

testing up to 50 die per week

• Junction parametric extraction for yield analysis and spreads

within wafer and wafer-to-wafer

• Penetration depth measurements for inductance extractions and

tracking

• VIA Ic and yield for all layers

• Resistor array testing to assess module yield and variability

Test Infrastructure

\\Low Temperature Circuit Characteristics from room temp probing


PCM Wafer-Level Analysis

D-Wave utilizes extensive process characterization and monitoring

structures for electrical and visual inspection of wafer yields.

In-situ metrology tools enable wafer-level visual inspection after each step is

completed.

All parametric data assembled into wafer maps for easy known good die

selection. Useful visualization tool for yield analysis.

SEM image on the left shows a 0.25μm wire and space DAC storage inductor

(left in image) and associated demux circuitry for addressing and

programming the DAC (right in image). Image was captured during routine

in-situ inspection after BASE and JUNC steps.

Junction RnA Distribution

Wafer-Level SEM Inspection

Junction CE

0.25µm

Resistors

Wafer 20RnA@RT, Ohm*um^2 Sizing, um

17 370 386 395 393 400 17 -0.08 -0.11 -0.12 -0.1 -0.1

16 353 369 371 376 387 387 396 394 393 16 -0.01 -0.04 0 0 0 0.01 0.01 -0.02 -0.01

15 350 360 370 379 381 390 394 401 398 396 394 15 -0.14 -0.12 -0.13 -0.12 -0.11 -0.12 -0.11 -0.12 -0.1 -0.11 -0.12

14 339 348 356 366 372 381 383 392 394 393 390 389 385 14 -0.03 -0.02 -0.01 -0.02 -0.01 -0.01 0 -0.01 0 0 0 -0.02 -0.03

13 341 350 355 363 376 378 384 393 394 393 393 391 389 386 388 13 -0.13 -0.13 -0.13 -0.13 -0.13 -0.12 -0.12 -0.11 -0.12 -0.11 -0.11 -0.11 -0.12 -0.12 -0.12

12 341 344 352 363 367 373 382 386 389 387 379 385 378 378 385 12 -0.03 -0.01 -0.01 -0.02 -0.01 0 -0.01 0 0 0 0.03 0 0.01 0 -0.03

11 343 350 355 368 374 381 388 394 394 393 389 387 384 383 387 11 -0.13 -0.12 -0.11 -0.12 -0.12 -0.12 -0.12 -0.12 -0.11 -0.11 -0.1 -0.1 -0.11 -0.12 -0.15

10 341 346 326 340 369 344 379 383 387 385 384 380 376 372 382 10 -0.02 0 0.1 0.08 -0.01 0.12 0.01 0.02 0 0.01 0.01 0.01 0 0 -0.04

9 346 350 358 369 376 356 361 386 392 396 390 387 369 376 385 9 -0.14 -0.12 -0.12 -0.12 -0.12 -0.01 -0.01 -0.06 -0.11 -0.11 -0.1 -0.1 -0.06 -0.11 -0.15

8 340 350 336 301 369 370 386 N/A 386 390 335 381 370 372 381 8 -0.03 -0.01 0.07 0.24 -0.01 0.01 0 N/A 0.01 0 0.19 0 0.03 0 -0.04

7 345 353 361 368 374 383 390 392 396 394 387 382 382 378 386 7 -0.14 -0.13 -0.12 -0.12 -0.12 -0.13 -0.12 -0.12 -0.11 -0.1 -0.1 -0.1 -0.1 -0.13 -0.16

6 338 347 350 302 369 349 382 342 389 389 384 379 371 373 380 6 -0.03 -0.02 -0.01 0.23 -0.01 0.09 0 0.17 0 0.01 0.02 0.02 0.02 -0.01-0.04

5 340 351 356 365 373 381 387 392 396 394 393 383 380 379 383 5 -0.14 -0.14 -0.12 -0.12 -0.13 -0.12 -0.11 -0.11 -0.1 -0.1 -0.1 -0.1 -0.11 -0.13 -0.15

4 344 348 351 365 354 382 354 388 390 387 380 381 373 4 -0.04 -0.030 -0.02 0.06 -0.01 0.12 0.01 0 0 0 -0.01 -0.03

3 353 358 370 380 385 390 394 397 391 396 388 3 -0.15 -0.14 -0.15 -0.13 -0.12 -0.11 -0.11 -0.12 -0.12 -0.13 -0.15

2 359 367 372 377 383 389 392 392 383 2 -0.04 -0.04 -0.02 -0.01 0 0-0.01 -0.02 -0.03

1 378 381 393 394 396 1 -0.14 -0.13 -0.14 -0.14 -0.14

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Test Infrastructure

\\Wafer Yield Characterization … Choosing Known Good Die


• D-Wave has operated a world-class superconducting foundry, centrally

managed and distributed over state-of-the-art facilities in US and

British Columbia

• The fully planarized, sub-micron, multilayer process is realized on

200mm wafers with 0.5μm minimum junction sizes, and 0.25μm lines

and spaces, high-Ic sub-micron VIA, in a low temperature process

• Our process utilizes industry-standard semiconductor equipment

optimized for superconducting processing. The process also uses the

most modern tools for in-situ metrology, continuous characterization

monitoring, and operational control

Current D-Wave Process Overview

evolving large scale quantum computers travis oh …...d-wave one: first commercial sale of quantum...

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