evaluation oard for the si5321 sonet/sdh p recision … · cal_actv 3.3v 3.3v 2.5v 3.3v 3.3v 3.3v...
TRANSCRIPT
Rev. 0.4 06/02 Copyright © 2002 by Silicon Laboratories Si5321-EVB-04
Si5321-EVB
EVALUATION BOARD FOR THE Si5321 SONET/SDH PRECISION CLOCK MULTIPLIER IC
Description
The Si5321-EVB is the customer evaluation board forthe Si5321 SONET/SDH Precision Port Card Clock IC.This board is supplied to customers for evaluation of theSi5321 device. The board provides access to signalsassociated with normal operation of the device andsignals that are reserved for factory testing purposes.
Features
Single supply at either 3.3 or 2.5 V (jumper configurable)
Differential I/Os ac coupled on board
Differential inputs terminated on board
Control input signals are switch configurable
Status outputs brought out to headers for easy access.
Function Block Diagram
text
text
Si5321+
+
––
CLKIN CLKOUT
ControlInputs
StatusOutputs
ControlInput
JumperHeader
StatusOutputSignalHeader
FactoryTestInput
Header
FactoryTest
OutputHeader
FactoryTest
SerialInput
FactoryTest
SerialOutput
Pow erSupplyInput
3.3 V/2.5 VSupply
Selection
FactoryTest
AnalogOutput
CLKIN CLKOUT50
50
3.3 V or 2.5 VSupply
Si5321-EVB
2 Rev. 0.4
Functional Overview
The Si5321-EVB is the customer evaluation board forthe Si5321 SONET/SDH Precision Port Card Clock IC.It is supplied to customers for evaluation of the Si5321device. The board provides access to signalsassociated with normal operation of the device andsignals that are reserved for factory testing purposes.
Power Supply Selection and ConnectionsThe Si5321-EVB board is switch selectable foroperation using either a single 3.3 V or a single 2.5 Vsupply.
For operation using a 3.3 V supply, configure the boardas follows:
1. Remove power supply connections from the VDD and GND terminals of the board’s power connector, J3.
2. Remove the connection between VDD33 and VDD25 by removing the jumper on header JPI.
3. Set VSEL33 high by sliding the switch on the VSEL33 (JP6) to the side marked “1”.
4. Connect the power supply ground lead and 3.3 V supply lead to the GND and VDD terminals of the board’s power connector, J3.
For operation using a 2.5 V supply, configure the boardas follows:
1. Remove power supply connections from the VDD and GND terminals of the board’s power connector, J3.
2. Set VSEL33 low by sliding the switch on the VSEL33 (JP6) to the side marked “0”.
3. Connect VDD33 and VDD25 by installing a jumper between one of the 3.3 V pins and one of the 2.5 V pins on header JPI.
4. Connect the power supply ground lead and 2.5 V supply lead to the GND and VDD terminals of the board’s power connector, J3.
Power ConsumptionTypical supply current draw for the Si5321-EVB is110 mA.
Si5321 Control InputsThe control inputs to the Si5321 are each routed fromthe center pin of a SPDT switch, JP5, to the Si5321device. Additionally, the switches at JP5 are connectedto GND on one side of the switch and to VDD33 on theother side. This arrangement allows easy configurationof each input to either a high or low state. To furtherreduce the coupling of noise into the device throughthese control inputs, the signals are routed on internallayers between ground planes.
RSTN/CAL Settings for Normal Operation and Self-CalibrationThe RSTN/CAL signal is an LVTTL input to the Si5321and has an on-chip pulldown mechanism. This pin mustbe set high for normal operation of the Si5321 device.
Setting RSTN/CAL low forces the Si5321 into the resetstate. A low-to-high transition of RSTN/CAL enables thepart and initiates a self-calibration sequence.
The Si5321 device initiates self-calibration at powerup ifthe RSTN/CAL signal is held high. A self-calibration ofthe device also can be manually initiated bymomentarily pushing the RSTN/CAL switch, SWI andthen releasing.
Manually initiate self-calibration after changing the stateof either the BWSEL[1:0] control inputs or the FEC[1:0]inputs.
Whether manually initiated or automatically initiated atpowerup, the self-calibration process requires a validinput clock. If the self-calibration is initiated without avalid clock present, the device waits for a valid clockbefore completing the self-calibration. The Si5321 clockoutput is set to the lower end of the operating frequencyrange while the device waits for a valid clock. After theclock input is validated, the calibration process runs tocompletion, the device locks to the clock input, and theclock output shifts to its target frequency. Subsequentlosses of the input clock signal do not require re-calibration. If the clock input is lost after self-calibration,the device enters Digital Hold mode. When the inputclock returns, the device re-locks to the input clockwithout performing a self-calibration.
Status SignalsThe status outputs from the Si5321 device are eachrouted to one pin of a two-row header. The signals arearranged so that each signal has a ground pin adjacentto the signal pin for reference. The row of signal pins ismarked with an “S”, and the row of ground pins ismarked with a “G”.
Visible indicators are added to the LOS and CAL_ACTVsignals. The LEDs glow when the signal is active andthe LED enable switch is set to ON. The LOS LED isilluminated when the device does not recognize a validclock input. The CAL_ACTV LED is illuminated whenthe device is calibrating to an input clock.
Differential Clock Input SignalsThe differential Clock inputs to the Si5321-EVB boardare ac coupled and terminated on the board at alocation near the SMA input connectors. Thetermination components are located on the top side ofthe board. The termination circuit consists of two 50
Si5321-EVB
Rev. 0.4 3
and a 0.1 F capacitor, such that the positive andnegative inputs of the differential pair each see a 50 termination to “ac ground,” and the line-to-linetermination impedance is 100 .
For single-ended operation, supply a signal to one ofthe differential inputs (usually the positive input). Theother input should be shorted to ground using an SMAshorting plug. The on-board termination circuit providesa 50 termination to ac-ground for each leg of thedifferential pair.
Differential Clock Output SignalsThe differential clock outputs from the Si5321 deviceare routed to the perimeter of the circuit board using50 transmission line structures. The capacitors thatprovide ac-coupling are located near the clock outputSMA connectors.
Internal Regulator CompensationThe Si5321-EVB contains pad locations for a resistorand a capacitor between the VDD25 node and ground.The resistor pads are populated with a 0 resistor. Thecapacitor pads are populated with a low ESR 33 Ftantalum capacitor. This is the suggested compensationcircuit for Si5321 devices.
There are two considerations for selecting thiscombination of compensation resistor and capacitor.First, is the stability of the regulator. The second is noisefiltering.
The acceptable range for the time constant at this nodeis 15 s to 50 s. The capacitor used on the board is a33 F capacitor with an ESR of .8 . This yields a timeconstant of 26.4 s. The designer could decide to use a330 F capacitor with an ESR of .15 . This yields atime constant of 49.5 s. Each of these cases provide acompensation circuit that makes the output of theregulator stable.
The second issue is noise filtering. For this, morecapacitance is usually better. For the two casesdescribed above, the 330 F case provides greaternoise filtering. However, the large case size of the330 F capacitor might make it impractical for manyapplications. The Si5321 device is specified with the33 F cap.
Default Jumper SettingsThe default jumper settings for the Si5321-EVB boardare given in Table 1. These settings configure the boardfor operation from a 3.3 V supply.
Table 1. Si5321-EVB Assembly Rev B-01 Default Jumper/Switch Settings
Location Signal State Notes
JP6 VSEL33 1 Internal Regulator enabled
JP1 VDD33 Open 3.3 V plane not connected to 2.5 V plane
JP5 VALTIME 0 100 ms Validation Time
FEC[0] 0 No FEC scaling
FEC[1] 0 No FEC scaling
FEC[2] 0 No FEC scaling
BWSEL[0] 0 Loop Filter Bandwidth = 800 Hz
BWSEL[1] 1 Loop Filter Bandwidth = 800 Hz
INFRQSEL[0] 1 Clock IN = 19.44 MHz
INFRQSEL[1] 0 Clock IN = 19.44 MHz
INFRQSEL[2] 0 Clock IN = 19.44 MHz
FRQSEL[0] 1 Clock Out = 622.08 MHz
FRQSEL[1] 1 Clock Out = 622.08 MHz
FRQSEL[2] 0 Clock Out = 622.08 MHz
BWBOOST 1 Selected bandwidth not doubled
FXDDELAY 0 Fixed Delay disabled
JP7 LED ENABLE On LED Indicators enabled
Si5321-EVB
4 Rev. 0.4
For
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D3D4D5E3E4E5
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VDD25VDD25VDD25VDD25VDD25VDD25VDD25VDD25VDD25
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Fig
ure
1.
Si5
321-
EV
B S
chem
atic
Si5321-EVB
Rev. 0.4 5
Bill of Materials
Reference Description Manufacturer Part Number
C1,C2,C3,C4,C6,C14 0.1uf, 0603 Venkel C0603X7R160-104KNEC5,C13 33uf, 3528 Venkel TA6R3TCR336KBRC7 2200pf, 0603 Venkel C0603X7R160-222KNEC8 22pf, 0603 Venkel C0603C0G500-220KNEC10,C11,C12 330uf, 7343 Venkel TA6R3TCR337KERC15,C16 Spare, 0402D1 LED, SM, green Panasonic LN1371GD2 LED, SM, red Panasonic LN1274RJP1 14x3 HEADERJP2,JP4,JP5 1x3 HEADERJP3 1x2 HEADERJP6 HEADER 3x2JP7 5x3JP8 7x2 HeaderJ1,J2,J3,J4 SMA, notch fit Johnson Components 82 SMA-S50-0-45J5 power connector, 2 pin Phoenix Contact 140-A-111-02 1729018L1 600 ohm, 1206 MURATA BLM31A601SQ1,Q2 MOS, SM, FDN337N Fairchild FDN337NR1 0, 0603 Venkel CR0603-16W-000TR3,R2 49.9, 0603 Venkel CR0603-16W-49R9FTR4,R5,R10 0, 0402 Venkel CR0402-16W-000TR6 10k, 0402 Venkel CR0402-16W-1002FTR7,R8 60.4, 0402 Venkel CR0402-16W-60R4FTR9 4.99k, 0603 Venkel CR0603-16W-4991FTSW1 101-0161 Mouser 101-0161U1 Si5321_revB Silicon Laboratories Si5321-BC
Si5321-EVB
6 Rev. 0.4
Figure 2. Si5321-EVB Top Silkscreen
Si5321-EVB
Rev. 0.4 7
Figure 3. Si5321-EVB—Layer 1, Component Side
Si5321-EVB
8 Rev. 0.4
Figure 4. Si5321-EVB—Layer 2, High Speed Signals
Si5321-EVB
Rev. 0.4 9
Figure 5. Si5321-EVB—Layer 3, GND
Si5321-EVB
10 Rev. 0.4
Figure 6. Si5321-EVB—Layer 4, VDD 2.5
Si5321-EVB
Rev. 0.4 11
Figure 7. Si5321-EVB—Layer 5, GND
Si5321-EVB
12 Rev. 0.4
Figure 8. Si5321-EVB—Layer 6, VDD 3.3
Si5321-EVB
Rev. 0.4 13
Figure 9. Si5321-EVB—Layer 7, GND
Si5321-EVB
14 Rev. 0.4
Figure 10. Si5321-EVB—Layer 8, Bottom
Si5321-EVB
Rev. 0.4 15
Figure 11. Si5321-EVB Bottom Silkscreen
Si5321-EVB
16 Rev. 0.4
Document Revision Change List
Revision 0.1 to Revision 0.4 Updated to reflect Rev. D printed circuit boards.
Default jumper settings added.
Evaluation Board Assembly Revision History
Assembly Level PCB Rev. Si5321 Rev. Assembly Notes
B-01 Rev. C Rev. B Assemble per BOM rev B-01
Si5321-EVB
Rev. 0.4 17
Notes:
DisclaimerSilicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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