ete 204 - digital electronics counters [lecture:14] instructor: sajib roy lecturer, ete, ulab
TRANSCRIPT
Counters
● A counter is a sequential circuit (aka. finitestate machine) that cycles through a fixedsequence of states.
● The state of the counter is stored in Flip-Flops.
● An n-bit counter- has n Flip-Flops
- can cycle through at most 2n states.
Summer 2012 ETE 204 - Digital Electronics 2
Counters
111 000 00100
11 01110 010
10
101 100 011
2-bit Counter
3-bit Counter
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Counters
00000
01110 010
10
101 011
2-bit Counter
using only 3 states 3-bit Counterusing only 5 states
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Binary Counters
● An n-bit binary counter is a counter that cyclesthrough all 2n states in ascending (ordescending) order.
111 000 001
3-bit Binary Counter
110 010Cycles through all 8 statesin ascending order
101 100 011
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Binary Counters: Design1.Draw a state graph that specifies the desiredsequence of the counter.
2.Construct a state table from the state graph.
One Flip-Flop for each bit in the state.
3.Derive a K-map from the state table for eachFlip-Flop input.
Select the type of Flip-Flop to be used.
4.Determine the input equation(s) for eachFlip-Flop.
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Binary Counters: Design
Example: State Table (using D FF)
Present StateNext State FF Inputs
C B A
0 0 0
C+ B+ A+ +
0 0 1
DC DB DA CharacteristicEquation:
0 0 1 0 1 0 Q+ = D
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0 7
Summer 2012 ETE 204 - Digital Electronics
Binary Counters: Design
Example: K-maps (for D FF inputs)
8Summer 2012 ETE 204 - Digital Electronics
Binary Counters: Design
Example: Circuit Diagram (using D FF)
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Binary Counters: Design
Example: State Table (using T FF)
Present State
C B A
0 0 0
0 0 1
Next State
C+ B+ A+
0 0 1
0 1 0
FF Inputs
TC TB TACharacteristic
Equation:
Q+ = T xor Q
0 1 0
0 1 1
0 1 1
1 0 0Excitation Table:
Q Q + T1 0 0 1 0 1 0 0 0
1 0 1
1 1 0
1 1 1
1 1 0
1 1 1
0 0 0
0 1 1
1 0 1
1 1 010
Summer 2012 ETE 204 - Digital Electronics
Binary Counters: Design
Example: K-maps (for T FF inputs)
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Binary Counters: Design
Example: Circuit Diagram (using T FF)
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Binary Up-Down Counters
What constraints must be placed on the U and D control signals?
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Counters: Design1.Draw a state graph that specifies the desiredsequence of the counter.
2.Construct a state table from the state graph.
One Flip-Flop for each bit in the state.
3.Derive a K-map from the state table for eachFlip-Flop input.
Select the type of Flip-Flop to be used.
4.Determine the input equation(s) for eachFlip-Flop.
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Counters: Design
Example:
Design the following counter using D Flip-Flops.
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Counters: Design
Example: State Table (using D FF)
Present StateNext State FF Inputs
C B A C+ B+ A+ DC DB DA
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
ExcitationEquation:
1 0 0
1 0 1
1 1 1
x x x
D = Q+1 1 01 1 1
x x x0 1 0 18
Summer 2012 ETE 204 - Digital Electronics
Counters: Design
Example: K-maps (for D FF inputs)
DC DB DA
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Counters: Design
Example:
Design the following counter using T Flip-Flops.
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Counters: Design
Example: State Table (using T FF)
Present StateNext State FF InputsC B A C+ B+ A+ TC TB TA
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
ExcitationEquation:
T = Q xor Q+
1 0 0
1 0 1
1 1 0
1 1 1
1 1 1
x x x
x x x
0 1 0 22
Summer 2012 ETE 204 - Digital Electronics
Counters: Design
Example: K-maps (for T FF inputs)
We could derive TC , TB , and TA directly from the state table,but it is often more convenient to plot next-state mapsshowing C+, B+, and A+ as functions of C, B, and A, and thenderive TC , TB , and TA from these maps.
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Summer 2012 ETE 204 - Digital Electronics
Counters: Design
Example: Next States (for T FF inputs)
Although the original state table for the counter is notcompletely specified, the next states of states 001, 101,and 110 have been specified in the process ofcompleting the circuit design
101 110
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Summer 2012 ETE 204 - Digital Electronics
Counters: Design
Example:
Design the following counter using JK Flip-Flops.
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Summer 2012 ETE 204 - Digital Electronics
Counters: Design
Example: Using JK Flip-Flops
Excitation Table:
Q Q+ J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
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Summer 2012 ETE 204 - Digital Electronics
Counters: Design
Example: State Table (using JK FF)
Present StateNext State FF InputsC B A C+ B+ A+ JC KC JB KB JA KA
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0 29
Summer 2012 ETE 204 - Digital Electronics
Counters: Design
Example: Circuit Diagram (using JK FF)
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Summer 2012 ETE 204 - Digital Electronics