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ENGR 212 / CSCI 3104 March, 2002

All slides except those with blue backgrounds are taken from John Wakerly’s

Stanford EE 121, Digital Design Laboratory

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Programmable Array Logic (PALs)• How beneficial is product sharing?

– Not enough to justify the extra AND array• PALs ==> fixed OR array

– Each AND gate is permanently connected to a certain OR gate.

• Example: PAL16L8

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• 10 primary inputs• 8 outputs, with 7 ANDs

per output• 1 AND for 3-state enable• 6 outputs available as

inputs– more inputs, at expense of

outputs– two-pass logic, helper terms

• Note inversion on outputs– output is complement of

sum-of-products– newer PALs have

selectable inversion

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Designing with PALs• Compare number of inputs and outputs of the

problem with available resources in the PAL.• Write equations for each output using ABEL.• Compile the ABEL program, determine

whether minimimized equations fit in the available AND terms.

• If no fit, try modifying equations or providing “helper” terms.

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“Recent” PLA’s• TI EPIC (1989)• SPLD

– Simple Programmable Logic Design• PLA – Programmable Logic Array• PAL – Programmable Logic Array• GAL – Generic Array Logic

• Programmable Logic FAQ

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Decoders• General decoder structure

• Typically n inputs, 2n outputs– 2-to-4, 3-to-8, 4-to-16, etc.– with a few enable inputs

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Binary 2-to-4 decoder

Note “x” (don’t care) notation.

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MSI 2-to-4 decoder

• Input buffering (less load)• NAND gates (faster)

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Decoder Symbol

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3-to-8 decoder

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74x138 3-to-8-decoder symbol

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Decoder cascading

4-to-16 decoder

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More cascading

5-to-32 decoder

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ABEL / PAL Version of 74x138module Z74X138

title '74x138 Decoder PLD J. Wakerly, Stanford University‘

"Z74X138 device 'P16L8';

" Input pins

A, B, C, !G2A, !G2B, G1 pin 1, 2, 3, 4, 5, 6;

" Output pins

!Y0, !Y1, !Y2, !Y3 pin 19, 18, 17, 16 istype 'com'; !Y4, !Y5, !Y6, !Y7 pin 15, 14, 13, 12 istype 'com';

" Constant expressionENB = G1 & G2A & G2B;

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ABEL decoder program (continuedequationsY0 = ENB & !C & !B & !A; Y1 = ENB & !C & !B & A; Y2 = ENB & !C & B & !A; Y3 = ENB & !C & B & A; Y4 = ENB & C & !B & !A; Y5 = ENB & C & !B & A; Y6 = ENB & C & B & !A; Y7 = ENB & C & B & A;

end Z74X138

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Decoder applications• Microprocessor memory systems

– selecting different banks of memory• Microprocessor input/output systems

– selecting different devices• Microprocessor instruction decoding

– enabling different functional units• Memory chips

– enabling different rows of memory depending on address

• Lots of other applications

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Encoders vs. Decoders

Decoder Encoder

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Binary encoders

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Need priority in most applications

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8-input priority encoder

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Priority-encoder logic equations

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74x148 8-input priority encoder

– Active-low I/O– Enable Input– “Got Something”– Enable Output

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74x148circuit

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74x148 Truth Table

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Cascading priority encoders

• 32-inputpriority encoder

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Multiplexers

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74x1518-input

multiplexer

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74x151 truth table

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Easy ABEL multiplexer codemodule mux4in8b title '4-input, 8-bit wide multiplexer PLD J. Wakerly, Stanford University'

" Input and output pins !G pin; " Output enableS1..S0 pin; " Select inputsA1..A8, B1..B8, C1..C8, D1..D8 pin; " input busesY1..Y8 pin istype 'com'; " three-state output bus

" SetsSEL = [S1..S0];A = [A1..A8];B = [B1..B8];C = [C1..C8];D = [D1..D8];Y = [Y1..Y8];

equations

Y.OE = G; “ support variesWHEN (SEL == 0) THEN Y = A;ELSE WHEN (SEL == 1) THEN Y = B;ELSE WHEN (SEL == 2) THEN Y = C;ELSE WHEN (SEL == 3) THEN Y = D;

end mux4in8b

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CMOS transmission gates

• 2-input multiplexer

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Three-state buffers• Output = LOW, HIGH, or Hi-Z.

• Can tie multiple outputs together, if at most one at a time is driven.

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Different flavors

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Timing considerations

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Three-state drivers

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Driver application

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Three-state transceiver

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Barrel shifter design example• n data inputs, n data outputs• Control inputs specify number of positions to

rotate or shift data inputs• Example: n = 16

– DIN[15:0], DOUT[15:0], S[3:0] (shift amount)• Many possible solutions, all based on

multiplexers

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2-input XOR gates• Like an OR gate, but excludes the case

where both inputs are 1.

• XNOR: complement of XOR

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XOR and XNOR symbols

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Gate-level XOR circuits• No direct realization with just a few transistors.

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CMOS XOR with transmission gates

IF B==1 THEN Z = !A;ELSE Z = A;

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Parity tree• Faster with balanced tree structure

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Comparators• Not Op Amps• Inputs

– Pairs of n-bit numbers• Outputs

– Results of comparison• GT, EQ, LT

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ALU• Usual inputs

– Pairs of N-bit words– Control inputs

• Typical functions– Arithmetic ops

• Add, Subtract– Logical ops

• Bit-wise AND, OR, NOT, XOR

• Can be used in slices• 74181