engineering project recommendations(23)

8/8/2019 Engineering Project Recommendations(23)

1/13

Engineering Project

Recommendations (23)

http://www.chineseowl.idv.tw
http://www.chineseowl.idv.tw/http://www.chineseowl.idv.tw/


2/13

?

:?

?

?

?

?

?

? ?


3/13

( :) During our most recent board meeting,participants expressed concern over the current trend indeteriorating quality of several passive optical network (PN)related services such as in video and FTP. PNsplay an increasingly significant role in fiber to the x networks,

e.g., fiber to the home (FTTH) and fiber to the building (FTTB). APON specified by G.983.1 comprises an optical line terminal(OLT) connected to multiple optical network terminals (ONTs) ina point-to-multi-point network. A PON network is characterizedby its ability to share upstream bandwidth between OLT andONTs. The bandwidth between OLT and ONTs. The OLT is

responsible for allocating bandwidth to the ONTs on trafficcontracts. The OLT should devise a dynamic bandwidthallocation (DBA) method to allocate bandwidth dynamically, thusresponding effectively to the dynamic changes in traffic demandfor vaious ONTs to the network resources efficiently.


4/13

( :) However, the conventional DBA is based on queue-status reports (SR) sent by ONTs to OLT periodically. The grantscheduler at the OLT defines a granting cycle W. During each Wperiod, the OLT solicits the queue-status reports from ONTs; the ONTsrespond with queue-status reports; and, then, the grant schedulerprocesses these reports and assigns bandwidth for the next W

period. The SR delay time, OLT processing time, and PON round-triptime determine the minimal response time. During this period, thequeue status changes, often causing SR-DBA to fall below optimalaccuracy. In addition to bandwidth efficiency, SR-DBA deploymentheavily depends on interoperability between OLT and ONTsystems. Specifically, the complexity of ONTs increases due to thehigher real-time constraints and additional circuitry required to supportqueue-status reports. For instance, SR-DBA isinefficient under varying traffic conditions. For instance, the overallbandwidth utilization remains under 80% and the packet delay usuallyexceeds 4 ms. SR-DBA also implies high buffer requirements over 4MB and a high packet loss ratio exceeding 5%.


5/13

( :) SR-DBA is inefficient for FTTH,creating a situation in which inefficient bandwidth utilizationexpends a considerable amount of investment in PONnetworks. Additional resources are necessary to achievethe required bandwidth. Additionally, delay-sensitive

services such as voice or interactive services cannotcomply with standard requirements under a high packetdelay. Moreover, users can not wait for a response fromthe peer for a long delay time. High buffer requirementsalso imply high overhead costs for a service provider and,

ultimately, high subscription charges for users. In sum, ahigh packet loss cannot satisfy the service level agreementand deteriorate the quality of several services such as invideo and FTP.


6/13

(:) Therefore, we recommend developing a predictiveDBA method based on pseudo status report from ONTs toincrease the DBA efficiency. The proposed method fully grantsthe excess bandwidth and grants each active ONT at least once ina W period to decrease the packet delay and increase the link

throughput. To do so, the usage pattern for ONTbandwidth can be monitored as pseudo status reports. In a periodW, the allocated bandwidth and used bandwidth of each ONT canthen be compared. Next, several parameters can be manipulatedto control the trade-off between optimizing link throughput andpacket delay. Additionally, the bandwidth in the next W period can

be predicted. Moreover, a bandwidth assignment map for the nextW period can be constructed based on these demandpredictions. Furthermore, the DBA can be fine-tuned for variousscenarios, e.g., FTTH vs. FTTC.


7/13

(:) As anticipated, the predictive DBA method can elevate thePON efficiency. While the overall bandwidth utilization can exceed 80%,the packet delay can be reduced to less than 4 ms. In addition to lowbuffer requirements under 4 MB and a low packet loss ratio notexceeding 5%, the predictive DBA method also implies bufferrequirements less than 4 MB, and an extremely low packet loss ratio

under 5%., thus satisfying requirements of delay and packet losssensitive services. Additionally, the predictive DBA method can simplifyONT design and reduce the risk of having inter-operability problemsbetween OLTs and ONTs from different vendors. Moreover, thepredictive DBA method can support not only dynamic bandwidthallocation, but also a static one that is used for fixed bandwidth trafficsuch as voice and leased line traffic such as voice and leased line traffic.Furthermore, the proposed method can contain several parameters thatnot only control the trade-off between throughput optimization and packetdelay optimization, but also provide the ability to fine tune the DBA forvarious scenarios. The predictive DBA method can also be usedaccurately reflect a certain level of fairness among ONTs by determiningthe effective traffic rate and packet delay.


8/13

(:) Importantly, the proposed predictive DBAmethod can be more efficient than SR-DBA with respect toincreasing the PON efficiency in order to reduce the amountof equipment in PON systems The proposed method canalso reduce overhead costs of the service providers

implementing PON networks., ultimately making nextgeneration network services less expensive and of highquality.


9/13


10/13

( :) For instance, the likelihood of success inhardware design at ABC Company using the conventional method isroughly 50%. Therefore, ABC Company mandates that two teamsprocess the same hardware design, resulting in at least one teamexperiencing success. Given the competition between the two teamsto succeed, more hardware components are added to ensure sufficient

hardware computational power in order to comply with productrequirements. Such tendency increases hardware costs and powerconsumption. Power consumption is essential hand-held devices giventhat batteries are the power resource of such devices. An excessive amount of human resources expended in hardwaredesign lowers the success probability below 100%. Additionally,success probability varies according to knowledge expertise of thedesigners. Given the inability to reduce high hardware costs, manyredundant hardware components are added owing to the impossibilityof ensuring sufficient computational power, ultimately resulting in thefailure of hand-held devices owing to battery constraints.


11/13

(:) Therefore, we recommend developing a novel method todetermine whether hardware deign complies with minimum productrequirements and ensure that the hardware design contains no redundanthardware components. To do so, the hardware cycle can besimulated accurately. SystemC is a C++ class library method to create a cycle-accurate model of hardware architecture, as well as interfaces of System On aChip (SoC). Therefore, SystemC can be adopted as the simulatorlanguage. For instance, if designers want to design hardware such as aMPEG4 decoder, the hardware can be simulated by writing the system usingSystemC. Designers can then fee the MPEG4 data to the simulator andevaluate whether the computational power is sufficient to comply with productrequirements, e.g., 30 frames per second. Next, if the computational power issufficient, redundant hardware components can be removed. If computationalpower is insufficient, some hardware components, e.g., digital signal

processors (DSPs), can be added to increase the computational power. Thecomputational power can be evaluated again until the minimum number ofhardware components can be used to conform to productrequirements. Additionally, the power consumption model can be incorporatedinto a simulator to evaluate power consumption.


12/13

(:) As anticipated, the proposed method can minimizehardware costs because minimal hardware components are used tocomply with product requirements; hence, the success probabilityapproaches 100%. Adding or removing hardware components in asimulator is easier than doing so in actual hardware, thus reducing thetime needed to verify the completeness and performance of hardware

significantly. Moreover, the added power consumption model can helpdesigners to design higher power-saving hand-held devices. Importantly, the proposed method can orient hardware designers onhardware functions, performance and power-consumption. Additionally,companies can minimize hardware overhead costs and reduce thetime-to-market delivery period. Furthermore, the proposed method cancontribute to efforts of hardware architecture researchers attempting toidentify hardware architecture that performs optimally and saves power.


13/13

Further details can be found at

http://www.chineseowl.idv.tw
http://www.chineseowl.idv.tw/http://www.chineseowl.idv.tw/

engineering project recommendations(23)

Documents