energy harvesting system

2552 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 12, DECEMBER 2005

A Fully Integrated Low-Power BPSK Demodulatorfor Implantable Medical DevicesYamu Hu, Student Member, IEEE, and Mohamad Sawan, Fellow, IEEE

Abstract—During the past decades, research has progressed onthe biomedical implantable electronic devices that require powerand data communication through wireless inductive links. In thispaper, we present a fully integrated binary phase-shift keying(BPSK) demodulator, which is based on a hard-limited COSTASloop topology, dedicated to such implantable medical devices. Theexperimental results of the proposed demodulator show a datatransmission rate of 1.12 Mbps, less than 0.7 mW consumptionunder a supply voltage of 1.8 V, and silicon area of 0.2 mm2 in theTaiwan Semiconductor Manufacturing Company (TSMC) CMOS0.18- m technology. The transmitter satisfies the requirementof applications relative to high forward-transferring data rate,such as cortical stimulation. Moreover, the employment of BPSKdemodulation along with a passive modulation method allowsfull-duplex data communication between an external controllerand the implantable device, which may improve the controllabilityand observability of the overall implanted system.

Index Terms—Binary phase-shift keying (BPSK) demodulator,biotelemetry, COSTAS loop, electronic implant, inductive link,wireless data transmitter.

I. INTRODUCTION

WITH the rapid development of microelectronics duringthe last ten years, high performance implantable elec-

tronic devices (sensors and neuromuscular stimulators) play anincreasingly important role in modern medical treatments [1].Inductive links have been widely used in functional electricalstimulation (FES) [2]–[5] and neural signal recording (NSR)applications [6]–[8] to provide power to the implantable device.Meanwhile, the link is also employed as a media to transmit databetween the external controller and the implanted unit. Fig. 1presents a block diagram of such a system using the inductivelink.

Generally, the external controller needs sending commandsand stimulation data to the implant. The desired transmissionrate is dependent on different applications, varied from a fewkilobits per second (kbps) (command data package) to severalmegabits per second (Mbps) (stimulation data in visual pros-thesis). On the other hand, the monitored data, such as nervesignals, are required to be sent to the external controller from

Manuscript received February 1, 2005; revised August 1, 2005. This workwas supported by the Natural Sciences and Engineering Research Council ofCanada and the Canadian Research Chair on Smart Medical Devices. This paperwas recommended by Guest Editor T. S. Lande.

Y. Hu was with the Polystim Neurotechnologies Laboratory, Department ofElectrical Engineering, École Polytechnique de Montréal, Montréal, QC H3C3A7, Canada. He is now with Texas Instruments, Dallas, TX 75243 USA.

M. Sawan is with the Polystim Neurotechnologies Laboratory, Department ofElectrical Engineering, École Polytechnique de Montréal, Montréal, QC H3C3A7, Canada (e-mail: [email protected]).

Digital Object Identifier 10.1109/TCSI.2005.858163

Fig. 1. Inductive link to transmit power/data.

the implantable device in NSR applications. In the remainingsections, we refer to the data transmission from the externalcontroller to the implant as downlink, and the data transmissionfrom the implant to the external controller as uplink. Realizingbidirectional data transmission between the two parts has be-come a trend in state-of-the-art biotelemetry systems. This is be-cause the backward information can serve for several purposes.

1) Improved controllability: Bidirectional data communica-tion provides a means of in situ confirmation of systemstatus, which allows the external controller to make ad-justment according to the implant status. This may alsoimprove the safety of the patient, prevent the overheatingof the system by monitoring the on-site temperature.

2) In-vivo measurement: For instance, with the knowledgeof programmed current, the end-of-phase voltage will pro-vide a means of estimating the tissue complex impedance.Also, electroneurogram recording technique [1] has beenproposed and used to enhance diseased bladder functions.

Furthermore, full-duplex transmission mode is desirable forthe reasons that it makes it possible to monitor and control theimplantable system in real-time. In addition, it simplifies theprotocol control circuitry and can increase the data transmissionspeed by reducing the time of handshaking.

During the past ten years, few novel circuits and systemtopologies on the inductive link have been reported [2]–[10].Table I presents major data communication characteristicsof these main works. In [2], the authors reported a 100-elec-trode neurostimulation application-specific integrated circuit.

1057-7122/$20.00 © 2005 IEEE

HU AND SAWAN: BPSK DEMODULATOR FOR IMPLANTABLE MEDICAL DEVICES 2553

TABLE IMAIN CHARACTERISTICS OF REPORTED INDUCTIVE LINK SYSTEM

Data of stimulation are delivered by a “sequence” of data,which contains a series of “packet bursts.” Each packet bursthas a beginning and an end whereby fixed carrier frequencypulses commence and cease, respectively. Each packet burstis separated in time by a “silent” period or “packet burst gap”wherein no pulses are present. The authors of [3] introduced aneural-stimulus chip with telemetry unit for retinal prostheticdevice. The data are processed by a pulsewidth modulation cir-cuit and subsequently modulated onto a radio-frequency carrierusing amplitude-shift keying (ASK) technique. The data ratevaries between 25 and 250 kbps with 1 to 10 MHz carrier fre-quency. Gudnason et al. [4] described a chip for a multichannelneural stimulator for FES. The data signal is encoded by a pulseamplitude modulation of the carrier with on–off keying (OOK).The data rate has been set to 100 kbps with a carrier frequencyof 5 MHz. Smith et al. [5] described an integrated stimulatorand telemetry system with bidirectional data communication,which is dedicated to the functional neuromuscular stimulation(FNS) applications. Commands are transmitted into the implantby means of OOK, and sampled data is sent out of the implantusing load-shift keying (LSK). This configuration is capableof reliably transmitting data bytes at rates of 200 kbps witha carrier frequency of 6.78 MHz. Akin et al. [6] reported afully integrated wireless multichannel neural recording systemusing amplitude modulation. Data are encoded using a variablepulse-width modulation technique with a data transmission rateof 125 kbps at a carrier frequency of 4 MHz.

All of the above reported works employed ASK or OOKto transmit data between the two parts of device due to theirsimplicity. Some of them realized bidirectional communicationbut only half duplex. The ASK modulation suffers from theproblems of relatively low data transmission rate and reducedamount of transferred power to implants. Some works, whichused frequency-shift keying (FSK) [9] or phase-shift keying

(PSK) [10] as the modulation method, were also reported.Theoretically, the carrier using either one of the two modu-lation methods has constant amplitude, which may increasethe maximum amount of transferred power. And both modu-lation methods allow a full-duplex communication with LSKmodulation being used as the backward transmission method.However, FSK modulation is only applicable on the wide-bandinductive link applications [9], which requires a low qualityfactor of the resonant circuit. This leads to an inherently lowtransfer efficiency of power.

In this paper, we mainly address the implementation of afully integrated low power binary phase-shift keying (BPSK)demodulator, which is used as downlink data communication ofnarrow-band inductive link systems. Low power consumption,miniaturization, and reliability of the circuit are of our main con-cerns. This paper is organized as follows. In Section II, we firstintroduce the characteristics of narrow-band inductive link andphase-shift keying modulation. Then we describe the principleof BPSK demodulator and our proposed circuit implementationin Section III. Experimental results of the prototype chip andconclusions are presented in the last sections.

II. DATA COMMUNICATION WITH NARROW-BAND

INDUCTIVE LINK

As shown in Fig. 1, the biotelemetry system consists of twocoils, one integrated in the implant, isolated in the human body,and another put close but outside the body. Since the 1970s,several works have been reported to address maximizing thegain and power-transmission efficiency of these inductive links[11]–[13]. They concluded that to have better power transfer ef-ficiency, both sides of the link could be tuned at the same reso-nant frequency. In most cases the primary circuit is tuned in se-ries to provide a low-impedance load to the driving transmitter.On the other hand, the secondary is almost invariably a parallelLC circuit to better drive a nonlinear rectifier load. Fig. 2(a) de-picts a simplified inductive link model, where represents theresistance of the voltage source (this is equal to the outputresistance of the power amplifier), represents the equivalentac resistance of load that depends on the configuration of therectifier, and represents the mutual inductance between thetwo coils of the link.

The transfer function (in Laplace domain) of the transcuta-neous link can be derived from its two network equations [14],as shown in (1) at the bottom of the page. The link behavesas a narrow-band fourth-order bandpass filter due to the exis-tence of the resonant circuitry. Fig. 2(b) presents the voltagetransfer function (magnitude and phase) at the secondary coilunder three different load resistances, with a source resistanceof 3 and coupling coefficient (defined as )of 0.07. It illustrates that the bandwidth of the link is extremelynarrow due to the high quality factor of the LC tank to increase

(1)


Fig. 2. Typical inductive link. (a) Simplified schematic. (b) Magnitude andphase transfer function.Rs = 3, coupling coefficient k = 0:07, and resonantfrequency (fr) is 13.56 MHz.

the voltage/power transfer efficiency. This narrow band imposesa challenge to design a bidirectional data transmission system,as only one carrier frequency is available in such a system. In ourapplications, a carrier with a frequency of 13.56 MHz is chosenfrom the considerations of data transfer rate, power efficiency,human safety, etc. A full-duplex bidirectional data communica-tion system, which employs PSK method as the downlink andutilizes LSK modulation as uplink data transmission method,has been proposed in [15]. LSK, which is a passive modulationmethod, has been reported in several papers [5], [16]. It utilizesthe property of inductive coupling where the impedance of theprimary coil reflects the effective secondary load. LSK mod-ulation does not need the secondary carrier frequency, and itsimplementation circuitry can be simple without using a poweramplifier, which is the most power consuming part of the trans-ceiver circuit. Through some circuit techniques, we can realizethe full-duplex data communication by extracting the two di-rectional data from the carrier’s amplitude and phase, respec-tively. In this paper, we will focus on the implementation ofthe BPSK demodulator only, since the design of an implantabledevice encounters more constraints and challenges than its ex-ternal controller.

PSK is a modulation process whereby the input signals, abinary pulse code modulation (PCM) waveform, shift the phaseof the output waveform to one of a fixed number of states.BPSK modulation shifts the carrier’s phase between 0 and180 . Fig. 3(a) presents the spectrum of the modulated signalwith a random bitstream at data rate of 1 Mbps and a carrier

frequency of 13.56 MHz. The spectrum of the modulatedcarrier is the convolution of the carrier tone with the spectrumof the data stream that contains high-order harmonics. To inves-tigate aforementioned link’s effect on the BPSK demodulation,Fig. 3(a) simultaneously gives out the spectrum of the receivedcarrier of the link. The carrier’s spectrum is bandpass shapedby the virtue of narrow-band link, as presented in Fig. 2(b).

Although the data’s high-order harmonics have been sup-pressed to a significant extent, the main lobe of signal tone isnot attenuated and input signal-to-noise ratio (SNR) is still highenough to efficiently demodulate the received signal. Assumingthat the interference coupling from external world could be ig-nored, which is reasonable due to the characteristics of closecoupling of the inductive link, the noise sources of this datatransmission channel mainly come from the thermal noise of thepower amplifier and the primary and the secondary coils’ resis-tive impedances. Simulation in Cadence shows that the overallin-band (from 10 to 20 MHz) root-mean-square (rms) noise is6.7 mV with a source resistance of 3 and coil quality factorof 100. As shown in Fig. 3(a), the main lobe of received signalis not attenuated from the input signal, which is higher than 700mV. Consequently, the input SNR of the BPSK demodulator ishigher than 40 dB. The theoretical error probability is calculatedby (2), as reported in [17], which gives a bit error rate (BER) ofless than 10 under SNR of 40 dB

(2)

where represents the function that denotes the area under thetail of the Gaussian probability density function and rep-resents the SNR here. Note that the BPSK modulated carrierstill contains a great amount of energy at the carrier frequency,as shown in Fig. 3(a). It is further amplified by the inductivelink to provide the power of the implantable system. This isone critical advantage comparing with FSK method. In fact,Fig. 3(b) presents the spectrum of the binary frequency-shiftkeying (BFSK) modulated signal with a random bitstream atdata rate of 1 Mbps and a carrier frequency of 13.56 MHz. Sinceno energy exists at the carrier frequency, which is the most effi-cient tone from the power-transferring viewpoint, all the powerhas to be recovered from the data stream bins (12.56 and 14.56MHz), which reduces the received power and deteriorates thepower efficiency to a great extent. Fig. 4(a) shows the receivedpower of the equivalent load resistance using BPSK and BFSKmodulations, respectively. Correspondingly, Fig. 4(b) gives thepower transfer efficiency, which is defined as a ratio between thecarrier’s power received from the secondary coil and modulatedsignal power sending on the primary side, of these two methods.It illustrates that using BPSK modulation is much more powerefficient than using the BFSK method under the narrow-band in-ductive link. This could be very important when power budgetis becoming a bottleneck in an implantable device.

The impact of coils movement and load impedance variationmay be of great concern. From (1), we know that the phase ofthe received signal is a function of coupling coefficient, loadimpedance. Fig. 5 shows the phase shift versus the couplingcoefficient from 0.05 to 0.09 under three equivalent resistive


Fig. 3. Spectrum of the modulated and received carriers: (a) BPSK and (b) BFSK (32 768 points fast Fourier transform analysis with data recorded from thesimulation result under Cadence environment).

Fig. 4. Power transfer under different resistive loads with a full-wave rectifier,primary carrier amplitude of 700 mV, Rs = 3 and coupling coefficient of0.07. (a) Received power and (b) transfer efficiency.

loads. We could find that the overall phase ambiguity is 37 ,which is much less than the phase difference (180 ) of BPSK.It may cause a slight increment of BER. However, it is stillhigher than using quaternary phase-shift keying (90 phasedifference).

III. PROPOSED BPSK DEMODULATOR

Since the received PSK modulated waveform is a suppressedcarrier in nature, coherent detection is required and the carrierhas to be recovered first. Several techniques, such as squaringloop, COSTAS loop, and remodulator loop, have been proposedto solve the problem [18]. Among them, the COSTAS loop isthe most often used technique due to its practical feasibility. Itconsists of two parallel phase-locked-loops (PLL), where oneis called in-phase loop and the other is called quadrature-phase

Fig. 5. Phase shift of received voltage at the secondary coil versus couplingcoefficient.

(90-phase-shift) loop [18]. Their phase error outputs are multi-plied to control the frequency of the oscillator. The square termof the data stream makes the control signal onlyproportionalto the phase difference as the conventional PLL. In the lockedstate, the output at the in-phase branch becomes the demodu-lated signal.

The main drawback of the conventional COSTAS loop BPSKdemodulators is their complexity. Normally, a four-quadrantanalog multiplier is adopted to realize the I/Q arm phase de-tector and the multiplier in the voltage-controlled oscillator(VCO) branch. Demodulation is sensitive to the input operatingpoints of each block. Present BPSK demodulators are imple-mented mostly by digital technique, including multiplication,filtering, phase shifting, and digital controlled oscillator, suchas HSP50210 manufactured by Harris. However, all digitalCOSTAS loop demodulators suffer from high power consump-tion, which is intolerable for implantable applications.

Fig. 6 presents the block diagram of our proposed BPSK de-modulator, which is inspired from digital PLLs. First, a com-parator converts the received sinusoidal carrier to the squarewaveform. This allows using two simple digital phase detec-tors in the demodulator arms. Although the analysis in [18] is


Fig. 6. Block diagram of the proposed BPSK demodulator.

based on sinusoidal input signal, it can be extended into squarewave due to the fact that the low-pass loop filters will reject the-high-order harmonics. In addition, another comparator is addedinto the lower branch, which forms a hard-limited COSTASloop. It relaxes the requirement of the center multiplier, whichwill be explained later. A fully differential architecture is ex-tensively adopted everywhere to improve circuit’s reliability,power-supply rejection ratio (PSRR), and noise immunity.

A. Phase Detector and Loop Filters

From the above analysis, we know that the key issues ofthe BPSK demodulator are to generate a square term of datastream in the control signal of VCO and to make it being onlyproportional to the phase error. There are three main digitalphase detector categories available: exclusive-OR, J-K flip-flop,and phase frequency detector (PFD). Among them, only exclu-sive-OR can be directly used here as the I/Q arm multipliers. Itcan be illustrated from the following analysis. Considering theeffects of low-pass arm filter, Fig. 7(a) and (b) gives the outputsof two arm phase detectors using exclusive-OR as

(3)

(4)

where is a constant and denotes the phase detector gain.Fig. 7(c) illustrates their multiplication (curve ), which isquite similar to the output ( ) using analog multipliers

as shown in (5). After introducing a comparator to the demodu-lator’s bottom branch, which is called a hard-limited COSTASloop [19], the phase detection output to VCO can be derived as

(5)

where represents the signum function. Their waveforms arepresented in Fig. 7(d) and (e). It is important to note that theoverall loop gain is independent of its input signal amplitudeby using the digital phase detectors along with the hard-limitedtechnique. Furthermore, the overall phase-error output of hard-limited COSTAS loop has a larger linear range (from 2 to

2) than using the analog multiplier (only around ). Thesefeatures facilitate the stability analysis and the design of thewhole feedback loop. In addition, the phase detection range ofthe hard-limited loop is enlarged twice to instead of 2 inthe previous case. On the contrary, by using the same analyticalmethod, we could find that the other two digital phase detec-tors, J-K flip-flop and PFD, cannot be employed in this loop,since their overall phase errors (I-branch phase error multipliedby Q-branch phase error) are not locked at either in-phase orquadrature state at all.

As the input carrier and the output of Q-branch have been con-verted into the binary form, a fully differential exclusive-OR aswell as a chopper style multiplier used in the central multipliercan be simply realized by the same circuit based on transmissiongates (Fig. 8). The only difference between these two multipliersis their input signal level. The input at pin (Fig. 8)could be either digital format (high or low) when using I/Q phase


Fig. 7. Phase detection error (a) I-phase, (b) Q-phase, (c) overall phase error using XOR gates, (d) Q-phase, and (e) overall phase error with hard-limitation.

Fig. 8. Transmission gate-based multiplier.

detector or analog signal using central multiplier. Since this mul-tiplier only consists of eight switch transistors, no static poweris consumed in it.

On the other hand, on-chip passive first-order lag filters arechosen from the consideration of design simplicity and weakpower consumption. The value of , , and should be con-sidered from the tradeoff of data transfer rate, damping factor,and silicon area space. From the above analysis, we find thatthe hard-limited COSTAS loop is analogous to a second-orderlinear PLL using XOR as the phase detector. Its nature frequency

and damping factor are given as [18]

(6)

(7)

where and represent the gain of the phase detectorand VCO, respectively, and denotes the frequency-divisionratio. For the design of PLL, damping factor has an impor-tant influence on the dynamic performance of the loop. Ourtarget is to set it at a value between 0.707 and 1 in order toavoid oscillation and sluggish dynamic response. The nature fre-quency determines the loop’s lock-in time, which reflects the

maximum data rate of the demodulator. Choosing a high naturefrequency may decrease the damping factor. Therefore, somecompromises should be considered to obtain an optimum per-formance. Another important characteristic is the loop’s lockrange, as written in (8), which dictates the maximum deviationof center frequency of VCO

(8)

B. Fully Differential Comparator

The comparator squares up the received sinusoidal carrier,which allows the implementation of the proposed BPSK demod-ulator in the classical digital PLL method. Fig. 9 presents thecomparator [21] used in our system. Transistorsconstruct a constant- bias voltage/current generation circuit,where rgw startup circuit is not shown in the figure. The biasingloop current is produced by the gain–source voltage ( ) differ-ence between the transistors and divided by resistor

. One current sink ( and ) is put into the input stage tolimit current consumption of the comparator. Otherwise, the casemay occur where all transistors of the input stage are turned onwhen the common-mode input voltage stays around thresholdvoltage and a large amount of undesired power is consumed. As


Fig. 9. Low power consumption fully differential comparator.

Fig. 10. Circuit implementation of VCO.

the amplitude of received carrier can be higher than VDD (1.8 V)to some extent, two input transistors ( and ) are designed towork under 3.3 V, whose gate oxide thickness is enhanced. In ad-dition, the input stage is protected by an off-chip shunt regulator,which is not shown in the figure. The output stage consists oftransistors and two digital buffers. Common-modefeedback circuit is not needed here due to the employment of twofully symmetric current mirrors (transistors , ) and theinherently nonlinear characteristic of the comparator.

C. VCO and Quadrature Signals Generator

Fig. 10 shows the schematic of the implemented CMOSVCO, where labels BP, CP, and CN represent constant voltagesgenerated from a biasing circuit. The VCO mainly includes arelaxation oscillator [20] and a transconductance ( ) cell.Transistors and operate as switches, which are turnedon and off in turn in accordance with voltage potentials oftheir gate and source terminals. A linear transconductance cell,


Fig. 11. Simulated waveforms of the demodulator.

formed by transistors – and resistor , controls theoscillator’s frequency. The frequency of oscillation is given by

(9)

where represents the transconductance value and de-notes threshold voltage of transistors and . Wide-swingcurrent sources/sinks are widely used here to have a more pre-cise branch current due to less variation of drain–source voltage( ) of the mirror transistor, which improves the frequency pre-cision. In addition, their enhanced output impedances increaseoverall PSRR and common-mode rejection ratio of the oscil-lator. To facilitate investigating the proposed demodulator loop,a continuous-mode tuning method is adopted to trim the centerfrequency and VCO gain of the oscillator. Another transconduc-tance cell (transistors ) converts trimming voltageto a dc current injecting into the oscillator. As a consequence,the center frequency can be trimmed bidirectionally throughchanging the differential voltage of pins and . As illus-trated in (9), this VCO’s gain mainly relies on the transconduc-tance ( ), which can be tuned by varying biasing current ofthe cell. As shown in Fig. 10, a multiplexer formed by tran-sistors and an inverter allow this VCO being ableto work in either normal mode (selecting BP) or tuning mode(connecting with the gate of transistor ). An external cur-rent sink from a source measurement unit or a simple resistorcan be used to provide tuning current through pin Tin.

A quadrature pair of the oscillated signal can be simply ful-filled by a divide-by-two circuit in digital domain, which con-sists of only two D-flip-flops. Note that a reference with twicethe carrier frequency has to be generated in the VCO in thiscircumstance. Although it leads to approximately 40 A morecurrent consumed in the VCO, the overall power increment re-mains very small.

TABLE IISIMULATED CURRENT CONSUMPTION OF PROPOSED DEMODULATOR

Fig. 12. Microphotograph of the proposed BPSK demodulator.

Fig. 13. Measured oscillated frequency of the VCO.

Fig. 11 shows the simulated waveforms of the proposedBPSK demodulator under Cadence environment with SpectreSsimulator, where the free-running frequency of VCO is set0.5 MHz less than carrier frequency. The top three traces(1–3) represent the input data, received carrier, and squared upcarrier, respectively. Note that the quadrature-phase error (trace4) follows the input data transitions while in-phase error (trace5) stays at around half of power rails (0.9 V). The simulatedoverall power consumption is 652 W, which includes thedemodulator and front-end comparator. Table II presents theconsumed current in each subblock. It illustrates that most ofthe power is consumed in the VCO and comparators. Since the


Fig. 14. Testing setup of the proposed BPSK demodulator.

back gate of switch transistors is hooked to power rails, only afew nanoampere leakage currents are expected in multipliers.

IV. EXPERIMENTAL RESULTS

Five prototype chips of the proposed BPSK demodulatorhave been fabricated in Taiwan Semiconductor ManufacturingCompany (TSMC) 0.18- m one-poly six-metal CMOS tech-nology. An analog testing bus/multiplexer is introduced whenimplementing the demodulator, which can cut the loop andallow us to test the components separately. The micropho-tograph of the proposed BPSK demodulator is presented inFig. 12, which costs a total area of only 0.19 mm includingthe testing components. The on-chip resistors are implementedthrough unsalicided polysilicon, and the capacitors are fulfilledusing metal–insulator–metal (MIM) capacitor. Fig. 13 presentsthe measured oscillation frequency of the integrated VCOversus the control voltage as well as the simulation result. Wefind that the measured oscillation frequencies are 30% lessthan the simulated counterparts, while the variation of theVCO’s gain is in the range of 10%. The oscillator’s frequencycan be tuned from 19.5 to 21.5 MHz, rather than 27 MHz aswe designed. These variations mainly come from the processvariation when implementing the 0.6 pF on-chip capacitor(Fig. 10) and the biasing resistor. This problem can be mitigatedthrough increasing the size of capacitor at the expense ofmore power consumption. All five prototype chips give us sim-ilar results. Fig. 14 presents the testing setup of the proposedBPSK demodulator. As the frequency of the fabricated VCOcan not be tuned up to the twice of 13.56 MHz, to evaluate theperformance of our demodulator, the modulated carrier of 10MHz is adopted and provided from the pattern generator oflogic analyzer (TLA715). Through a class-E power amplifier,the amplified carrier is then transmitted to the secondary coilthrough the link with the characteristics listed in Table III.

The capacitors and are introduced here to form avoltage doubler when LSK switch is turned on. It is impor-tant to note that the received carrier at node A will be affectedby the backward LSK modulation to some extent when full

TABLE IIIPROPOSED BPSK DEMODULATOR PERFORMANCE

Fig. 15. Measured results of the prototype BPSK demodulator.

duplex communication mode is employed. The proposed BPSKdemodulator processed the received carrier from node B, andthe reference (not shown in figure) comes from the rectifieddc voltage. The loop is currently established at outside of thechip, which employs commercially available components (XOR

and flip-flop) as the phase detector and quadrature clocks gen-erator due to one internal connection problem. Fig. 15 presentsthe measured BPSK data in, data out received carrier andrecovered clock, respectively. The received carrier is probed


Fig. 16. Block scheme of the proposed on-chip frequency tuning module.

with a circled wire instead of hooking to node B directly toavoid parasitic capacitor effects on the whole detection circuit.The measurement result indicates the maximum data rate theproposed demodulator can reach is 1.12 Mbps. Note that theamplitude of the received carrier is maintained around a stablevalue when the BPSK data are transferred. The measured dataare recorded by using a digital oscilloscope (TDS7154) andpostprocessed further using MATLAB programming language.The overall power consumption of the demodulator is only610 W, where the system works under a supply voltage of1.8 V. Table II summarizes the simulation result as well as theobtained experimental result.

For future work, we know that the center frequency of theVCO (Fig. 10) is highly reliant on to the static current oftransistors (M3 and M4) and the capacitance . The absolutecapacitance value is not well controlled in CMOS technologiesbecause they are affected by the process parameter tolerances.Currently, the oscillation frequency is tuned through off-chipcomponents and only able to work under the carrier of 10MHz due to the limited tunable range. Eventually, an on-chipautomatic frequency-tuning block is desired to initialize theVCO center frequency inside the lock range of the demod-ulator and expected to work under the carrier frequency of13.56 MHz. Fig. 16 presents a block diagram of the proposedfrequency tuning block. Its principle can be explained asfollows: the carrier without modulation is sent to the implantfirst. As the conventional PLL, a phase-frequency detectorcombined with a charge pump generates a tuning voltagesignal to control the VCO. When the lock frequency andphases are detected, the final tuning voltage is restored into an8-bit register through an on-chip programmable second-ordersigma–delta analog-to-digital converter (ADC). Once locked,the PFD and charge pump will be turned off to save power. Alsothe ADC is used for recording nerve signal and monitoringsystem status [22]. Therefore, the overall power consumptionis not increased significantly due to the existence of this tuningblock. The data stored in the register will keep tuning the VCOthrough a digital-to-analog converter (DAC) and a cell.The in-lock detection is fulfilled by connecting a low-pass filterand an Schmitt trigger to the quadrature branch of the BPSKdemodulator [18].

V. CONCLUSION

We reported in this paper a novel fully integrated BPSK de-modulator based in a hard-limited COSTA loop topology, whichfeatures small integration area, low power consumption, highdata transmission rate, and easy implementation. The achieveddata transfer rate and power consumption are quite competitivewith the reported implantable ASK demodulators, and it is theo-retically more power efficient comparing with FSK modulationin narrow-band inductive link applications. Using PSK as thedownlink modulation method facilitates the design of a bidirec-tional data transmission in inductively coupled parts of med-ical devices. In addition, this BPSK demodulator is prone to bemodified as a QPSK demodulator, which is quite similar to theBPSK except needing one more multiplier and an analog ad-dition circuit. The data rate in QPSK modulation is expected todouble compared to BPSK at the expense of increasing the BER.However, the BER can be improved by introducing some com-munication encoding techniques, such as differential phase-shiftkeying . The proposed topology is intended for biomedical de-vices, ;it also can be used in other wireless applications.

ACKNOWLEDGMENT

The authors thank the Canadian Microelectronics Corpora-tion for design tools and fabrication support.

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Yamu Hu (S’03) received the B.S degree in elec-trical engineering from Huazhong University ofScience and Technology, Wuhan, China, in 1993and the M.S degree in electronics engineering fromEcole Polytechnique of Montreal, Montreal, QC,Canada, in 2000, where he is currently pursuing thePh.D degree in electronics engineering.

His research interests include low-noise low-power analog/mixed-signal ICs for biomedicalapplications and RF front-end for wireless commu-nications. He is with Texas Instruments, Dallas, TX.

Mohamad Sawan (S’88–M’89–SM’96–F’04)received the B.Sc. degree from Université Laval,Quebec, QC, Canada, in 1984 and the M.Sc. andPh.D. degrees from Université de Sherbrooke, Sher-brooke, QC, Canada, in 1986 and 1990, respectively,all in electrical engineering.

He conducted postdoctoratal training at McGillUniversity, Montreal, QC, Canada in 1991. Hejoined Ecole Polytechnique de Montréal in 1991,where he is currently a Professor in microelectronics.His scientific interests are the design and test of

mixed-signal (analog, digital, and RF) circuits and systems, digital and analogsignal processing, and modeling, design, integration, assembly, and validationof advanced wirelessly powered and controlled monitoring and measurementtechniques. These topics are oriented toward biomedical implantable devicesand telecommunications applications. He holds the Canadian Research Chairin Smart Medical Devices. He is leading the Microelectronics StrategicAlliance of Quebec. He has published more than 300 papers in peer-reviewedjournals and conference proceedings. He holds six patents. He is Editor of theMixed-Signal Letters.

Dr. Sawan is a Fellow of the Canadian Academy of Engineering. He isFounder of the Eastern Canadian IEEE Solid-State Circuits Society Chapter,the International IEEE-NEWCAS conference, cofounder of the InternationalFES Society, and Founder of the Polystim neurotechnologies laboratory, EcolePolytechnique de Montreal. He is a Distinguished Lecturer for the IEEECircuits and Systems Society. He received the Barbara Turnbull 2003 Awardfor spinal cord research, the Medal of Merit from the President of Lebanon,and the Bombardier Medal of Merit from the French Canadian Association forthe Advancement of Sciences.

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