enabling high-precision, high-performance dsp variable-precision dsp architecture
DESCRIPTION
Enabling High-Precision, High-Performance DSP Variable-Precision DSP Architecture. 2010 Technology Roadshow. Agenda. DSP system design trend Altera DSP architecture (28 nm) Summary. Key DSP Design Trend. 9-Bit Precision. Floating-point Precision. TeraFLOPs. 100 GMACs. Video - PowerPoint PPT PresentationTRANSCRIPT
© 2010 Altera Corporation—Public
Enabling High-Precision, High-Performance DSPVariable-Precision DSP Architecture
2010 Technology Roadshow
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Agenda
DSP system design trend Altera DSP architecture (28 nm) Summary
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© 2010 Altera Corporation—Public
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Key DSP Design Trend
Video Surveillance
BroadcastSystems
Wireless Basestations
Medical Imaging
Military Radar
High-PerformanceComputing
100 GMACs
9-Bit Precision
TeraFLOPs
Floating-point Precision
Applications Moving to Variable and Higher Precisions
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
High-precision DSP Applications
Military
Medical
Wireless
High-performance ComputingHigh-performance Computing
High-precision multiply accumulate
High-precision FIR filters
High-precision FFTs
Floating-point FFTs
Floating-point matrix operations
Test and Measurement
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Industry’s First Variable-precision DSP Block
Set the Precision Dial to Match Your Application
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
DSP Builder Advanced Blockset
HDL Automatically Optimized for System Clock Frequency and Latency
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
DSP Builder Advanced Blockset AdvantageBuilding a High-performance DSP Datapath
This Design Needs to Close Timing at 350 MHz.
Portion of a High-end
RadarFront-end
Design
8-Channel Polyphase FIR Filter8-Channel Polyphase FIR Filter
Complex Mixer + AdderComplex Mixer + Adder
1024-point, Radix 4, Complex FFT1024-point, Radix 4, Complex FFT
8-Channel Polyphase FIR Filter8-Channel Polyphase FIR Filter
Complex Mixer + AdderComplex Mixer + Adder
1024-point, Radix 4, Complex FFT1024-point, Radix 4, Complex FFT
8-Channel Polyphase FIR Filter8-Channel Polyphase FIR Filter
Complex Mixer + AdderComplex Mixer + Adder
1024-point, Radix 4, Complex FFT1024-point, Radix 4, Complex FFT
8-Channel Polyphase FIR Filter8-Channel Polyphase FIR Filter
Complex Mixer + AdderComplex Mixer + Adder
1024-point, Radix 4, Complex FFT1024-point, Radix 4, Complex FFT
4 Instances
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
DSP Builder Advanced Blockset Design FlowBuild the Design in MATLAB/Simulink
High-level Simulink Design Description
FIR Filter Complex Mixer/Adder
Complex FFT
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
DSP Builder Advanced Blockset Design FlowSet the Desired fMAX Within Simulink
Set fMAX Constraints Within the High-level Simulink Design Description
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Evolution of the DSP Block
Variable-precision DSP Block
DSP Half Block
DSP Half Block
Variable-precision DSP Block
Variable-precision DSP Block
Variable-precision DSP Block
72
72
72
72
32
32
32
32
64
64
64
64
72
72
72
72
Highest Performance, Highest Precision DSP (28 nm)
Eight 18x18 Multipliers (Sum)
Four 18x18 (Independent)
Stratix III/IV FPGA Stratix V FPGAStratix II FPGA
36
36
36
36
36
36
36
36
DSP Block
Eight 18x18 Multipliers (Sum)
Eight 18x18 (Independent)
High-precision Mode
Four 18x18 (Independent)
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© 2010 Altera Corporation—Public
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The First Variable-precision DSP Block
18-Bit Precision Mode
High-Precision Mode
First DSP Architecture with Two Native Precision Modes
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable-precision DSP Block18-Bit Precision Mode
X18
18
X18
18
Independent Mode
32
32
X
+_
X
18
18
18
18 Sum Mode
37
64-bit
Acc
Configurable
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable-precision DSP BlockHigh-precision Mode
27x27
X
Inp
ut
Reg
iste
r
27 Bits
27 Bits
Acc
Reg
64
Configurable
18x36
X
Inp
ut
Reg
iste
r
18 Bits
36 Bits
Acc
Reg
64
Competing 18x25 DSP Blocks are Limited to
25-Bit Data Precision Only13
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable-precision DSP BlockFloating-point Precision
Single-precision Floating-point Mantissa MultiplicationCan Be Implemented in One Variable-precision DSP Block
27x27 X
Inp
ut
Reg
iste
r
27 Bits
27 Bits
27x27 X
Inp
ut
Reg
iste
r
27 Bits
co-eff27
Acc
Reg
64Acc
Reg
64
Configurable
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable Precision with 64-Bit Cascade
64-Bit Accumulator
64-Bit Cascade Bus
64 Bits Allows for Cascading Without Loss in Precision
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable Precision with 64-Bit Cascade 18-Bit Precision Mode
X36 Bits18
18
X36 Bits18
18
X36 Bits18
18
Three Competing 18x25 DSP BlocksWould Be Required to Do This
64-Bits
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
FFTs Require High-precision Complex Multiply
∑
∑
∑
∑ ∑
∑
∑
∑x0
x2
x1
x3
X0
X1
X2
X3
∑∑
∑∑
∑∑
∑∑ ∑∑
∑∑
∑∑
∑∑x0
x2
x1
x3
X0
X1
X2
X3
18x18 Precision∑
∑
∑
∑ ∑
∑
∑
∑x0
x2
x1
x3
X0
X1
X2
X3
∑∑
∑∑
∑∑
∑∑ ∑∑
∑∑
∑∑
∑∑x0
x2
x1
x3
X0
X1
X2
X3
18x25 Precision
∑
∑
∑
∑ ∑
∑
∑
∑x0
x2
x1
x3
X0
X1
X2
X3
∑∑
∑∑
∑∑
∑∑ ∑∑
∑∑
∑∑
∑∑x0
x2
x1
x3
X0
X1
X2
X3
18x36 Precision
Data Width Increases with Each Stage;Coefficient Width Stays the Same
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable Precision with 64-Bit Cascade Efficient Complex Multiply
18x18 Complex
18x25 Complex
18x36 Complex
Competing 18x25 DSP Requires:
4 Blocks 8 Blocks4 Blocks
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable Precision with 64-Bit Cascade Floating-point Precision
OR
Single-precision Mantissa Multiplication27x27 Mode
Double-precision Mantissa Multiplication54x54 Mode
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable Precision with 64-Bit Cascade Single-precision Floating-point FFT
∑
∑
∑
∑ ∑
∑
∑
∑x0
x2
x1
x3
X0
X1
X2
X3
∑∑
∑∑
∑∑
∑∑ ∑∑
∑∑
∑∑
∑∑x0
x2
x1
x3
X0
X1
X2
X3
27x27 Complex Multiply
Eight Competing 18x25 DSP BlocksWould Be Required to Do This
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable-precision DSP AdvantageMultiplier Size Competing Single-
precision DSP Arch.
(Today)
Variable-precision DSP Arch. (28 nm )
Altera Advantage
Video processing (9x9 multiply)
One DSP block DSP block three operations
3X
Wireless RF card DUC/DDC (18x18 multiply)
One DSP block DSP block two operations
2X
Wireless channel card (High-precision complex multiply)
4 to 8 DSP blocks (precision-dependent)
3 to 4 DSP blocks (precision-dependent)
2X
Wireless channel card MIMO (Floating-point multiply)
2 DSP blocks + logic One DSP block 2X
Radar post process (Floating-point multiply)
2 DSP blocks + logic One DSP block 2X
Achieve Performance Goals Using Half the FPGA DSP Resources
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable-precision DSP Advantage
Video Processing Wireless Basestations Military Radar
FixedPrecision
⅓ DSP Resources
½ DSP Resources
½ DSP Resources
VariablePrecision
FixedPrecision
VariablePrecision
VariablePrecision
FixedPrecision
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable-precision DSP Block
Hard Pre-adder
Internal Coeff. Blocks
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Pre-adder Reduces Multiplier Count by Half
Variable-precision DSP BlockHard Pre-adder for Filters
X X X X
C0 C1 C1 C0
+
+
+
D3 D2 D1 D0
+
X
+
X
C0 C1
+
D3 D2
D0 D1X+/-
+_
X
18-bit
co-eff
18-bit
co-eff
+/-18x18
18x18
XX+/-
+_+_
XX
18-bit
co-eff
18-bit
co-eff
+/-18x18
18x18
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Variable-precision DSP BlockInternal Coefficient Register Banks
Dual, independent 18-bit or single 27-bit wide banks Both are eight registers deep Dynamic, independent register addressing Eases timing closure and eliminates external registers
01234567
18 Bits
01234567
27 Bits
OR
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Summary: Competitive
Xilinx Altera at 28 nm
Native support for 27x27 multiply mode
Variable-precision multiplier size:
27x27, 18x36, or (dual) 18x18
Efficient implementation of floating-point signal processing
Coefficient register banks within the DSP block
Efficient 18x25 complex multiply for FFTs
Accumulator size 48 bits 64 bits
Width of the cascade bus 48 bits 64 bits
Pre-adder support for symmetric filters
Support for systolic FIR filters
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© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
For More Information
Download our DSP architecture whitepaper FPGA Industry’s first variable precision DSP
architecture
Download the Stratix V FPGA handbook
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© 2010 Altera Corporation—Public
Thank You!
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