enabling envelope tracking through gan transistors · 2016. 1. 10. · epc - the leader in egan®...
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www.epc-co.com 1 EPC - The Leader in eGaN® FETs
Enabling Envelope Tracking through GaN
Transistors
Johan Strydom Ph.D.
Efficient Power Conversion Corporation
The eGaN® FET
Journey Continues
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Agenda
• Overview of Envelope Tracking
• Why eGaN® FETs for Envelope Tracking
• Maximizing Device Performance
• Experimental Results
• Summary and Current Limitations
• A Look into the Future
• Q & A
eGaN® is a registered trademark of Efficient Power Conversion Corporation
www.epc-co.com 3 EPC - The Leader in eGaN® FETs
Same average
Reference: Nujira.com website
0
2
4
6
8
10
12
2012 2013 2014 2015 2016 2017
Ex
ab
yte
s p
er
Mo
nth
Source: Cisco VNI Mobile
Data Traffic Forecast
66%
Compound
annual growth
rate (CAGR)
Why Envelope Tracking?
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Effect of PAPR
Fixed supply
Peak Power Average
Power
Output Power (dBm)
Output
Probability
Average efficiency
only 25%
PAPR = 0dB
Peak efficiency
up to 65%
Increasing PAPR
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Effect of Envelope Tracking
Envelope Tracking
Output Power (dBm)
Average efficiency
~50% (incl. ET)
Only 1/3 the losses
Average
Power
Output
Probability
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Hybrid ET Implementation
Kimball, Don, et al. "50% PAE WCDMA basestation amplifier implemented with GaN HFETs." Compound
Semiconductor Integrated Circuit Symposium, 2005. CSIC'05. IEEE. IEEE, 2005.
Can benefit from both improved efficiency and improved bandwidth
- Improves overall ET efficiency
- Simplifies Linear stage design / Removes it entirely?
- Increase linear stage BW – improved performance
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TVF TCR
VDS
Idealized Switching
IDS
VGS
VIN
ION
t
VPL
VTH
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High Frequency
eGaN FETs
eGaN® is a registered trademark of Efficient Power Conversion Corporation
BV (V)
Max.
RDS(ON) Min. Typical Charge
(pC)
Typical
Capacitance (pF)
(mΩ) Peak Id (A) (VDS = 20 V; VGS =
0 V)
EPC Part No. (VGS = 5V,
(Pulsed, 25 oC,
QG QGD QGS QOSS QRR
ID = 0.5 A) Tpulse = 300
µs) CISS COSS CRSS
EPC8004 40 125 7.5 358 31 110 493 0 45 17 0.4
EPC8007 40 160 6 302 25 97 406 0 39 14 0.3
EPC8008 40 325 2.9 177 12 67 211 0 25 8 0.2
EPC8009 65 138 7.5 380 36 116 769 0 47 17 0.4
EPC8005 65 275 3.8 218 18 77 414 0 29 9.7 0.2
EPC8002 65 530 2 141 9.4 59 244 0 21 5.9 0.1
EPC8003 100 300 5 315 34 110 1100 0 38 18 0.2
EPC8010 100 160 7.5 354 32 109 1509 0 47 18 0.2
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Hard Switching FOM
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dv/dt Immunity
EPC8004
eGaN FET
QGS1 QGD
20V 40V QGS1>QGD
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TVF
VDS IDS
VGS
VIN
ION
VPL
VTH
t
TCR
IDS
VIN
VPL
VTH
TCR TVF
VDS IDS
VGS
ION
Common Source Inductance
t
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eGaN FET SO-8 LFPAK DirectFET LGA
65
70
75
80
85
90
0.5 1 1.5 2 2.5 3 3.5
Eff
icie
ncy (
%)
Switching Frequency (MHz)
SO-8
LFPAK
DirectFET
LGA
0
0.5
1
1.5
2
2.5
SO-8 LFPAK DirectFET LGA
Po
we
r L
os
s (
W)
Device Loss Breakdown
Package
Die
18%
82%
0
0.5
1
1.5
2
2.5
SO-8 LFPAK DirectFET LGA
Po
we
r L
os
s (
W)
Device Loss Breakdown
Package
Die
18%
82%
27%
73%
0
0.5
1
1.5
2
2.5
SO-8 LFPAK DirectFET LGA
Po
we
r L
os
s (
W)
Device Loss Breakdown
Package
Die
18%
82%
27%
73%
53%
47%
0
0.5
1
1.5
2
2.5
SO-8 LFPAK DirectFET LGA
Po
we
r L
os
s (
W)
Device Loss Breakdown
Package
Die
18%
82%
27%
73%
53%
47%
82%
18%
VIN =12V
VOUT =1.2V
IOUT =20A
FS =1MHz
Drain
Source
Gate
Packaging Evolution
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3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 P
ow
er
Lo
ss(W
)
Parasitic Inductance (nH)
Power Loss vs Parasitic Inductance
Ls
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 P
ow
er
Lo
ss(W
)
Parasitic Inductance (nH)
Power Loss vs Parasitic Inductance
Ls LLoop
Cin
T
SR
LS: Common Source
Inductance VIN=12 V, VOUT=1.2 V,
fsw=1 MHz, IOUT= 20 A LLoop: High Frequency
Power Loop Inductance
Converter Parasitics
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Low Parasitic Layout
To BUS caps
Switch
node
Ground Bottom Gate
Top Gate Ga
te
Drain
Source
Sub
S
Gate
Drain Sub
S
Re
turn
R
etu
rn
Source
Gate
Current
orthogonal
to drain
current
Vias to next layer
Supply
Vias to next layer Top Layer
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Optimum gate
loop return
Optimum gate
loop return
To gate
drive
To gate
drive
Optimum power
loop return
Gate
Drain
Source
Sub
S
Gate
Drain Sub
S
Retu
rn
Re
turn
Source
Low Parasitic Layout
First InnerLayer
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ET Prototype Board
EPC80XX
Bus caps
SO-8 footprint
EPC80XX LM5113
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di/dt interval
dv/dt interval
Rise time ~1.0 ns Total switching time ~1.2 ns
2 ns/div and 10 V/div, 1 GHz 100:1 1pF TM probe
42VIN at 1AOUT
No measureable overshoot
75V/ns slew rate
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EPC8005
42VIN, 20VOUT, 10MHz
Conduction
Switching
COSS
Additional losses
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Le
ve
l S
hift
VDD VDD
IC c
ap
acita
nce
Bo
ots
tra
p d
iod
e
Reverse
recovery
charge
Switch-node
rising edge
LM5113 half-bridge driver
Parasitic Losses
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10 MHz switching, no load, large dead-time
No-load Switching
Initially slow
rising edge
Actual voltage commutation
slopes are different, even
though currents are the same
10V/div, 100mA/div, 10ns/div
Expected commutation based on
eGaN FET COSS
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Bootstrap QRR
10 MHz switching, no load, large dead-time 10V/div, 100mA/div, 10ns/div
Switch-node voltage
Actual commutation based on total
COSS – including IC capacitance
Loss Breakdown
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Conduction
Switching
COSS
42VIN, 20VOUT, 10MHz
COSS Driver
QRR Bootstrap diode
Switching
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Calculated efficiency improvement
eGaN FET Limited Efficiency
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Summary
• New devices enable higher switching frequencies
• Switching 42V, 40W at 10MHz at 89% possible
• Driver parasitics limit performance
• Doubles light load losses
www.epc-co.com 25 EPC - The Leader in eGaN® FETs
The end of the road
for silicon…..
is the beginning of
the eGaN FET
journey!